smc91c111.c 22 KB

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  1. /*
  2. * SMSC 91C111 Ethernet interface emulation
  3. *
  4. * Copyright (c) 2005 CodeSourcery, LLC.
  5. * Written by Paul Brook
  6. *
  7. * This code is licensed under the GPL
  8. */
  9. #include "sysbus.h"
  10. #include "net.h"
  11. #include "devices.h"
  12. /* For crc32 */
  13. #include <zlib.h>
  14. /* Number of 2k memory pages available. */
  15. #define NUM_PACKETS 4
  16. typedef struct {
  17. SysBusDevice busdev;
  18. NICState *nic;
  19. NICConf conf;
  20. uint16_t tcr;
  21. uint16_t rcr;
  22. uint16_t cr;
  23. uint16_t ctr;
  24. uint16_t gpr;
  25. uint16_t ptr;
  26. uint16_t ercv;
  27. qemu_irq irq;
  28. int bank;
  29. int packet_num;
  30. int tx_alloc;
  31. /* Bitmask of allocated packets. */
  32. int allocated;
  33. int tx_fifo_len;
  34. int tx_fifo[NUM_PACKETS];
  35. int rx_fifo_len;
  36. int rx_fifo[NUM_PACKETS];
  37. int tx_fifo_done_len;
  38. int tx_fifo_done[NUM_PACKETS];
  39. /* Packet buffer memory. */
  40. uint8_t data[NUM_PACKETS][2048];
  41. uint8_t int_level;
  42. uint8_t int_mask;
  43. MemoryRegion mmio;
  44. } smc91c111_state;
  45. static const VMStateDescription vmstate_smc91c111 = {
  46. .name = "smc91c111",
  47. .version_id = 1,
  48. .minimum_version_id = 1,
  49. .fields = (VMStateField []) {
  50. VMSTATE_UINT16(tcr, smc91c111_state),
  51. VMSTATE_UINT16(rcr, smc91c111_state),
  52. VMSTATE_UINT16(cr, smc91c111_state),
  53. VMSTATE_UINT16(ctr, smc91c111_state),
  54. VMSTATE_UINT16(gpr, smc91c111_state),
  55. VMSTATE_UINT16(ptr, smc91c111_state),
  56. VMSTATE_UINT16(ercv, smc91c111_state),
  57. VMSTATE_INT32(bank, smc91c111_state),
  58. VMSTATE_INT32(packet_num, smc91c111_state),
  59. VMSTATE_INT32(tx_alloc, smc91c111_state),
  60. VMSTATE_INT32(allocated, smc91c111_state),
  61. VMSTATE_INT32(tx_fifo_len, smc91c111_state),
  62. VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS),
  63. VMSTATE_INT32(rx_fifo_len, smc91c111_state),
  64. VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS),
  65. VMSTATE_INT32(tx_fifo_done_len, smc91c111_state),
  66. VMSTATE_INT32_ARRAY(tx_fifo_done, smc91c111_state, NUM_PACKETS),
  67. VMSTATE_BUFFER_UNSAFE(data, smc91c111_state, 0, NUM_PACKETS * 2048),
  68. VMSTATE_UINT8(int_level, smc91c111_state),
  69. VMSTATE_UINT8(int_mask, smc91c111_state),
  70. VMSTATE_END_OF_LIST()
  71. }
  72. };
  73. #define RCR_SOFT_RST 0x8000
  74. #define RCR_STRIP_CRC 0x0200
  75. #define RCR_RXEN 0x0100
  76. #define TCR_EPH_LOOP 0x2000
  77. #define TCR_NOCRC 0x0100
  78. #define TCR_PAD_EN 0x0080
  79. #define TCR_FORCOL 0x0004
  80. #define TCR_LOOP 0x0002
  81. #define TCR_TXEN 0x0001
  82. #define INT_MD 0x80
  83. #define INT_ERCV 0x40
  84. #define INT_EPH 0x20
  85. #define INT_RX_OVRN 0x10
  86. #define INT_ALLOC 0x08
  87. #define INT_TX_EMPTY 0x04
  88. #define INT_TX 0x02
  89. #define INT_RCV 0x01
  90. #define CTR_AUTO_RELEASE 0x0800
  91. #define CTR_RELOAD 0x0002
  92. #define CTR_STORE 0x0001
  93. #define RS_ALGNERR 0x8000
  94. #define RS_BRODCAST 0x4000
  95. #define RS_BADCRC 0x2000
  96. #define RS_ODDFRAME 0x1000
  97. #define RS_TOOLONG 0x0800
  98. #define RS_TOOSHORT 0x0400
  99. #define RS_MULTICAST 0x0001
  100. /* Update interrupt status. */
  101. static void smc91c111_update(smc91c111_state *s)
  102. {
  103. int level;
  104. if (s->tx_fifo_len == 0)
  105. s->int_level |= INT_TX_EMPTY;
  106. if (s->tx_fifo_done_len != 0)
  107. s->int_level |= INT_TX;
  108. level = (s->int_level & s->int_mask) != 0;
  109. qemu_set_irq(s->irq, level);
  110. }
  111. /* Try to allocate a packet. Returns 0x80 on failure. */
  112. static int smc91c111_allocate_packet(smc91c111_state *s)
  113. {
  114. int i;
  115. if (s->allocated == (1 << NUM_PACKETS) - 1) {
  116. return 0x80;
  117. }
  118. for (i = 0; i < NUM_PACKETS; i++) {
  119. if ((s->allocated & (1 << i)) == 0)
  120. break;
  121. }
  122. s->allocated |= 1 << i;
  123. return i;
  124. }
  125. /* Process a pending TX allocate. */
  126. static void smc91c111_tx_alloc(smc91c111_state *s)
  127. {
  128. s->tx_alloc = smc91c111_allocate_packet(s);
  129. if (s->tx_alloc == 0x80)
  130. return;
  131. s->int_level |= INT_ALLOC;
  132. smc91c111_update(s);
  133. }
  134. /* Remove and item from the RX FIFO. */
  135. static void smc91c111_pop_rx_fifo(smc91c111_state *s)
  136. {
  137. int i;
  138. s->rx_fifo_len--;
  139. if (s->rx_fifo_len) {
  140. for (i = 0; i < s->rx_fifo_len; i++)
  141. s->rx_fifo[i] = s->rx_fifo[i + 1];
  142. s->int_level |= INT_RCV;
  143. } else {
  144. s->int_level &= ~INT_RCV;
  145. }
  146. smc91c111_update(s);
  147. }
  148. /* Remove an item from the TX completion FIFO. */
  149. static void smc91c111_pop_tx_fifo_done(smc91c111_state *s)
  150. {
  151. int i;
  152. if (s->tx_fifo_done_len == 0)
  153. return;
  154. s->tx_fifo_done_len--;
  155. for (i = 0; i < s->tx_fifo_done_len; i++)
  156. s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
  157. }
  158. /* Release the memory allocated to a packet. */
  159. static void smc91c111_release_packet(smc91c111_state *s, int packet)
  160. {
  161. s->allocated &= ~(1 << packet);
  162. if (s->tx_alloc == 0x80)
  163. smc91c111_tx_alloc(s);
  164. }
  165. /* Flush the TX FIFO. */
  166. static void smc91c111_do_tx(smc91c111_state *s)
  167. {
  168. int i;
  169. int len;
  170. int control;
  171. int packetnum;
  172. uint8_t *p;
  173. if ((s->tcr & TCR_TXEN) == 0)
  174. return;
  175. if (s->tx_fifo_len == 0)
  176. return;
  177. for (i = 0; i < s->tx_fifo_len; i++) {
  178. packetnum = s->tx_fifo[i];
  179. p = &s->data[packetnum][0];
  180. /* Set status word. */
  181. *(p++) = 0x01;
  182. *(p++) = 0x40;
  183. len = *(p++);
  184. len |= ((int)*(p++)) << 8;
  185. len -= 6;
  186. control = p[len + 1];
  187. if (control & 0x20)
  188. len++;
  189. /* ??? This overwrites the data following the buffer.
  190. Don't know what real hardware does. */
  191. if (len < 64 && (s->tcr & TCR_PAD_EN)) {
  192. memset(p + len, 0, 64 - len);
  193. len = 64;
  194. }
  195. #if 0
  196. {
  197. int add_crc;
  198. /* The card is supposed to append the CRC to the frame.
  199. However none of the other network traffic has the CRC
  200. appended. Suspect this is low level ethernet detail we
  201. don't need to worry about. */
  202. add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
  203. if (add_crc) {
  204. uint32_t crc;
  205. crc = crc32(~0, p, len);
  206. memcpy(p + len, &crc, 4);
  207. len += 4;
  208. }
  209. }
  210. #endif
  211. if (s->ctr & CTR_AUTO_RELEASE)
  212. /* Race? */
  213. smc91c111_release_packet(s, packetnum);
  214. else if (s->tx_fifo_done_len < NUM_PACKETS)
  215. s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum;
  216. qemu_send_packet(&s->nic->nc, p, len);
  217. }
  218. s->tx_fifo_len = 0;
  219. smc91c111_update(s);
  220. }
  221. /* Add a packet to the TX FIFO. */
  222. static void smc91c111_queue_tx(smc91c111_state *s, int packet)
  223. {
  224. if (s->tx_fifo_len == NUM_PACKETS)
  225. return;
  226. s->tx_fifo[s->tx_fifo_len++] = packet;
  227. smc91c111_do_tx(s);
  228. }
  229. static void smc91c111_reset(DeviceState *dev)
  230. {
  231. smc91c111_state *s = FROM_SYSBUS(smc91c111_state, sysbus_from_qdev(dev));
  232. s->bank = 0;
  233. s->tx_fifo_len = 0;
  234. s->tx_fifo_done_len = 0;
  235. s->rx_fifo_len = 0;
  236. s->allocated = 0;
  237. s->packet_num = 0;
  238. s->tx_alloc = 0;
  239. s->tcr = 0;
  240. s->rcr = 0;
  241. s->cr = 0xa0b1;
  242. s->ctr = 0x1210;
  243. s->ptr = 0;
  244. s->ercv = 0x1f;
  245. s->int_level = INT_TX_EMPTY;
  246. s->int_mask = 0;
  247. smc91c111_update(s);
  248. }
  249. #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
  250. #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
  251. static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
  252. uint32_t value)
  253. {
  254. smc91c111_state *s = (smc91c111_state *)opaque;
  255. offset = offset & 0xf;
  256. if (offset == 14) {
  257. s->bank = value;
  258. return;
  259. }
  260. if (offset == 15)
  261. return;
  262. switch (s->bank) {
  263. case 0:
  264. switch (offset) {
  265. case 0: /* TCR */
  266. SET_LOW(tcr, value);
  267. return;
  268. case 1:
  269. SET_HIGH(tcr, value);
  270. return;
  271. case 4: /* RCR */
  272. SET_LOW(rcr, value);
  273. return;
  274. case 5:
  275. SET_HIGH(rcr, value);
  276. if (s->rcr & RCR_SOFT_RST)
  277. smc91c111_reset(&s->busdev.qdev);
  278. return;
  279. case 10: case 11: /* RPCR */
  280. /* Ignored */
  281. return;
  282. case 12: case 13: /* Reserved */
  283. return;
  284. }
  285. break;
  286. case 1:
  287. switch (offset) {
  288. case 0: /* CONFIG */
  289. SET_LOW(cr, value);
  290. return;
  291. case 1:
  292. SET_HIGH(cr,value);
  293. return;
  294. case 2: case 3: /* BASE */
  295. case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
  296. /* Not implemented. */
  297. return;
  298. case 10: /* Genral Purpose */
  299. SET_LOW(gpr, value);
  300. return;
  301. case 11:
  302. SET_HIGH(gpr, value);
  303. return;
  304. case 12: /* Control */
  305. if (value & 1)
  306. fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
  307. if (value & 2)
  308. fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
  309. value &= ~3;
  310. SET_LOW(ctr, value);
  311. return;
  312. case 13:
  313. SET_HIGH(ctr, value);
  314. return;
  315. }
  316. break;
  317. case 2:
  318. switch (offset) {
  319. case 0: /* MMU Command */
  320. switch (value >> 5) {
  321. case 0: /* no-op */
  322. break;
  323. case 1: /* Allocate for TX. */
  324. s->tx_alloc = 0x80;
  325. s->int_level &= ~INT_ALLOC;
  326. smc91c111_update(s);
  327. smc91c111_tx_alloc(s);
  328. break;
  329. case 2: /* Reset MMU. */
  330. s->allocated = 0;
  331. s->tx_fifo_len = 0;
  332. s->tx_fifo_done_len = 0;
  333. s->rx_fifo_len = 0;
  334. s->tx_alloc = 0;
  335. break;
  336. case 3: /* Remove from RX FIFO. */
  337. smc91c111_pop_rx_fifo(s);
  338. break;
  339. case 4: /* Remove from RX FIFO and release. */
  340. if (s->rx_fifo_len > 0) {
  341. smc91c111_release_packet(s, s->rx_fifo[0]);
  342. }
  343. smc91c111_pop_rx_fifo(s);
  344. break;
  345. case 5: /* Release. */
  346. smc91c111_release_packet(s, s->packet_num);
  347. break;
  348. case 6: /* Add to TX FIFO. */
  349. smc91c111_queue_tx(s, s->packet_num);
  350. break;
  351. case 7: /* Reset TX FIFO. */
  352. s->tx_fifo_len = 0;
  353. s->tx_fifo_done_len = 0;
  354. break;
  355. }
  356. return;
  357. case 1:
  358. /* Ignore. */
  359. return;
  360. case 2: /* Packet Number Register */
  361. s->packet_num = value;
  362. return;
  363. case 3: case 4: case 5:
  364. /* Should be readonly, but linux writes to them anyway. Ignore. */
  365. return;
  366. case 6: /* Pointer */
  367. SET_LOW(ptr, value);
  368. return;
  369. case 7:
  370. SET_HIGH(ptr, value);
  371. return;
  372. case 8: case 9: case 10: case 11: /* Data */
  373. {
  374. int p;
  375. int n;
  376. if (s->ptr & 0x8000)
  377. n = s->rx_fifo[0];
  378. else
  379. n = s->packet_num;
  380. p = s->ptr & 0x07ff;
  381. if (s->ptr & 0x4000) {
  382. s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff);
  383. } else {
  384. p += (offset & 3);
  385. }
  386. s->data[n][p] = value;
  387. }
  388. return;
  389. case 12: /* Interrupt ACK. */
  390. s->int_level &= ~(value & 0xd6);
  391. if (value & INT_TX)
  392. smc91c111_pop_tx_fifo_done(s);
  393. smc91c111_update(s);
  394. return;
  395. case 13: /* Interrupt mask. */
  396. s->int_mask = value;
  397. smc91c111_update(s);
  398. return;
  399. }
  400. break;
  401. case 3:
  402. switch (offset) {
  403. case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
  404. /* Multicast table. */
  405. /* Not implemented. */
  406. return;
  407. case 8: case 9: /* Management Interface. */
  408. /* Not implemented. */
  409. return;
  410. case 12: /* Early receive. */
  411. s->ercv = value & 0x1f;
  412. case 13:
  413. /* Ignore. */
  414. return;
  415. }
  416. break;
  417. }
  418. hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
  419. }
  420. static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
  421. {
  422. smc91c111_state *s = (smc91c111_state *)opaque;
  423. offset = offset & 0xf;
  424. if (offset == 14) {
  425. return s->bank;
  426. }
  427. if (offset == 15)
  428. return 0x33;
  429. switch (s->bank) {
  430. case 0:
  431. switch (offset) {
  432. case 0: /* TCR */
  433. return s->tcr & 0xff;
  434. case 1:
  435. return s->tcr >> 8;
  436. case 2: /* EPH Status */
  437. return 0;
  438. case 3:
  439. return 0x40;
  440. case 4: /* RCR */
  441. return s->rcr & 0xff;
  442. case 5:
  443. return s->rcr >> 8;
  444. case 6: /* Counter */
  445. case 7:
  446. /* Not implemented. */
  447. return 0;
  448. case 8: /* Memory size. */
  449. return NUM_PACKETS;
  450. case 9: /* Free memory available. */
  451. {
  452. int i;
  453. int n;
  454. n = 0;
  455. for (i = 0; i < NUM_PACKETS; i++) {
  456. if (s->allocated & (1 << i))
  457. n++;
  458. }
  459. return n;
  460. }
  461. case 10: case 11: /* RPCR */
  462. /* Not implemented. */
  463. return 0;
  464. case 12: case 13: /* Reserved */
  465. return 0;
  466. }
  467. break;
  468. case 1:
  469. switch (offset) {
  470. case 0: /* CONFIG */
  471. return s->cr & 0xff;
  472. case 1:
  473. return s->cr >> 8;
  474. case 2: case 3: /* BASE */
  475. /* Not implemented. */
  476. return 0;
  477. case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
  478. return s->conf.macaddr.a[offset - 4];
  479. case 10: /* General Purpose */
  480. return s->gpr & 0xff;
  481. case 11:
  482. return s->gpr >> 8;
  483. case 12: /* Control */
  484. return s->ctr & 0xff;
  485. case 13:
  486. return s->ctr >> 8;
  487. }
  488. break;
  489. case 2:
  490. switch (offset) {
  491. case 0: case 1: /* MMUCR Busy bit. */
  492. return 0;
  493. case 2: /* Packet Number. */
  494. return s->packet_num;
  495. case 3: /* Allocation Result. */
  496. return s->tx_alloc;
  497. case 4: /* TX FIFO */
  498. if (s->tx_fifo_done_len == 0)
  499. return 0x80;
  500. else
  501. return s->tx_fifo_done[0];
  502. case 5: /* RX FIFO */
  503. if (s->rx_fifo_len == 0)
  504. return 0x80;
  505. else
  506. return s->rx_fifo[0];
  507. case 6: /* Pointer */
  508. return s->ptr & 0xff;
  509. case 7:
  510. return (s->ptr >> 8) & 0xf7;
  511. case 8: case 9: case 10: case 11: /* Data */
  512. {
  513. int p;
  514. int n;
  515. if (s->ptr & 0x8000)
  516. n = s->rx_fifo[0];
  517. else
  518. n = s->packet_num;
  519. p = s->ptr & 0x07ff;
  520. if (s->ptr & 0x4000) {
  521. s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff);
  522. } else {
  523. p += (offset & 3);
  524. }
  525. return s->data[n][p];
  526. }
  527. case 12: /* Interrupt status. */
  528. return s->int_level;
  529. case 13: /* Interrupt mask. */
  530. return s->int_mask;
  531. }
  532. break;
  533. case 3:
  534. switch (offset) {
  535. case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
  536. /* Multicast table. */
  537. /* Not implemented. */
  538. return 0;
  539. case 8: /* Management Interface. */
  540. /* Not implemented. */
  541. return 0x30;
  542. case 9:
  543. return 0x33;
  544. case 10: /* Revision. */
  545. return 0x91;
  546. case 11:
  547. return 0x33;
  548. case 12:
  549. return s->ercv;
  550. case 13:
  551. return 0;
  552. }
  553. break;
  554. }
  555. hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset);
  556. return 0;
  557. }
  558. static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
  559. uint32_t value)
  560. {
  561. smc91c111_writeb(opaque, offset, value & 0xff);
  562. smc91c111_writeb(opaque, offset + 1, value >> 8);
  563. }
  564. static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
  565. uint32_t value)
  566. {
  567. /* 32-bit writes to offset 0xc only actually write to the bank select
  568. register (offset 0xe) */
  569. if (offset != 0xc)
  570. smc91c111_writew(opaque, offset, value & 0xffff);
  571. smc91c111_writew(opaque, offset + 2, value >> 16);
  572. }
  573. static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
  574. {
  575. uint32_t val;
  576. val = smc91c111_readb(opaque, offset);
  577. val |= smc91c111_readb(opaque, offset + 1) << 8;
  578. return val;
  579. }
  580. static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
  581. {
  582. uint32_t val;
  583. val = smc91c111_readw(opaque, offset);
  584. val |= smc91c111_readw(opaque, offset + 2) << 16;
  585. return val;
  586. }
  587. static int smc91c111_can_receive(NetClientState *nc)
  588. {
  589. smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
  590. if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
  591. return 1;
  592. if (s->allocated == (1 << NUM_PACKETS) - 1)
  593. return 0;
  594. return 1;
  595. }
  596. static ssize_t smc91c111_receive(NetClientState *nc, const uint8_t *buf, size_t size)
  597. {
  598. smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
  599. int status;
  600. int packetsize;
  601. uint32_t crc;
  602. int packetnum;
  603. uint8_t *p;
  604. if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
  605. return -1;
  606. /* Short packets are padded with zeros. Receiving a packet
  607. < 64 bytes long is considered an error condition. */
  608. if (size < 64)
  609. packetsize = 64;
  610. else
  611. packetsize = (size & ~1);
  612. packetsize += 6;
  613. crc = (s->rcr & RCR_STRIP_CRC) == 0;
  614. if (crc)
  615. packetsize += 4;
  616. /* TODO: Flag overrun and receive errors. */
  617. if (packetsize > 2048)
  618. return -1;
  619. packetnum = smc91c111_allocate_packet(s);
  620. if (packetnum == 0x80)
  621. return -1;
  622. s->rx_fifo[s->rx_fifo_len++] = packetnum;
  623. p = &s->data[packetnum][0];
  624. /* ??? Multicast packets? */
  625. status = 0;
  626. if (size > 1518)
  627. status |= RS_TOOLONG;
  628. if (size & 1)
  629. status |= RS_ODDFRAME;
  630. *(p++) = status & 0xff;
  631. *(p++) = status >> 8;
  632. *(p++) = packetsize & 0xff;
  633. *(p++) = packetsize >> 8;
  634. memcpy(p, buf, size & ~1);
  635. p += (size & ~1);
  636. /* Pad short packets. */
  637. if (size < 64) {
  638. int pad;
  639. if (size & 1)
  640. *(p++) = buf[size - 1];
  641. pad = 64 - size;
  642. memset(p, 0, pad);
  643. p += pad;
  644. size = 64;
  645. }
  646. /* It's not clear if the CRC should go before or after the last byte in
  647. odd sized packets. Linux disables the CRC, so that's no help.
  648. The pictures in the documentation show the CRC aligned on a 16-bit
  649. boundary before the last odd byte, so that's what we do. */
  650. if (crc) {
  651. crc = crc32(~0, buf, size);
  652. *(p++) = crc & 0xff; crc >>= 8;
  653. *(p++) = crc & 0xff; crc >>= 8;
  654. *(p++) = crc & 0xff; crc >>= 8;
  655. *(p++) = crc & 0xff;
  656. }
  657. if (size & 1) {
  658. *(p++) = buf[size - 1];
  659. *p = 0x60;
  660. } else {
  661. *(p++) = 0;
  662. *p = 0x40;
  663. }
  664. /* TODO: Raise early RX interrupt? */
  665. s->int_level |= INT_RCV;
  666. smc91c111_update(s);
  667. return size;
  668. }
  669. static const MemoryRegionOps smc91c111_mem_ops = {
  670. /* The special case for 32 bit writes to 0xc means we can't just
  671. * set .impl.min/max_access_size to 1, unfortunately
  672. */
  673. .old_mmio = {
  674. .read = { smc91c111_readb, smc91c111_readw, smc91c111_readl, },
  675. .write = { smc91c111_writeb, smc91c111_writew, smc91c111_writel, },
  676. },
  677. .endianness = DEVICE_NATIVE_ENDIAN,
  678. };
  679. static void smc91c111_cleanup(NetClientState *nc)
  680. {
  681. smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
  682. s->nic = NULL;
  683. }
  684. static NetClientInfo net_smc91c111_info = {
  685. .type = NET_CLIENT_OPTIONS_KIND_NIC,
  686. .size = sizeof(NICState),
  687. .can_receive = smc91c111_can_receive,
  688. .receive = smc91c111_receive,
  689. .cleanup = smc91c111_cleanup,
  690. };
  691. static int smc91c111_init1(SysBusDevice *dev)
  692. {
  693. smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev);
  694. memory_region_init_io(&s->mmio, &smc91c111_mem_ops, s,
  695. "smc91c111-mmio", 16);
  696. sysbus_init_mmio(dev, &s->mmio);
  697. sysbus_init_irq(dev, &s->irq);
  698. qemu_macaddr_default_if_unset(&s->conf.macaddr);
  699. s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
  700. object_get_typename(OBJECT(dev)), dev->qdev.id, s);
  701. qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
  702. /* ??? Save/restore. */
  703. return 0;
  704. }
  705. static Property smc91c111_properties[] = {
  706. DEFINE_NIC_PROPERTIES(smc91c111_state, conf),
  707. DEFINE_PROP_END_OF_LIST(),
  708. };
  709. static void smc91c111_class_init(ObjectClass *klass, void *data)
  710. {
  711. DeviceClass *dc = DEVICE_CLASS(klass);
  712. SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  713. k->init = smc91c111_init1;
  714. dc->reset = smc91c111_reset;
  715. dc->vmsd = &vmstate_smc91c111;
  716. dc->props = smc91c111_properties;
  717. }
  718. static TypeInfo smc91c111_info = {
  719. .name = "smc91c111",
  720. .parent = TYPE_SYS_BUS_DEVICE,
  721. .instance_size = sizeof(smc91c111_state),
  722. .class_init = smc91c111_class_init,
  723. };
  724. static void smc91c111_register_types(void)
  725. {
  726. type_register_static(&smc91c111_info);
  727. }
  728. /* Legacy helper function. Should go away when machine config files are
  729. implemented. */
  730. void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  731. {
  732. DeviceState *dev;
  733. SysBusDevice *s;
  734. qemu_check_nic_model(nd, "smc91c111");
  735. dev = qdev_create(NULL, "smc91c111");
  736. qdev_set_nic_properties(dev, nd);
  737. qdev_init_nofail(dev);
  738. s = sysbus_from_qdev(dev);
  739. sysbus_mmio_map(s, 0, base);
  740. sysbus_connect_irq(s, 0, irq);
  741. }
  742. type_init(smc91c111_register_types)