pl031.c 6.9 KB

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  1. /*
  2. * ARM AMBA PrimeCell PL031 RTC
  3. *
  4. * Copyright (c) 2007 CodeSourcery
  5. *
  6. * This file is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Contributions after 2012-01-13 are licensed under the terms of the
  11. * GNU GPL, version 2 or (at your option) any later version.
  12. */
  13. #include "sysbus.h"
  14. #include "qemu-timer.h"
  15. #include "sysemu.h"
  16. //#define DEBUG_PL031
  17. #ifdef DEBUG_PL031
  18. #define DPRINTF(fmt, ...) \
  19. do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
  20. #else
  21. #define DPRINTF(fmt, ...) do {} while(0)
  22. #endif
  23. #define RTC_DR 0x00 /* Data read register */
  24. #define RTC_MR 0x04 /* Match register */
  25. #define RTC_LR 0x08 /* Data load register */
  26. #define RTC_CR 0x0c /* Control register */
  27. #define RTC_IMSC 0x10 /* Interrupt mask and set register */
  28. #define RTC_RIS 0x14 /* Raw interrupt status register */
  29. #define RTC_MIS 0x18 /* Masked interrupt status register */
  30. #define RTC_ICR 0x1c /* Interrupt clear register */
  31. typedef struct {
  32. SysBusDevice busdev;
  33. MemoryRegion iomem;
  34. QEMUTimer *timer;
  35. qemu_irq irq;
  36. /* Needed to preserve the tick_count across migration, even if the
  37. * absolute value of the rtc_clock is different on the source and
  38. * destination.
  39. */
  40. uint32_t tick_offset_vmstate;
  41. uint32_t tick_offset;
  42. uint32_t mr;
  43. uint32_t lr;
  44. uint32_t cr;
  45. uint32_t im;
  46. uint32_t is;
  47. } pl031_state;
  48. static const unsigned char pl031_id[] = {
  49. 0x31, 0x10, 0x14, 0x00, /* Device ID */
  50. 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
  51. };
  52. static void pl031_update(pl031_state *s)
  53. {
  54. qemu_set_irq(s->irq, s->is & s->im);
  55. }
  56. static void pl031_interrupt(void * opaque)
  57. {
  58. pl031_state *s = (pl031_state *)opaque;
  59. s->is = 1;
  60. DPRINTF("Alarm raised\n");
  61. pl031_update(s);
  62. }
  63. static uint32_t pl031_get_count(pl031_state *s)
  64. {
  65. int64_t now = qemu_get_clock_ns(rtc_clock);
  66. return s->tick_offset + now / get_ticks_per_sec();
  67. }
  68. static void pl031_set_alarm(pl031_state *s)
  69. {
  70. uint32_t ticks;
  71. /* The timer wraps around. This subtraction also wraps in the same way,
  72. and gives correct results when alarm < now_ticks. */
  73. ticks = s->mr - pl031_get_count(s);
  74. DPRINTF("Alarm set in %ud ticks\n", ticks);
  75. if (ticks == 0) {
  76. qemu_del_timer(s->timer);
  77. pl031_interrupt(s);
  78. } else {
  79. int64_t now = qemu_get_clock_ns(rtc_clock);
  80. qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
  81. }
  82. }
  83. static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
  84. unsigned size)
  85. {
  86. pl031_state *s = (pl031_state *)opaque;
  87. if (offset >= 0xfe0 && offset < 0x1000)
  88. return pl031_id[(offset - 0xfe0) >> 2];
  89. switch (offset) {
  90. case RTC_DR:
  91. return pl031_get_count(s);
  92. case RTC_MR:
  93. return s->mr;
  94. case RTC_IMSC:
  95. return s->im;
  96. case RTC_RIS:
  97. return s->is;
  98. case RTC_LR:
  99. return s->lr;
  100. case RTC_CR:
  101. /* RTC is permanently enabled. */
  102. return 1;
  103. case RTC_MIS:
  104. return s->is & s->im;
  105. case RTC_ICR:
  106. fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
  107. (int)offset);
  108. break;
  109. default:
  110. hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
  111. break;
  112. }
  113. return 0;
  114. }
  115. static void pl031_write(void * opaque, target_phys_addr_t offset,
  116. uint64_t value, unsigned size)
  117. {
  118. pl031_state *s = (pl031_state *)opaque;
  119. switch (offset) {
  120. case RTC_LR:
  121. s->tick_offset += value - pl031_get_count(s);
  122. pl031_set_alarm(s);
  123. break;
  124. case RTC_MR:
  125. s->mr = value;
  126. pl031_set_alarm(s);
  127. break;
  128. case RTC_IMSC:
  129. s->im = value & 1;
  130. DPRINTF("Interrupt mask %d\n", s->im);
  131. pl031_update(s);
  132. break;
  133. case RTC_ICR:
  134. /* The PL031 documentation (DDI0224B) states that the interrupt is
  135. cleared when bit 0 of the written value is set. However the
  136. arm926e documentation (DDI0287B) states that the interrupt is
  137. cleared when any value is written. */
  138. DPRINTF("Interrupt cleared");
  139. s->is = 0;
  140. pl031_update(s);
  141. break;
  142. case RTC_CR:
  143. /* Written value is ignored. */
  144. break;
  145. case RTC_DR:
  146. case RTC_MIS:
  147. case RTC_RIS:
  148. fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
  149. (int)offset);
  150. break;
  151. default:
  152. hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
  153. break;
  154. }
  155. }
  156. static const MemoryRegionOps pl031_ops = {
  157. .read = pl031_read,
  158. .write = pl031_write,
  159. .endianness = DEVICE_NATIVE_ENDIAN,
  160. };
  161. static int pl031_init(SysBusDevice *dev)
  162. {
  163. pl031_state *s = FROM_SYSBUS(pl031_state, dev);
  164. struct tm tm;
  165. memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
  166. sysbus_init_mmio(dev, &s->iomem);
  167. sysbus_init_irq(dev, &s->irq);
  168. qemu_get_timedate(&tm, 0);
  169. s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
  170. s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
  171. return 0;
  172. }
  173. static void pl031_pre_save(void *opaque)
  174. {
  175. pl031_state *s = opaque;
  176. /* tick_offset is base_time - rtc_clock base time. Instead, we want to
  177. * store the base time relative to the vm_clock for backwards-compatibility. */
  178. int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
  179. s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
  180. }
  181. static int pl031_post_load(void *opaque, int version_id)
  182. {
  183. pl031_state *s = opaque;
  184. int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
  185. s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
  186. pl031_set_alarm(s);
  187. return 0;
  188. }
  189. static const VMStateDescription vmstate_pl031 = {
  190. .name = "pl031",
  191. .version_id = 1,
  192. .minimum_version_id = 1,
  193. .pre_save = pl031_pre_save,
  194. .post_load = pl031_post_load,
  195. .fields = (VMStateField[]) {
  196. VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
  197. VMSTATE_UINT32(mr, pl031_state),
  198. VMSTATE_UINT32(lr, pl031_state),
  199. VMSTATE_UINT32(cr, pl031_state),
  200. VMSTATE_UINT32(im, pl031_state),
  201. VMSTATE_UINT32(is, pl031_state),
  202. VMSTATE_END_OF_LIST()
  203. }
  204. };
  205. static void pl031_class_init(ObjectClass *klass, void *data)
  206. {
  207. DeviceClass *dc = DEVICE_CLASS(klass);
  208. SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  209. k->init = pl031_init;
  210. dc->no_user = 1;
  211. dc->vmsd = &vmstate_pl031;
  212. }
  213. static TypeInfo pl031_info = {
  214. .name = "pl031",
  215. .parent = TYPE_SYS_BUS_DEVICE,
  216. .instance_size = sizeof(pl031_state),
  217. .class_init = pl031_class_init,
  218. };
  219. static void pl031_register_types(void)
  220. {
  221. type_register_static(&pl031_info);
  222. }
  223. type_init(pl031_register_types)