pflash_cfi01.c 21 KB

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  1. /*
  2. * CFI parallel flash with Intel command set emulation
  3. *
  4. * Copyright (c) 2006 Thorsten Zitterell
  5. * Copyright (c) 2005 Jocelyn Mayer
  6. *
  7. * This library is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU Lesser General Public
  9. * License as published by the Free Software Foundation; either
  10. * version 2 of the License, or (at your option) any later version.
  11. *
  12. * This library is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * Lesser General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU Lesser General Public
  18. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. /*
  21. * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22. * Supported commands/modes are:
  23. * - flash read
  24. * - flash write
  25. * - flash ID read
  26. * - sector erase
  27. * - CFI queries
  28. *
  29. * It does not support timings
  30. * It does not support flash interleaving
  31. * It does not implement software data protection as found in many real chips
  32. * It does not implement erase suspend/resume commands
  33. * It does not implement multiple sectors erase
  34. *
  35. * It does not implement much more ...
  36. */
  37. #include "hw.h"
  38. #include "flash.h"
  39. #include "block.h"
  40. #include "qemu-timer.h"
  41. #include "exec-memory.h"
  42. #define PFLASH_BUG(fmt, ...) \
  43. do { \
  44. printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  45. exit(1); \
  46. } while(0)
  47. /* #define PFLASH_DEBUG */
  48. #ifdef PFLASH_DEBUG
  49. #define DPRINTF(fmt, ...) \
  50. do { \
  51. printf("PFLASH: " fmt , ## __VA_ARGS__); \
  52. } while (0)
  53. #else
  54. #define DPRINTF(fmt, ...) do { } while (0)
  55. #endif
  56. struct pflash_t {
  57. BlockDriverState *bs;
  58. target_phys_addr_t base;
  59. target_phys_addr_t sector_len;
  60. target_phys_addr_t total_len;
  61. int width;
  62. int wcycle; /* if 0, the flash is read normally */
  63. int bypass;
  64. int ro;
  65. uint8_t cmd;
  66. uint8_t status;
  67. uint16_t ident[4];
  68. uint8_t cfi_len;
  69. uint8_t cfi_table[0x52];
  70. target_phys_addr_t counter;
  71. unsigned int writeblock_size;
  72. QEMUTimer *timer;
  73. MemoryRegion mem;
  74. void *storage;
  75. };
  76. static void pflash_timer (void *opaque)
  77. {
  78. pflash_t *pfl = opaque;
  79. DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  80. /* Reset flash */
  81. pfl->status ^= 0x80;
  82. if (pfl->bypass) {
  83. pfl->wcycle = 2;
  84. } else {
  85. memory_region_rom_device_set_readable(&pfl->mem, true);
  86. pfl->wcycle = 0;
  87. }
  88. pfl->cmd = 0;
  89. }
  90. static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
  91. int width, int be)
  92. {
  93. target_phys_addr_t boff;
  94. uint32_t ret;
  95. uint8_t *p;
  96. ret = -1;
  97. boff = offset & 0xFF; /* why this here ?? */
  98. if (pfl->width == 2)
  99. boff = boff >> 1;
  100. else if (pfl->width == 4)
  101. boff = boff >> 2;
  102. #if 0
  103. DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
  104. __func__, offset, pfl->cmd, width);
  105. #endif
  106. switch (pfl->cmd) {
  107. case 0x00:
  108. /* Flash area read */
  109. p = pfl->storage;
  110. switch (width) {
  111. case 1:
  112. ret = p[offset];
  113. DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
  114. __func__, offset, ret);
  115. break;
  116. case 2:
  117. if (be) {
  118. ret = p[offset] << 8;
  119. ret |= p[offset + 1];
  120. } else {
  121. ret = p[offset];
  122. ret |= p[offset + 1] << 8;
  123. }
  124. DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
  125. __func__, offset, ret);
  126. break;
  127. case 4:
  128. if (be) {
  129. ret = p[offset] << 24;
  130. ret |= p[offset + 1] << 16;
  131. ret |= p[offset + 2] << 8;
  132. ret |= p[offset + 3];
  133. } else {
  134. ret = p[offset];
  135. ret |= p[offset + 1] << 8;
  136. ret |= p[offset + 2] << 16;
  137. ret |= p[offset + 3] << 24;
  138. }
  139. DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
  140. __func__, offset, ret);
  141. break;
  142. default:
  143. DPRINTF("BUG in %s\n", __func__);
  144. }
  145. break;
  146. case 0x20: /* Block erase */
  147. case 0x50: /* Clear status register */
  148. case 0x60: /* Block /un)lock */
  149. case 0x70: /* Status Register */
  150. case 0xe8: /* Write block */
  151. /* Status register read */
  152. ret = pfl->status;
  153. DPRINTF("%s: status %x\n", __func__, ret);
  154. break;
  155. case 0x90:
  156. switch (boff) {
  157. case 0:
  158. ret = pfl->ident[0] << 8 | pfl->ident[1];
  159. DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
  160. break;
  161. case 1:
  162. ret = pfl->ident[2] << 8 | pfl->ident[3];
  163. DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
  164. break;
  165. default:
  166. DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff);
  167. ret = 0;
  168. break;
  169. }
  170. break;
  171. case 0x98: /* Query mode */
  172. if (boff > pfl->cfi_len)
  173. ret = 0;
  174. else
  175. ret = pfl->cfi_table[boff];
  176. break;
  177. default:
  178. /* This should never happen : reset state & treat it as a read */
  179. DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
  180. pfl->wcycle = 0;
  181. pfl->cmd = 0;
  182. }
  183. return ret;
  184. }
  185. /* update flash content on disk */
  186. static void pflash_update(pflash_t *pfl, int offset,
  187. int size)
  188. {
  189. int offset_end;
  190. if (pfl->bs) {
  191. offset_end = offset + size;
  192. /* round to sectors */
  193. offset = offset >> 9;
  194. offset_end = (offset_end + 511) >> 9;
  195. bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
  196. offset_end - offset);
  197. }
  198. }
  199. static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
  200. uint32_t value, int width, int be)
  201. {
  202. uint8_t *p = pfl->storage;
  203. DPRINTF("%s: block write offset " TARGET_FMT_plx
  204. " value %x counter " TARGET_FMT_plx "\n",
  205. __func__, offset, value, pfl->counter);
  206. switch (width) {
  207. case 1:
  208. p[offset] = value;
  209. break;
  210. case 2:
  211. if (be) {
  212. p[offset] = value >> 8;
  213. p[offset + 1] = value;
  214. } else {
  215. p[offset] = value;
  216. p[offset + 1] = value >> 8;
  217. }
  218. break;
  219. case 4:
  220. if (be) {
  221. p[offset] = value >> 24;
  222. p[offset + 1] = value >> 16;
  223. p[offset + 2] = value >> 8;
  224. p[offset + 3] = value;
  225. } else {
  226. p[offset] = value;
  227. p[offset + 1] = value >> 8;
  228. p[offset + 2] = value >> 16;
  229. p[offset + 3] = value >> 24;
  230. }
  231. break;
  232. }
  233. }
  234. static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
  235. uint32_t value, int width, int be)
  236. {
  237. uint8_t *p;
  238. uint8_t cmd;
  239. cmd = value;
  240. DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
  241. __func__, offset, value, width, pfl->wcycle);
  242. if (!pfl->wcycle) {
  243. /* Set the device in I/O access mode */
  244. memory_region_rom_device_set_readable(&pfl->mem, false);
  245. }
  246. switch (pfl->wcycle) {
  247. case 0:
  248. /* read mode */
  249. switch (cmd) {
  250. case 0x00: /* ??? */
  251. goto reset_flash;
  252. case 0x10: /* Single Byte Program */
  253. case 0x40: /* Single Byte Program */
  254. DPRINTF("%s: Single Byte Program\n", __func__);
  255. break;
  256. case 0x20: /* Block erase */
  257. p = pfl->storage;
  258. offset &= ~(pfl->sector_len - 1);
  259. DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes "
  260. TARGET_FMT_plx "\n",
  261. __func__, offset, pfl->sector_len);
  262. if (!pfl->ro) {
  263. memset(p + offset, 0xff, pfl->sector_len);
  264. pflash_update(pfl, offset, pfl->sector_len);
  265. } else {
  266. pfl->status |= 0x20; /* Block erase error */
  267. }
  268. pfl->status |= 0x80; /* Ready! */
  269. break;
  270. case 0x50: /* Clear status bits */
  271. DPRINTF("%s: Clear status bits\n", __func__);
  272. pfl->status = 0x0;
  273. goto reset_flash;
  274. case 0x60: /* Block (un)lock */
  275. DPRINTF("%s: Block unlock\n", __func__);
  276. break;
  277. case 0x70: /* Status Register */
  278. DPRINTF("%s: Read status register\n", __func__);
  279. pfl->cmd = cmd;
  280. return;
  281. case 0x90: /* Read Device ID */
  282. DPRINTF("%s: Read Device information\n", __func__);
  283. pfl->cmd = cmd;
  284. return;
  285. case 0x98: /* CFI query */
  286. DPRINTF("%s: CFI query\n", __func__);
  287. break;
  288. case 0xe8: /* Write to buffer */
  289. DPRINTF("%s: Write to buffer\n", __func__);
  290. pfl->status |= 0x80; /* Ready! */
  291. break;
  292. case 0xff: /* Read array mode */
  293. DPRINTF("%s: Read array mode\n", __func__);
  294. goto reset_flash;
  295. default:
  296. goto error_flash;
  297. }
  298. pfl->wcycle++;
  299. pfl->cmd = cmd;
  300. break;
  301. case 1:
  302. switch (pfl->cmd) {
  303. case 0x10: /* Single Byte Program */
  304. case 0x40: /* Single Byte Program */
  305. DPRINTF("%s: Single Byte Program\n", __func__);
  306. if (!pfl->ro) {
  307. pflash_data_write(pfl, offset, value, width, be);
  308. pflash_update(pfl, offset, width);
  309. } else {
  310. pfl->status |= 0x10; /* Programming error */
  311. }
  312. pfl->status |= 0x80; /* Ready! */
  313. pfl->wcycle = 0;
  314. break;
  315. case 0x20: /* Block erase */
  316. case 0x28:
  317. if (cmd == 0xd0) { /* confirm */
  318. pfl->wcycle = 0;
  319. pfl->status |= 0x80;
  320. } else if (cmd == 0xff) { /* read array mode */
  321. goto reset_flash;
  322. } else
  323. goto error_flash;
  324. break;
  325. case 0xe8:
  326. DPRINTF("%s: block write of %x bytes\n", __func__, value);
  327. pfl->counter = value;
  328. pfl->wcycle++;
  329. break;
  330. case 0x60:
  331. if (cmd == 0xd0) {
  332. pfl->wcycle = 0;
  333. pfl->status |= 0x80;
  334. } else if (cmd == 0x01) {
  335. pfl->wcycle = 0;
  336. pfl->status |= 0x80;
  337. } else if (cmd == 0xff) {
  338. goto reset_flash;
  339. } else {
  340. DPRINTF("%s: Unknown (un)locking command\n", __func__);
  341. goto reset_flash;
  342. }
  343. break;
  344. case 0x98:
  345. if (cmd == 0xff) {
  346. goto reset_flash;
  347. } else {
  348. DPRINTF("%s: leaving query mode\n", __func__);
  349. }
  350. break;
  351. default:
  352. goto error_flash;
  353. }
  354. break;
  355. case 2:
  356. switch (pfl->cmd) {
  357. case 0xe8: /* Block write */
  358. if (!pfl->ro) {
  359. pflash_data_write(pfl, offset, value, width, be);
  360. } else {
  361. pfl->status |= 0x10; /* Programming error */
  362. }
  363. pfl->status |= 0x80;
  364. if (!pfl->counter) {
  365. target_phys_addr_t mask = pfl->writeblock_size - 1;
  366. mask = ~mask;
  367. DPRINTF("%s: block write finished\n", __func__);
  368. pfl->wcycle++;
  369. if (!pfl->ro) {
  370. /* Flush the entire write buffer onto backing storage. */
  371. pflash_update(pfl, offset & mask, pfl->writeblock_size);
  372. } else {
  373. pfl->status |= 0x10; /* Programming error */
  374. }
  375. }
  376. pfl->counter--;
  377. break;
  378. default:
  379. goto error_flash;
  380. }
  381. break;
  382. case 3: /* Confirm mode */
  383. switch (pfl->cmd) {
  384. case 0xe8: /* Block write */
  385. if (cmd == 0xd0) {
  386. pfl->wcycle = 0;
  387. pfl->status |= 0x80;
  388. } else {
  389. DPRINTF("%s: unknown command for \"write block\"\n", __func__);
  390. PFLASH_BUG("Write block confirm");
  391. goto reset_flash;
  392. }
  393. break;
  394. default:
  395. goto error_flash;
  396. }
  397. break;
  398. default:
  399. /* Should never happen */
  400. DPRINTF("%s: invalid write state\n", __func__);
  401. goto reset_flash;
  402. }
  403. return;
  404. error_flash:
  405. printf("%s: Unimplemented flash cmd sequence "
  406. "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n",
  407. __func__, offset, pfl->wcycle, pfl->cmd, value);
  408. reset_flash:
  409. memory_region_rom_device_set_readable(&pfl->mem, true);
  410. pfl->bypass = 0;
  411. pfl->wcycle = 0;
  412. pfl->cmd = 0;
  413. return;
  414. }
  415. static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
  416. {
  417. return pflash_read(opaque, addr, 1, 1);
  418. }
  419. static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
  420. {
  421. return pflash_read(opaque, addr, 1, 0);
  422. }
  423. static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
  424. {
  425. pflash_t *pfl = opaque;
  426. return pflash_read(pfl, addr, 2, 1);
  427. }
  428. static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
  429. {
  430. pflash_t *pfl = opaque;
  431. return pflash_read(pfl, addr, 2, 0);
  432. }
  433. static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
  434. {
  435. pflash_t *pfl = opaque;
  436. return pflash_read(pfl, addr, 4, 1);
  437. }
  438. static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
  439. {
  440. pflash_t *pfl = opaque;
  441. return pflash_read(pfl, addr, 4, 0);
  442. }
  443. static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
  444. uint32_t value)
  445. {
  446. pflash_write(opaque, addr, value, 1, 1);
  447. }
  448. static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
  449. uint32_t value)
  450. {
  451. pflash_write(opaque, addr, value, 1, 0);
  452. }
  453. static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
  454. uint32_t value)
  455. {
  456. pflash_t *pfl = opaque;
  457. pflash_write(pfl, addr, value, 2, 1);
  458. }
  459. static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
  460. uint32_t value)
  461. {
  462. pflash_t *pfl = opaque;
  463. pflash_write(pfl, addr, value, 2, 0);
  464. }
  465. static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
  466. uint32_t value)
  467. {
  468. pflash_t *pfl = opaque;
  469. pflash_write(pfl, addr, value, 4, 1);
  470. }
  471. static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
  472. uint32_t value)
  473. {
  474. pflash_t *pfl = opaque;
  475. pflash_write(pfl, addr, value, 4, 0);
  476. }
  477. static const MemoryRegionOps pflash_cfi01_ops_be = {
  478. .old_mmio = {
  479. .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
  480. .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
  481. },
  482. .endianness = DEVICE_NATIVE_ENDIAN,
  483. };
  484. static const MemoryRegionOps pflash_cfi01_ops_le = {
  485. .old_mmio = {
  486. .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
  487. .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
  488. },
  489. .endianness = DEVICE_NATIVE_ENDIAN,
  490. };
  491. /* Count trailing zeroes of a 32 bits quantity */
  492. static int ctz32 (uint32_t n)
  493. {
  494. int ret;
  495. ret = 0;
  496. if (!(n & 0xFFFF)) {
  497. ret += 16;
  498. n = n >> 16;
  499. }
  500. if (!(n & 0xFF)) {
  501. ret += 8;
  502. n = n >> 8;
  503. }
  504. if (!(n & 0xF)) {
  505. ret += 4;
  506. n = n >> 4;
  507. }
  508. if (!(n & 0x3)) {
  509. ret += 2;
  510. n = n >> 2;
  511. }
  512. if (!(n & 0x1)) {
  513. ret++;
  514. #if 0 /* This is not necessary as n is never 0 */
  515. n = n >> 1;
  516. #endif
  517. }
  518. #if 0 /* This is not necessary as n is never 0 */
  519. if (!n)
  520. ret++;
  521. #endif
  522. return ret;
  523. }
  524. pflash_t *pflash_cfi01_register(target_phys_addr_t base,
  525. DeviceState *qdev, const char *name,
  526. target_phys_addr_t size,
  527. BlockDriverState *bs, uint32_t sector_len,
  528. int nb_blocs, int width,
  529. uint16_t id0, uint16_t id1,
  530. uint16_t id2, uint16_t id3, int be)
  531. {
  532. pflash_t *pfl;
  533. target_phys_addr_t total_len;
  534. int ret;
  535. total_len = sector_len * nb_blocs;
  536. /* XXX: to be fixed */
  537. #if 0
  538. if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
  539. total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
  540. return NULL;
  541. #endif
  542. pfl = g_malloc0(sizeof(pflash_t));
  543. memory_region_init_rom_device(
  544. &pfl->mem, be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
  545. name, size);
  546. vmstate_register_ram(&pfl->mem, qdev);
  547. pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
  548. memory_region_add_subregion(get_system_memory(), base, &pfl->mem);
  549. pfl->bs = bs;
  550. if (pfl->bs) {
  551. /* read the initial flash content */
  552. ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
  553. if (ret < 0) {
  554. memory_region_del_subregion(get_system_memory(), &pfl->mem);
  555. vmstate_unregister_ram(&pfl->mem, qdev);
  556. memory_region_destroy(&pfl->mem);
  557. g_free(pfl);
  558. return NULL;
  559. }
  560. bdrv_attach_dev_nofail(pfl->bs, pfl);
  561. }
  562. if (pfl->bs) {
  563. pfl->ro = bdrv_is_read_only(pfl->bs);
  564. } else {
  565. pfl->ro = 0;
  566. }
  567. pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
  568. pfl->base = base;
  569. pfl->sector_len = sector_len;
  570. pfl->total_len = total_len;
  571. pfl->width = width;
  572. pfl->wcycle = 0;
  573. pfl->cmd = 0;
  574. pfl->status = 0;
  575. pfl->ident[0] = id0;
  576. pfl->ident[1] = id1;
  577. pfl->ident[2] = id2;
  578. pfl->ident[3] = id3;
  579. /* Hardcoded CFI table */
  580. pfl->cfi_len = 0x52;
  581. /* Standard "QRY" string */
  582. pfl->cfi_table[0x10] = 'Q';
  583. pfl->cfi_table[0x11] = 'R';
  584. pfl->cfi_table[0x12] = 'Y';
  585. /* Command set (Intel) */
  586. pfl->cfi_table[0x13] = 0x01;
  587. pfl->cfi_table[0x14] = 0x00;
  588. /* Primary extended table address (none) */
  589. pfl->cfi_table[0x15] = 0x31;
  590. pfl->cfi_table[0x16] = 0x00;
  591. /* Alternate command set (none) */
  592. pfl->cfi_table[0x17] = 0x00;
  593. pfl->cfi_table[0x18] = 0x00;
  594. /* Alternate extended table (none) */
  595. pfl->cfi_table[0x19] = 0x00;
  596. pfl->cfi_table[0x1A] = 0x00;
  597. /* Vcc min */
  598. pfl->cfi_table[0x1B] = 0x45;
  599. /* Vcc max */
  600. pfl->cfi_table[0x1C] = 0x55;
  601. /* Vpp min (no Vpp pin) */
  602. pfl->cfi_table[0x1D] = 0x00;
  603. /* Vpp max (no Vpp pin) */
  604. pfl->cfi_table[0x1E] = 0x00;
  605. /* Reserved */
  606. pfl->cfi_table[0x1F] = 0x07;
  607. /* Timeout for min size buffer write */
  608. pfl->cfi_table[0x20] = 0x07;
  609. /* Typical timeout for block erase */
  610. pfl->cfi_table[0x21] = 0x0a;
  611. /* Typical timeout for full chip erase (4096 ms) */
  612. pfl->cfi_table[0x22] = 0x00;
  613. /* Reserved */
  614. pfl->cfi_table[0x23] = 0x04;
  615. /* Max timeout for buffer write */
  616. pfl->cfi_table[0x24] = 0x04;
  617. /* Max timeout for block erase */
  618. pfl->cfi_table[0x25] = 0x04;
  619. /* Max timeout for chip erase */
  620. pfl->cfi_table[0x26] = 0x00;
  621. /* Device size */
  622. pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
  623. /* Flash device interface (8 & 16 bits) */
  624. pfl->cfi_table[0x28] = 0x02;
  625. pfl->cfi_table[0x29] = 0x00;
  626. /* Max number of bytes in multi-bytes write */
  627. if (width == 1) {
  628. pfl->cfi_table[0x2A] = 0x08;
  629. } else {
  630. pfl->cfi_table[0x2A] = 0x0B;
  631. }
  632. pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
  633. pfl->cfi_table[0x2B] = 0x00;
  634. /* Number of erase block regions (uniform) */
  635. pfl->cfi_table[0x2C] = 0x01;
  636. /* Erase block region 1 */
  637. pfl->cfi_table[0x2D] = nb_blocs - 1;
  638. pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
  639. pfl->cfi_table[0x2F] = sector_len >> 8;
  640. pfl->cfi_table[0x30] = sector_len >> 16;
  641. /* Extended */
  642. pfl->cfi_table[0x31] = 'P';
  643. pfl->cfi_table[0x32] = 'R';
  644. pfl->cfi_table[0x33] = 'I';
  645. pfl->cfi_table[0x34] = '1';
  646. pfl->cfi_table[0x35] = '0';
  647. pfl->cfi_table[0x36] = 0x00;
  648. pfl->cfi_table[0x37] = 0x00;
  649. pfl->cfi_table[0x38] = 0x00;
  650. pfl->cfi_table[0x39] = 0x00;
  651. pfl->cfi_table[0x3a] = 0x00;
  652. pfl->cfi_table[0x3b] = 0x00;
  653. pfl->cfi_table[0x3c] = 0x00;
  654. pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
  655. return pfl;
  656. }
  657. MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
  658. {
  659. return &fl->mem;
  660. }