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exec-all.h 13 KB

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  1. /*
  2. * internal execution defines for qemu
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * This library is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU Lesser General Public
  8. * License as published by the Free Software Foundation; either
  9. * version 2 of the License, or (at your option) any later version.
  10. *
  11. * This library is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * Lesser General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU Lesser General Public
  17. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef _EXEC_ALL_H_
  20. #define _EXEC_ALL_H_
  21. #include "qemu-common.h"
  22. /* allow to see translation results - the slowdown should be negligible, so we leave it */
  23. #define DEBUG_DISAS
  24. /* Page tracking code uses ram addresses in system mode, and virtual
  25. addresses in userspace mode. Define tb_page_addr_t to be an appropriate
  26. type. */
  27. #if defined(CONFIG_USER_ONLY)
  28. typedef abi_ulong tb_page_addr_t;
  29. #else
  30. typedef ram_addr_t tb_page_addr_t;
  31. #endif
  32. /* is_jmp field values */
  33. #define DISAS_NEXT 0 /* next instruction can be analyzed */
  34. #define DISAS_JUMP 1 /* only pc was modified dynamically */
  35. #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
  36. #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  37. struct TranslationBlock;
  38. typedef struct TranslationBlock TranslationBlock;
  39. /* XXX: make safe guess about sizes */
  40. #define MAX_OP_PER_INSTR 208
  41. #if HOST_LONG_BITS == 32
  42. #define MAX_OPC_PARAM_PER_ARG 2
  43. #else
  44. #define MAX_OPC_PARAM_PER_ARG 1
  45. #endif
  46. #define MAX_OPC_PARAM_IARGS 5
  47. #define MAX_OPC_PARAM_OARGS 1
  48. #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  49. /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50. * and up to 4 + N parameters on 64-bit archs
  51. * (N = number of input arguments + output arguments). */
  52. #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53. #define OPC_BUF_SIZE 640
  54. #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  55. /* Maximum size a TCG op can expand to. This is complicated because a
  56. single op may require several host instructions and register reloads.
  57. For now take a wild guess at 192 bytes, which should allow at least
  58. a couple of fixup instructions per argument. */
  59. #define TCG_MAX_OP_SIZE 192
  60. #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  61. extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  62. extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  63. extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  64. #include "qemu-log.h"
  65. void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  66. void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
  67. void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  68. int pc_pos);
  69. void cpu_gen_init(void);
  70. int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
  71. int *gen_code_size_ptr);
  72. int cpu_restore_state(struct TranslationBlock *tb,
  73. CPUArchState *env, uintptr_t searched_pc);
  74. void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
  75. void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
  76. TranslationBlock *tb_gen_code(CPUArchState *env,
  77. target_ulong pc, target_ulong cs_base, int flags,
  78. int cflags);
  79. void cpu_exec_init(CPUArchState *env);
  80. void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
  81. int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
  82. void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
  83. int is_cpu_write_access);
  84. void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
  85. int is_cpu_write_access);
  86. #if !defined(CONFIG_USER_ONLY)
  87. /* cputlb.c */
  88. void tlb_flush_page(CPUArchState *env, target_ulong addr);
  89. void tlb_flush(CPUArchState *env, int flush_global);
  90. void tlb_set_page(CPUArchState *env, target_ulong vaddr,
  91. target_phys_addr_t paddr, int prot,
  92. int mmu_idx, target_ulong size);
  93. void tb_invalidate_phys_addr(target_phys_addr_t addr);
  94. #else
  95. static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
  96. {
  97. }
  98. static inline void tlb_flush(CPUArchState *env, int flush_global)
  99. {
  100. }
  101. #endif
  102. #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
  103. #define CODE_GEN_PHYS_HASH_BITS 15
  104. #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
  105. #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
  106. /* estimated block size for TB allocation */
  107. /* XXX: use a per code average code fragment size and modulate it
  108. according to the host CPU */
  109. #if defined(CONFIG_SOFTMMU)
  110. #define CODE_GEN_AVG_BLOCK_SIZE 128
  111. #else
  112. #define CODE_GEN_AVG_BLOCK_SIZE 64
  113. #endif
  114. #if defined(__arm__) || defined(_ARCH_PPC) \
  115. || defined(__x86_64__) || defined(__i386__) \
  116. || defined(__sparc__) \
  117. || defined(CONFIG_TCG_INTERPRETER)
  118. #define USE_DIRECT_JUMP
  119. #endif
  120. struct TranslationBlock {
  121. target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
  122. target_ulong cs_base; /* CS base for this block */
  123. uint64_t flags; /* flags defining in which context the code was generated */
  124. uint16_t size; /* size of target code for this block (1 <=
  125. size <= TARGET_PAGE_SIZE) */
  126. uint16_t cflags; /* compile flags */
  127. #define CF_COUNT_MASK 0x7fff
  128. #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
  129. uint8_t *tc_ptr; /* pointer to the translated code */
  130. /* next matching tb for physical address. */
  131. struct TranslationBlock *phys_hash_next;
  132. /* first and second physical page containing code. The lower bit
  133. of the pointer tells the index in page_next[] */
  134. struct TranslationBlock *page_next[2];
  135. tb_page_addr_t page_addr[2];
  136. /* the following data are used to directly call another TB from
  137. the code of this one. */
  138. uint16_t tb_next_offset[2]; /* offset of original jump target */
  139. #ifdef USE_DIRECT_JUMP
  140. uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
  141. #else
  142. uintptr_t tb_next[2]; /* address of jump generated code */
  143. #endif
  144. /* list of TBs jumping to this one. This is a circular list using
  145. the two least significant bits of the pointers to tell what is
  146. the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
  147. jmp_first */
  148. struct TranslationBlock *jmp_next[2];
  149. struct TranslationBlock *jmp_first;
  150. uint32_t icount;
  151. };
  152. static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
  153. {
  154. target_ulong tmp;
  155. tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
  156. return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
  157. }
  158. static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
  159. {
  160. target_ulong tmp;
  161. tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
  162. return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
  163. | (tmp & TB_JMP_ADDR_MASK));
  164. }
  165. static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
  166. {
  167. return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
  168. }
  169. void tb_free(TranslationBlock *tb);
  170. void tb_flush(CPUArchState *env);
  171. void tb_link_page(TranslationBlock *tb,
  172. tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
  173. void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
  174. extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
  175. #if defined(USE_DIRECT_JUMP)
  176. #if defined(CONFIG_TCG_INTERPRETER)
  177. static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
  178. {
  179. /* patch the branch destination */
  180. *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
  181. /* no need to flush icache explicitly */
  182. }
  183. #elif defined(_ARCH_PPC)
  184. void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
  185. #define tb_set_jmp_target1 ppc_tb_set_jmp_target
  186. #elif defined(__i386__) || defined(__x86_64__)
  187. static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
  188. {
  189. /* patch the branch destination */
  190. *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
  191. /* no need to flush icache explicitly */
  192. }
  193. #elif defined(__arm__)
  194. static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
  195. {
  196. #if !QEMU_GNUC_PREREQ(4, 1)
  197. register unsigned long _beg __asm ("a1");
  198. register unsigned long _end __asm ("a2");
  199. register unsigned long _flg __asm ("a3");
  200. #endif
  201. /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
  202. *(uint32_t *)jmp_addr =
  203. (*(uint32_t *)jmp_addr & ~0xffffff)
  204. | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
  205. #if QEMU_GNUC_PREREQ(4, 1)
  206. __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
  207. #else
  208. /* flush icache */
  209. _beg = jmp_addr;
  210. _end = jmp_addr + 4;
  211. _flg = 0;
  212. __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
  213. #endif
  214. }
  215. #elif defined(__sparc__)
  216. void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
  217. #else
  218. #error tb_set_jmp_target1 is missing
  219. #endif
  220. static inline void tb_set_jmp_target(TranslationBlock *tb,
  221. int n, uintptr_t addr)
  222. {
  223. uint16_t offset = tb->tb_jmp_offset[n];
  224. tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
  225. }
  226. #else
  227. /* set the jump target */
  228. static inline void tb_set_jmp_target(TranslationBlock *tb,
  229. int n, uintptr_t addr)
  230. {
  231. tb->tb_next[n] = addr;
  232. }
  233. #endif
  234. static inline void tb_add_jump(TranslationBlock *tb, int n,
  235. TranslationBlock *tb_next)
  236. {
  237. /* NOTE: this test is only needed for thread safety */
  238. if (!tb->jmp_next[n]) {
  239. /* patch the native jump address */
  240. tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
  241. /* add in TB jmp circular list */
  242. tb->jmp_next[n] = tb_next->jmp_first;
  243. tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
  244. }
  245. }
  246. TranslationBlock *tb_find_pc(uintptr_t pc_ptr);
  247. #include "qemu-lock.h"
  248. extern spinlock_t tb_lock;
  249. extern int tb_invalidated_flag;
  250. /* The return address may point to the start of the next instruction.
  251. Subtracting one gets us the call instruction itself. */
  252. #if defined(CONFIG_TCG_INTERPRETER)
  253. /* Alpha and SH4 user mode emulations and Softmmu call GETPC().
  254. For all others, GETPC remains undefined (which makes TCI a little faster. */
  255. # if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
  256. extern uintptr_t tci_tb_ptr;
  257. # define GETPC() tci_tb_ptr
  258. # endif
  259. #elif defined(__s390__) && !defined(__s390x__)
  260. # define GETPC() \
  261. (((uintptr_t)__builtin_return_address(0) & 0x7fffffffUL) - 1)
  262. #elif defined(__arm__)
  263. /* Thumb return addresses have the low bit set, so we need to subtract two.
  264. This is still safe in ARM mode because instructions are 4 bytes. */
  265. # define GETPC() ((uintptr_t)__builtin_return_address(0) - 2)
  266. #else
  267. # define GETPC() ((uintptr_t)__builtin_return_address(0) - 1)
  268. #endif
  269. #if !defined(CONFIG_USER_ONLY)
  270. struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
  271. uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
  272. unsigned size);
  273. void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
  274. uint64_t value, unsigned size);
  275. void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
  276. uintptr_t retaddr);
  277. #include "softmmu_defs.h"
  278. #define ACCESS_TYPE (NB_MMU_MODES + 1)
  279. #define MEMSUFFIX _code
  280. #define DATA_SIZE 1
  281. #include "softmmu_header.h"
  282. #define DATA_SIZE 2
  283. #include "softmmu_header.h"
  284. #define DATA_SIZE 4
  285. #include "softmmu_header.h"
  286. #define DATA_SIZE 8
  287. #include "softmmu_header.h"
  288. #undef ACCESS_TYPE
  289. #undef MEMSUFFIX
  290. #endif
  291. #if defined(CONFIG_USER_ONLY)
  292. static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
  293. {
  294. return addr;
  295. }
  296. #else
  297. /* cputlb.c */
  298. tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
  299. #endif
  300. typedef void (CPUDebugExcpHandler)(CPUArchState *env);
  301. void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
  302. /* vl.c */
  303. extern int singlestep;
  304. /* cpu-exec.c */
  305. extern volatile sig_atomic_t exit_request;
  306. /* Deterministic execution requires that IO only be performed on the last
  307. instruction of a TB so that interrupts take effect immediately. */
  308. static inline int can_do_io(CPUArchState *env)
  309. {
  310. if (!use_icount) {
  311. return 1;
  312. }
  313. /* If not executing code then assume we are ok. */
  314. if (!env->current_tb) {
  315. return 1;
  316. }
  317. return env->can_do_io != 0;
  318. }
  319. #endif