spitz.c 32 KB

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  1. /*
  2. * PXA270-based Clamshell PDA platforms.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Written by Andrzej Zaborowski <balrog@zabor.org>
  6. *
  7. * This code is licensed under the GNU GPL v2.
  8. */
  9. #include "hw.h"
  10. #include "pxa.h"
  11. #include "arm-misc.h"
  12. #include "sysemu.h"
  13. #include "pcmcia.h"
  14. #include "i2c.h"
  15. #include "ssi.h"
  16. #include "flash.h"
  17. #include "qemu-timer.h"
  18. #include "devices.h"
  19. #include "sharpsl.h"
  20. #include "console.h"
  21. #include "block.h"
  22. #include "audio/audio.h"
  23. #include "boards.h"
  24. #include "blockdev.h"
  25. #include "sysbus.h"
  26. #include "exec-memory.h"
  27. #undef REG_FMT
  28. #define REG_FMT "0x%02lx"
  29. /* Spitz Flash */
  30. #define FLASH_BASE 0x0c000000
  31. #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
  32. #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
  33. #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
  34. #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
  35. #define FLASH_ECCCLRR 0x10 /* Clear ECC */
  36. #define FLASH_FLASHIO 0x14 /* Flash I/O */
  37. #define FLASH_FLASHCTL 0x18 /* Flash Control */
  38. #define FLASHCTL_CE0 (1 << 0)
  39. #define FLASHCTL_CLE (1 << 1)
  40. #define FLASHCTL_ALE (1 << 2)
  41. #define FLASHCTL_WP (1 << 3)
  42. #define FLASHCTL_CE1 (1 << 4)
  43. #define FLASHCTL_RYBY (1 << 5)
  44. #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
  45. typedef struct {
  46. SysBusDevice busdev;
  47. MemoryRegion iomem;
  48. DeviceState *nand;
  49. uint8_t ctl;
  50. uint8_t manf_id;
  51. uint8_t chip_id;
  52. ECCState ecc;
  53. } SLNANDState;
  54. static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
  55. {
  56. SLNANDState *s = (SLNANDState *) opaque;
  57. int ryby;
  58. switch (addr) {
  59. #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  60. case FLASH_ECCLPLB:
  61. return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  62. BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  63. #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  64. case FLASH_ECCLPUB:
  65. return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  66. BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  67. case FLASH_ECCCP:
  68. return s->ecc.cp;
  69. case FLASH_ECCCNTR:
  70. return s->ecc.count & 0xff;
  71. case FLASH_FLASHCTL:
  72. nand_getpins(s->nand, &ryby);
  73. if (ryby)
  74. return s->ctl | FLASHCTL_RYBY;
  75. else
  76. return s->ctl;
  77. case FLASH_FLASHIO:
  78. if (size == 4) {
  79. return ecc_digest(&s->ecc, nand_getio(s->nand)) |
  80. (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
  81. }
  82. return ecc_digest(&s->ecc, nand_getio(s->nand));
  83. default:
  84. zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  85. }
  86. return 0;
  87. }
  88. static void sl_write(void *opaque, target_phys_addr_t addr,
  89. uint64_t value, unsigned size)
  90. {
  91. SLNANDState *s = (SLNANDState *) opaque;
  92. switch (addr) {
  93. case FLASH_ECCCLRR:
  94. /* Value is ignored. */
  95. ecc_reset(&s->ecc);
  96. break;
  97. case FLASH_FLASHCTL:
  98. s->ctl = value & 0xff & ~FLASHCTL_RYBY;
  99. nand_setpins(s->nand,
  100. s->ctl & FLASHCTL_CLE,
  101. s->ctl & FLASHCTL_ALE,
  102. s->ctl & FLASHCTL_NCE,
  103. s->ctl & FLASHCTL_WP,
  104. 0);
  105. break;
  106. case FLASH_FLASHIO:
  107. nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
  108. break;
  109. default:
  110. zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  111. }
  112. }
  113. enum {
  114. FLASH_128M,
  115. FLASH_1024M,
  116. };
  117. static const MemoryRegionOps sl_ops = {
  118. .read = sl_read,
  119. .write = sl_write,
  120. .endianness = DEVICE_NATIVE_ENDIAN,
  121. };
  122. static void sl_flash_register(PXA2xxState *cpu, int size)
  123. {
  124. DeviceState *dev;
  125. dev = qdev_create(NULL, "sl-nand");
  126. qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
  127. if (size == FLASH_128M)
  128. qdev_prop_set_uint8(dev, "chip_id", 0x73);
  129. else if (size == FLASH_1024M)
  130. qdev_prop_set_uint8(dev, "chip_id", 0xf1);
  131. qdev_init_nofail(dev);
  132. sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE);
  133. }
  134. static int sl_nand_init(SysBusDevice *dev) {
  135. SLNANDState *s;
  136. DriveInfo *nand;
  137. s = FROM_SYSBUS(SLNANDState, dev);
  138. s->ctl = 0;
  139. nand = drive_get(IF_MTD, 0, 0);
  140. s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
  141. memory_region_init_io(&s->iomem, &sl_ops, s, "sl", 0x40);
  142. sysbus_init_mmio_region(dev, &s->iomem);
  143. return 0;
  144. }
  145. /* Spitz Keyboard */
  146. #define SPITZ_KEY_STROBE_NUM 11
  147. #define SPITZ_KEY_SENSE_NUM 7
  148. static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
  149. 12, 17, 91, 34, 36, 38, 39
  150. };
  151. static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
  152. 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
  153. };
  154. /* Eighth additional row maps the special keys */
  155. static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
  156. { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
  157. { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
  158. { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
  159. { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
  160. { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
  161. { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
  162. { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
  163. { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
  164. };
  165. #define SPITZ_GPIO_AK_INT 13 /* Remote control */
  166. #define SPITZ_GPIO_SYNC 16 /* Sync button */
  167. #define SPITZ_GPIO_ON_KEY 95 /* Power button */
  168. #define SPITZ_GPIO_SWA 97 /* Lid */
  169. #define SPITZ_GPIO_SWB 96 /* Tablet mode */
  170. /* The special buttons are mapped to unused keys */
  171. static const int spitz_gpiomap[5] = {
  172. SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
  173. SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
  174. };
  175. typedef struct {
  176. SysBusDevice busdev;
  177. qemu_irq sense[SPITZ_KEY_SENSE_NUM];
  178. qemu_irq gpiomap[5];
  179. int keymap[0x80];
  180. uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
  181. uint16_t strobe_state;
  182. uint16_t sense_state;
  183. uint16_t pre_map[0x100];
  184. uint16_t modifiers;
  185. uint16_t imodifiers;
  186. uint8_t fifo[16];
  187. int fifopos, fifolen;
  188. QEMUTimer *kbdtimer;
  189. } SpitzKeyboardState;
  190. static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
  191. {
  192. int i;
  193. uint16_t strobe, sense = 0;
  194. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
  195. strobe = s->keyrow[i] & s->strobe_state;
  196. if (strobe) {
  197. sense |= 1 << i;
  198. if (!(s->sense_state & (1 << i)))
  199. qemu_irq_raise(s->sense[i]);
  200. } else if (s->sense_state & (1 << i))
  201. qemu_irq_lower(s->sense[i]);
  202. }
  203. s->sense_state = sense;
  204. }
  205. static void spitz_keyboard_strobe(void *opaque, int line, int level)
  206. {
  207. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  208. if (level)
  209. s->strobe_state |= 1 << line;
  210. else
  211. s->strobe_state &= ~(1 << line);
  212. spitz_keyboard_sense_update(s);
  213. }
  214. static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
  215. {
  216. int spitz_keycode = s->keymap[keycode & 0x7f];
  217. if (spitz_keycode == -1)
  218. return;
  219. /* Handle the additional keys */
  220. if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
  221. qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
  222. return;
  223. }
  224. if (keycode & 0x80)
  225. s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
  226. else
  227. s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
  228. spitz_keyboard_sense_update(s);
  229. }
  230. #define SHIFT (1 << 7)
  231. #define CTRL (1 << 8)
  232. #define FN (1 << 9)
  233. #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  234. static void spitz_keyboard_handler(void *opaque, int keycode)
  235. {
  236. SpitzKeyboardState *s = opaque;
  237. uint16_t code;
  238. int mapcode;
  239. switch (keycode) {
  240. case 0x2a: /* Left Shift */
  241. s->modifiers |= 1;
  242. break;
  243. case 0xaa:
  244. s->modifiers &= ~1;
  245. break;
  246. case 0x36: /* Right Shift */
  247. s->modifiers |= 2;
  248. break;
  249. case 0xb6:
  250. s->modifiers &= ~2;
  251. break;
  252. case 0x1d: /* Control */
  253. s->modifiers |= 4;
  254. break;
  255. case 0x9d:
  256. s->modifiers &= ~4;
  257. break;
  258. case 0x38: /* Alt */
  259. s->modifiers |= 8;
  260. break;
  261. case 0xb8:
  262. s->modifiers &= ~8;
  263. break;
  264. }
  265. code = s->pre_map[mapcode = ((s->modifiers & 3) ?
  266. (keycode | SHIFT) :
  267. (keycode & ~SHIFT))];
  268. if (code != mapcode) {
  269. #if 0
  270. if ((code & SHIFT) && !(s->modifiers & 1))
  271. QUEUE_KEY(0x2a | (keycode & 0x80));
  272. if ((code & CTRL ) && !(s->modifiers & 4))
  273. QUEUE_KEY(0x1d | (keycode & 0x80));
  274. if ((code & FN ) && !(s->modifiers & 8))
  275. QUEUE_KEY(0x38 | (keycode & 0x80));
  276. if ((code & FN ) && (s->modifiers & 1))
  277. QUEUE_KEY(0x2a | (~keycode & 0x80));
  278. if ((code & FN ) && (s->modifiers & 2))
  279. QUEUE_KEY(0x36 | (~keycode & 0x80));
  280. #else
  281. if (keycode & 0x80) {
  282. if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
  283. QUEUE_KEY(0x2a | 0x80);
  284. if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
  285. QUEUE_KEY(0x1d | 0x80);
  286. if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
  287. QUEUE_KEY(0x38 | 0x80);
  288. if ((s->imodifiers & 0x10) && (s->modifiers & 1))
  289. QUEUE_KEY(0x2a);
  290. if ((s->imodifiers & 0x20) && (s->modifiers & 2))
  291. QUEUE_KEY(0x36);
  292. s->imodifiers = 0;
  293. } else {
  294. if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
  295. QUEUE_KEY(0x2a);
  296. s->imodifiers |= 1;
  297. }
  298. if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
  299. QUEUE_KEY(0x1d);
  300. s->imodifiers |= 4;
  301. }
  302. if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
  303. QUEUE_KEY(0x38);
  304. s->imodifiers |= 8;
  305. }
  306. if ((code & FN ) && (s->modifiers & 1) &&
  307. !(s->imodifiers & 0x10)) {
  308. QUEUE_KEY(0x2a | 0x80);
  309. s->imodifiers |= 0x10;
  310. }
  311. if ((code & FN ) && (s->modifiers & 2) &&
  312. !(s->imodifiers & 0x20)) {
  313. QUEUE_KEY(0x36 | 0x80);
  314. s->imodifiers |= 0x20;
  315. }
  316. }
  317. #endif
  318. }
  319. QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
  320. }
  321. static void spitz_keyboard_tick(void *opaque)
  322. {
  323. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  324. if (s->fifolen) {
  325. spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
  326. s->fifolen --;
  327. if (s->fifopos >= 16)
  328. s->fifopos = 0;
  329. }
  330. qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
  331. get_ticks_per_sec() / 32);
  332. }
  333. static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
  334. {
  335. int i;
  336. for (i = 0; i < 0x100; i ++)
  337. s->pre_map[i] = i;
  338. s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
  339. s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
  340. s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
  341. s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
  342. s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
  343. s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
  344. s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
  345. s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
  346. s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
  347. s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
  348. s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
  349. s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
  350. s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
  351. s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
  352. s->pre_map[0x0d ] = 0x12 | FN; /* equal */
  353. s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
  354. s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
  355. s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
  356. s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
  357. s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
  358. s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
  359. s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
  360. s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
  361. s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
  362. s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
  363. s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
  364. s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
  365. s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
  366. s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
  367. s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
  368. s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
  369. s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
  370. s->modifiers = 0;
  371. s->imodifiers = 0;
  372. s->fifopos = 0;
  373. s->fifolen = 0;
  374. }
  375. #undef SHIFT
  376. #undef CTRL
  377. #undef FN
  378. static int spitz_keyboard_post_load(void *opaque, int version_id)
  379. {
  380. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  381. /* Release all pressed keys */
  382. memset(s->keyrow, 0, sizeof(s->keyrow));
  383. spitz_keyboard_sense_update(s);
  384. s->modifiers = 0;
  385. s->imodifiers = 0;
  386. s->fifopos = 0;
  387. s->fifolen = 0;
  388. return 0;
  389. }
  390. static void spitz_keyboard_register(PXA2xxState *cpu)
  391. {
  392. int i;
  393. DeviceState *dev;
  394. SpitzKeyboardState *s;
  395. dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
  396. s = FROM_SYSBUS(SpitzKeyboardState, sysbus_from_qdev(dev));
  397. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
  398. qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
  399. for (i = 0; i < 5; i ++)
  400. s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
  401. if (!graphic_rotate)
  402. s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
  403. for (i = 0; i < 5; i++)
  404. qemu_set_irq(s->gpiomap[i], 0);
  405. for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
  406. qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
  407. qdev_get_gpio_in(dev, i));
  408. qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
  409. qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
  410. }
  411. static int spitz_keyboard_init(SysBusDevice *dev)
  412. {
  413. SpitzKeyboardState *s;
  414. int i, j;
  415. s = FROM_SYSBUS(SpitzKeyboardState, dev);
  416. for (i = 0; i < 0x80; i ++)
  417. s->keymap[i] = -1;
  418. for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
  419. for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
  420. if (spitz_keymap[i][j] != -1)
  421. s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
  422. spitz_keyboard_pre_map(s);
  423. s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
  424. qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
  425. qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
  426. return 0;
  427. }
  428. /* LCD backlight controller */
  429. #define LCDTG_RESCTL 0x00
  430. #define LCDTG_PHACTRL 0x01
  431. #define LCDTG_DUTYCTRL 0x02
  432. #define LCDTG_POWERREG0 0x03
  433. #define LCDTG_POWERREG1 0x04
  434. #define LCDTG_GPOR3 0x05
  435. #define LCDTG_PICTRL 0x06
  436. #define LCDTG_POLCTRL 0x07
  437. typedef struct {
  438. SSISlave ssidev;
  439. uint32_t bl_intensity;
  440. uint32_t bl_power;
  441. } SpitzLCDTG;
  442. static void spitz_bl_update(SpitzLCDTG *s)
  443. {
  444. if (s->bl_power && s->bl_intensity)
  445. zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
  446. else
  447. zaurus_printf("LCD Backlight now off\n");
  448. }
  449. /* FIXME: Implement GPIO properly and remove this hack. */
  450. static SpitzLCDTG *spitz_lcdtg;
  451. static inline void spitz_bl_bit5(void *opaque, int line, int level)
  452. {
  453. SpitzLCDTG *s = spitz_lcdtg;
  454. int prev = s->bl_intensity;
  455. if (level)
  456. s->bl_intensity &= ~0x20;
  457. else
  458. s->bl_intensity |= 0x20;
  459. if (s->bl_power && prev != s->bl_intensity)
  460. spitz_bl_update(s);
  461. }
  462. static inline void spitz_bl_power(void *opaque, int line, int level)
  463. {
  464. SpitzLCDTG *s = spitz_lcdtg;
  465. s->bl_power = !!level;
  466. spitz_bl_update(s);
  467. }
  468. static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
  469. {
  470. SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
  471. int addr;
  472. addr = value >> 5;
  473. value &= 0x1f;
  474. switch (addr) {
  475. case LCDTG_RESCTL:
  476. if (value)
  477. zaurus_printf("LCD in QVGA mode\n");
  478. else
  479. zaurus_printf("LCD in VGA mode\n");
  480. break;
  481. case LCDTG_DUTYCTRL:
  482. s->bl_intensity &= ~0x1f;
  483. s->bl_intensity |= value;
  484. if (s->bl_power)
  485. spitz_bl_update(s);
  486. break;
  487. case LCDTG_POWERREG0:
  488. /* Set common voltage to M62332FP */
  489. break;
  490. }
  491. return 0;
  492. }
  493. static int spitz_lcdtg_init(SSISlave *dev)
  494. {
  495. SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
  496. spitz_lcdtg = s;
  497. s->bl_power = 0;
  498. s->bl_intensity = 0x20;
  499. return 0;
  500. }
  501. /* SSP devices */
  502. #define CORGI_SSP_PORT 2
  503. #define SPITZ_GPIO_LCDCON_CS 53
  504. #define SPITZ_GPIO_ADS7846_CS 14
  505. #define SPITZ_GPIO_MAX1111_CS 20
  506. #define SPITZ_GPIO_TP_INT 11
  507. static DeviceState *max1111;
  508. /* "Demux" the signal based on current chipselect */
  509. typedef struct {
  510. SSISlave ssidev;
  511. SSIBus *bus[3];
  512. uint32_t enable[3];
  513. } CorgiSSPState;
  514. static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
  515. {
  516. CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
  517. int i;
  518. for (i = 0; i < 3; i++) {
  519. if (s->enable[i]) {
  520. return ssi_transfer(s->bus[i], value);
  521. }
  522. }
  523. return 0;
  524. }
  525. static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  526. {
  527. CorgiSSPState *s = (CorgiSSPState *)opaque;
  528. assert(line >= 0 && line < 3);
  529. s->enable[line] = !level;
  530. }
  531. #define MAX1111_BATT_VOLT 1
  532. #define MAX1111_BATT_TEMP 2
  533. #define MAX1111_ACIN_VOLT 3
  534. #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
  535. #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
  536. #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
  537. static void spitz_adc_temp_on(void *opaque, int line, int level)
  538. {
  539. if (!max1111)
  540. return;
  541. if (level)
  542. max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
  543. else
  544. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  545. }
  546. static int corgi_ssp_init(SSISlave *dev)
  547. {
  548. CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
  549. qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
  550. s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
  551. s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
  552. s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
  553. return 0;
  554. }
  555. static void spitz_ssp_attach(PXA2xxState *cpu)
  556. {
  557. DeviceState *mux;
  558. DeviceState *dev;
  559. void *bus;
  560. mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
  561. bus = qdev_get_child_bus(mux, "ssi0");
  562. ssi_create_slave(bus, "spitz-lcdtg");
  563. bus = qdev_get_child_bus(mux, "ssi1");
  564. dev = ssi_create_slave(bus, "ads7846");
  565. qdev_connect_gpio_out(dev, 0,
  566. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
  567. bus = qdev_get_child_bus(mux, "ssi2");
  568. max1111 = ssi_create_slave(bus, "max1111");
  569. max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
  570. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  571. max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
  572. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
  573. qdev_get_gpio_in(mux, 0));
  574. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
  575. qdev_get_gpio_in(mux, 1));
  576. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
  577. qdev_get_gpio_in(mux, 2));
  578. }
  579. /* CF Microdrive */
  580. static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
  581. {
  582. PCMCIACardState *md;
  583. DriveInfo *dinfo;
  584. dinfo = drive_get(IF_IDE, 0, 0);
  585. if (!dinfo || dinfo->media_cd)
  586. return;
  587. md = dscm1xxxx_init(dinfo);
  588. pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
  589. }
  590. /* Wm8750 and Max7310 on I2C */
  591. #define AKITA_MAX_ADDR 0x18
  592. #define SPITZ_WM_ADDRL 0x1b
  593. #define SPITZ_WM_ADDRH 0x1a
  594. #define SPITZ_GPIO_WM 5
  595. static void spitz_wm8750_addr(void *opaque, int line, int level)
  596. {
  597. i2c_slave *wm = (i2c_slave *) opaque;
  598. if (level)
  599. i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
  600. else
  601. i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
  602. }
  603. static void spitz_i2c_setup(PXA2xxState *cpu)
  604. {
  605. /* Attach the CPU on one end of our I2C bus. */
  606. i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
  607. DeviceState *wm;
  608. /* Attach a WM8750 to the bus */
  609. wm = i2c_create_slave(bus, "wm8750", 0);
  610. spitz_wm8750_addr(wm, 0, 0);
  611. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
  612. qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
  613. /* .. and to the sound interface. */
  614. cpu->i2s->opaque = wm;
  615. cpu->i2s->codec_out = wm8750_dac_dat;
  616. cpu->i2s->codec_in = wm8750_adc_dat;
  617. wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
  618. }
  619. static void spitz_akita_i2c_setup(PXA2xxState *cpu)
  620. {
  621. /* Attach a Max7310 to Akita I2C bus. */
  622. i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
  623. AKITA_MAX_ADDR);
  624. }
  625. /* Other peripherals */
  626. static void spitz_out_switch(void *opaque, int line, int level)
  627. {
  628. switch (line) {
  629. case 0:
  630. zaurus_printf("Charging %s.\n", level ? "off" : "on");
  631. break;
  632. case 1:
  633. zaurus_printf("Discharging %s.\n", level ? "on" : "off");
  634. break;
  635. case 2:
  636. zaurus_printf("Green LED %s.\n", level ? "on" : "off");
  637. break;
  638. case 3:
  639. zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
  640. break;
  641. case 4:
  642. spitz_bl_bit5(opaque, line, level);
  643. break;
  644. case 5:
  645. spitz_bl_power(opaque, line, level);
  646. break;
  647. case 6:
  648. spitz_adc_temp_on(opaque, line, level);
  649. break;
  650. }
  651. }
  652. #define SPITZ_SCP_LED_GREEN 1
  653. #define SPITZ_SCP_JK_B 2
  654. #define SPITZ_SCP_CHRG_ON 3
  655. #define SPITZ_SCP_MUTE_L 4
  656. #define SPITZ_SCP_MUTE_R 5
  657. #define SPITZ_SCP_CF_POWER 6
  658. #define SPITZ_SCP_LED_ORANGE 7
  659. #define SPITZ_SCP_JK_A 8
  660. #define SPITZ_SCP_ADC_TEMP_ON 9
  661. #define SPITZ_SCP2_IR_ON 1
  662. #define SPITZ_SCP2_AKIN_PULLUP 2
  663. #define SPITZ_SCP2_BACKLIGHT_CONT 7
  664. #define SPITZ_SCP2_BACKLIGHT_ON 8
  665. #define SPITZ_SCP2_MIC_BIAS 9
  666. static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
  667. DeviceState *scp0, DeviceState *scp1)
  668. {
  669. qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
  670. qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
  671. qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
  672. qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
  673. qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
  674. if (scp1) {
  675. qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
  676. qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
  677. }
  678. qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  679. }
  680. #define SPITZ_GPIO_HSYNC 22
  681. #define SPITZ_GPIO_SD_DETECT 9
  682. #define SPITZ_GPIO_SD_WP 81
  683. #define SPITZ_GPIO_ON_RESET 89
  684. #define SPITZ_GPIO_BAT_COVER 90
  685. #define SPITZ_GPIO_CF1_IRQ 105
  686. #define SPITZ_GPIO_CF1_CD 94
  687. #define SPITZ_GPIO_CF2_IRQ 106
  688. #define SPITZ_GPIO_CF2_CD 93
  689. static int spitz_hsync;
  690. static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
  691. {
  692. PXA2xxState *cpu = (PXA2xxState *) opaque;
  693. qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
  694. spitz_hsync ^= 1;
  695. }
  696. static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  697. {
  698. qemu_irq lcd_hsync;
  699. /*
  700. * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
  701. * read to satisfy broken guests that poll-wait for hsync.
  702. * Simulating a real hsync event would be less practical and
  703. * wouldn't guarantee that a guest ever exits the loop.
  704. */
  705. spitz_hsync = 0;
  706. lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
  707. pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
  708. pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
  709. /* MMC/SD host */
  710. pxa2xx_mmci_handlers(cpu->mmc,
  711. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
  712. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
  713. /* Battery lock always closed */
  714. qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
  715. /* Handle reset */
  716. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
  717. /* PCMCIA signals: card's IRQ and Card-Detect */
  718. if (slots >= 1)
  719. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
  720. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
  721. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
  722. if (slots >= 2)
  723. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
  724. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
  725. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
  726. }
  727. /* Board init. */
  728. enum spitz_model_e { spitz, akita, borzoi, terrier };
  729. #define SPITZ_RAM 0x04000000
  730. #define SPITZ_ROM 0x00800000
  731. static struct arm_boot_info spitz_binfo = {
  732. .loader_start = PXA2XX_SDRAM_BASE,
  733. .ram_size = 0x04000000,
  734. };
  735. static void spitz_common_init(ram_addr_t ram_size,
  736. const char *kernel_filename,
  737. const char *kernel_cmdline, const char *initrd_filename,
  738. const char *cpu_model, enum spitz_model_e model, int arm_id)
  739. {
  740. PXA2xxState *cpu;
  741. DeviceState *scp0, *scp1 = NULL;
  742. MemoryRegion *address_space_mem = get_system_memory();
  743. MemoryRegion *rom = g_new(MemoryRegion, 1);
  744. if (!cpu_model)
  745. cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
  746. /* Setup CPU & memory */
  747. cpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
  748. sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
  749. memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM);
  750. memory_region_set_readonly(rom, true);
  751. memory_region_add_subregion(address_space_mem, 0, rom);
  752. /* Setup peripherals */
  753. spitz_keyboard_register(cpu);
  754. spitz_ssp_attach(cpu);
  755. scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
  756. if (model != akita) {
  757. scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
  758. }
  759. spitz_scoop_gpio_setup(cpu, scp0, scp1);
  760. spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
  761. spitz_i2c_setup(cpu);
  762. if (model == akita)
  763. spitz_akita_i2c_setup(cpu);
  764. if (model == terrier)
  765. /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
  766. spitz_microdrive_attach(cpu, 1);
  767. else if (model != akita)
  768. /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
  769. spitz_microdrive_attach(cpu, 0);
  770. spitz_binfo.kernel_filename = kernel_filename;
  771. spitz_binfo.kernel_cmdline = kernel_cmdline;
  772. spitz_binfo.initrd_filename = initrd_filename;
  773. spitz_binfo.board_id = arm_id;
  774. arm_load_kernel(cpu->env, &spitz_binfo);
  775. sl_bootparam_write(SL_PXA_PARAM_BASE);
  776. }
  777. static void spitz_init(ram_addr_t ram_size,
  778. const char *boot_device,
  779. const char *kernel_filename, const char *kernel_cmdline,
  780. const char *initrd_filename, const char *cpu_model)
  781. {
  782. spitz_common_init(ram_size, kernel_filename,
  783. kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
  784. }
  785. static void borzoi_init(ram_addr_t ram_size,
  786. const char *boot_device,
  787. const char *kernel_filename, const char *kernel_cmdline,
  788. const char *initrd_filename, const char *cpu_model)
  789. {
  790. spitz_common_init(ram_size, kernel_filename,
  791. kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
  792. }
  793. static void akita_init(ram_addr_t ram_size,
  794. const char *boot_device,
  795. const char *kernel_filename, const char *kernel_cmdline,
  796. const char *initrd_filename, const char *cpu_model)
  797. {
  798. spitz_common_init(ram_size, kernel_filename,
  799. kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
  800. }
  801. static void terrier_init(ram_addr_t ram_size,
  802. const char *boot_device,
  803. const char *kernel_filename, const char *kernel_cmdline,
  804. const char *initrd_filename, const char *cpu_model)
  805. {
  806. spitz_common_init(ram_size, kernel_filename,
  807. kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
  808. }
  809. static QEMUMachine akitapda_machine = {
  810. .name = "akita",
  811. .desc = "Akita PDA (PXA270)",
  812. .init = akita_init,
  813. };
  814. static QEMUMachine spitzpda_machine = {
  815. .name = "spitz",
  816. .desc = "Spitz PDA (PXA270)",
  817. .init = spitz_init,
  818. };
  819. static QEMUMachine borzoipda_machine = {
  820. .name = "borzoi",
  821. .desc = "Borzoi PDA (PXA270)",
  822. .init = borzoi_init,
  823. };
  824. static QEMUMachine terrierpda_machine = {
  825. .name = "terrier",
  826. .desc = "Terrier PDA (PXA270)",
  827. .init = terrier_init,
  828. };
  829. static void spitz_machine_init(void)
  830. {
  831. qemu_register_machine(&akitapda_machine);
  832. qemu_register_machine(&spitzpda_machine);
  833. qemu_register_machine(&borzoipda_machine);
  834. qemu_register_machine(&terrierpda_machine);
  835. }
  836. machine_init(spitz_machine_init);
  837. static bool is_version_0(void *opaque, int version_id)
  838. {
  839. return version_id == 0;
  840. }
  841. static VMStateDescription vmstate_sl_nand_info = {
  842. .name = "sl-nand",
  843. .version_id = 0,
  844. .minimum_version_id = 0,
  845. .minimum_version_id_old = 0,
  846. .fields = (VMStateField []) {
  847. VMSTATE_UINT8(ctl, SLNANDState),
  848. VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
  849. VMSTATE_END_OF_LIST(),
  850. },
  851. };
  852. static SysBusDeviceInfo sl_nand_info = {
  853. .init = sl_nand_init,
  854. .qdev.name = "sl-nand",
  855. .qdev.size = sizeof(SLNANDState),
  856. .qdev.vmsd = &vmstate_sl_nand_info,
  857. .qdev.props = (Property []) {
  858. DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
  859. DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
  860. DEFINE_PROP_END_OF_LIST(),
  861. },
  862. };
  863. static VMStateDescription vmstate_spitz_kbd = {
  864. .name = "spitz-keyboard",
  865. .version_id = 1,
  866. .minimum_version_id = 0,
  867. .minimum_version_id_old = 0,
  868. .post_load = spitz_keyboard_post_load,
  869. .fields = (VMStateField []) {
  870. VMSTATE_UINT16(sense_state, SpitzKeyboardState),
  871. VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
  872. VMSTATE_UNUSED_TEST(is_version_0, 5),
  873. VMSTATE_END_OF_LIST(),
  874. },
  875. };
  876. static SysBusDeviceInfo spitz_keyboard_info = {
  877. .init = spitz_keyboard_init,
  878. .qdev.name = "spitz-keyboard",
  879. .qdev.size = sizeof(SpitzKeyboardState),
  880. .qdev.vmsd = &vmstate_spitz_kbd,
  881. .qdev.props = (Property []) {
  882. DEFINE_PROP_END_OF_LIST(),
  883. },
  884. };
  885. static const VMStateDescription vmstate_corgi_ssp_regs = {
  886. .name = "corgi-ssp",
  887. .version_id = 1,
  888. .minimum_version_id = 1,
  889. .minimum_version_id_old = 1,
  890. .fields = (VMStateField []) {
  891. VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
  892. VMSTATE_END_OF_LIST(),
  893. }
  894. };
  895. static SSISlaveInfo corgi_ssp_info = {
  896. .qdev.name = "corgi-ssp",
  897. .qdev.size = sizeof(CorgiSSPState),
  898. .qdev.vmsd = &vmstate_corgi_ssp_regs,
  899. .init = corgi_ssp_init,
  900. .transfer = corgi_ssp_transfer
  901. };
  902. static const VMStateDescription vmstate_spitz_lcdtg_regs = {
  903. .name = "spitz-lcdtg",
  904. .version_id = 1,
  905. .minimum_version_id = 1,
  906. .minimum_version_id_old = 1,
  907. .fields = (VMStateField []) {
  908. VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
  909. VMSTATE_UINT32(bl_power, SpitzLCDTG),
  910. VMSTATE_END_OF_LIST(),
  911. }
  912. };
  913. static SSISlaveInfo spitz_lcdtg_info = {
  914. .qdev.name = "spitz-lcdtg",
  915. .qdev.size = sizeof(SpitzLCDTG),
  916. .qdev.vmsd = &vmstate_spitz_lcdtg_regs,
  917. .init = spitz_lcdtg_init,
  918. .transfer = spitz_lcdtg_transfer
  919. };
  920. static void spitz_register_devices(void)
  921. {
  922. ssi_register_slave(&corgi_ssp_info);
  923. ssi_register_slave(&spitz_lcdtg_info);
  924. sysbus_register_withprop(&spitz_keyboard_info);
  925. sysbus_register_withprop(&sl_nand_info);
  926. }
  927. device_init(spitz_register_devices)