spapr_hcall.c 20 KB

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  1. #include "sysemu.h"
  2. #include "cpu.h"
  3. #include "dyngen-exec.h"
  4. #include "qemu-char.h"
  5. #include "sysemu.h"
  6. #include "qemu-char.h"
  7. #include "helper_regs.h"
  8. #include "hw/spapr.h"
  9. #define HPTES_PER_GROUP 8
  10. #define HPTE_V_SSIZE_SHIFT 62
  11. #define HPTE_V_AVPN_SHIFT 7
  12. #define HPTE_V_AVPN 0x3fffffffffffff80ULL
  13. #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  14. #define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
  15. #define HPTE_V_BOLTED 0x0000000000000010ULL
  16. #define HPTE_V_LOCK 0x0000000000000008ULL
  17. #define HPTE_V_LARGE 0x0000000000000004ULL
  18. #define HPTE_V_SECONDARY 0x0000000000000002ULL
  19. #define HPTE_V_VALID 0x0000000000000001ULL
  20. #define HPTE_R_PP0 0x8000000000000000ULL
  21. #define HPTE_R_TS 0x4000000000000000ULL
  22. #define HPTE_R_KEY_HI 0x3000000000000000ULL
  23. #define HPTE_R_RPN_SHIFT 12
  24. #define HPTE_R_RPN 0x3ffffffffffff000ULL
  25. #define HPTE_R_FLAGS 0x00000000000003ffULL
  26. #define HPTE_R_PP 0x0000000000000003ULL
  27. #define HPTE_R_N 0x0000000000000004ULL
  28. #define HPTE_R_G 0x0000000000000008ULL
  29. #define HPTE_R_M 0x0000000000000010ULL
  30. #define HPTE_R_I 0x0000000000000020ULL
  31. #define HPTE_R_W 0x0000000000000040ULL
  32. #define HPTE_R_WIMG 0x0000000000000078ULL
  33. #define HPTE_R_C 0x0000000000000080ULL
  34. #define HPTE_R_R 0x0000000000000100ULL
  35. #define HPTE_R_KEY_LO 0x0000000000000e00ULL
  36. #define HPTE_V_1TB_SEG 0x4000000000000000ULL
  37. #define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
  38. #define HPTE_V_HVLOCK 0x40ULL
  39. static inline int lock_hpte(void *hpte, target_ulong bits)
  40. {
  41. uint64_t pteh;
  42. pteh = ldq_p(hpte);
  43. /* We're protected by qemu's global lock here */
  44. if (pteh & bits) {
  45. return 0;
  46. }
  47. stq_p(hpte, pteh | HPTE_V_HVLOCK);
  48. return 1;
  49. }
  50. static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
  51. target_ulong pte_index)
  52. {
  53. target_ulong rb, va_low;
  54. rb = (v & ~0x7fULL) << 16; /* AVA field */
  55. va_low = pte_index >> 3;
  56. if (v & HPTE_V_SECONDARY) {
  57. va_low = ~va_low;
  58. }
  59. /* xor vsid from AVA */
  60. if (!(v & HPTE_V_1TB_SEG)) {
  61. va_low ^= v >> 12;
  62. } else {
  63. va_low ^= v >> 24;
  64. }
  65. va_low &= 0x7ff;
  66. if (v & HPTE_V_LARGE) {
  67. rb |= 1; /* L field */
  68. #if 0 /* Disable that P7 specific bit for now */
  69. if (r & 0xff000) {
  70. /* non-16MB large page, must be 64k */
  71. /* (masks depend on page size) */
  72. rb |= 0x1000; /* page encoding in LP field */
  73. rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
  74. rb |= (va_low & 0xfe); /* AVAL field */
  75. }
  76. #endif
  77. } else {
  78. /* 4kB page */
  79. rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */
  80. }
  81. rb |= (v >> 54) & 0x300; /* B field */
  82. return rb;
  83. }
  84. static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr,
  85. target_ulong opcode, target_ulong *args)
  86. {
  87. target_ulong flags = args[0];
  88. target_ulong pte_index = args[1];
  89. target_ulong pteh = args[2];
  90. target_ulong ptel = args[3];
  91. target_ulong page_shift = 12;
  92. target_ulong raddr;
  93. target_ulong i;
  94. uint8_t *hpte;
  95. /* only handle 4k and 16M pages for now */
  96. if (pteh & HPTE_V_LARGE) {
  97. #if 0 /* We don't support 64k pages yet */
  98. if ((ptel & 0xf000) == 0x1000) {
  99. /* 64k page */
  100. } else
  101. #endif
  102. if ((ptel & 0xff000) == 0) {
  103. /* 16M page */
  104. page_shift = 24;
  105. /* lowest AVA bit must be 0 for 16M pages */
  106. if (pteh & 0x80) {
  107. return H_PARAMETER;
  108. }
  109. } else {
  110. return H_PARAMETER;
  111. }
  112. }
  113. raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);
  114. if (raddr < spapr->ram_limit) {
  115. /* Regular RAM - should have WIMG=0010 */
  116. if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
  117. return H_PARAMETER;
  118. }
  119. } else {
  120. /* Looks like an IO address */
  121. /* FIXME: What WIMG combinations could be sensible for IO?
  122. * For now we allow WIMG=010x, but are there others? */
  123. /* FIXME: Should we check against registered IO addresses? */
  124. if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
  125. return H_PARAMETER;
  126. }
  127. }
  128. pteh &= ~0x60ULL;
  129. if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
  130. return H_PARAMETER;
  131. }
  132. if (likely((flags & H_EXACT) == 0)) {
  133. pte_index &= ~7ULL;
  134. hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
  135. for (i = 0; ; ++i) {
  136. if (i == 8) {
  137. return H_PTEG_FULL;
  138. }
  139. if (((ldq_p(hpte) & HPTE_V_VALID) == 0) &&
  140. lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
  141. break;
  142. }
  143. hpte += HASH_PTE_SIZE_64;
  144. }
  145. } else {
  146. i = 0;
  147. hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
  148. if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
  149. return H_PTEG_FULL;
  150. }
  151. }
  152. stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
  153. /* eieio(); FIXME: need some sort of barrier for smp? */
  154. stq_p(hpte, pteh);
  155. assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
  156. args[0] = pte_index + i;
  157. return H_SUCCESS;
  158. }
  159. enum {
  160. REMOVE_SUCCESS = 0,
  161. REMOVE_NOT_FOUND = 1,
  162. REMOVE_PARM = 2,
  163. REMOVE_HW = 3,
  164. };
  165. static target_ulong remove_hpte(CPUState *env, target_ulong ptex,
  166. target_ulong avpn,
  167. target_ulong flags,
  168. target_ulong *vp, target_ulong *rp)
  169. {
  170. uint8_t *hpte;
  171. target_ulong v, r, rb;
  172. if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
  173. return REMOVE_PARM;
  174. }
  175. hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);
  176. while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
  177. /* We have no real concurrency in qemu soft-emulation, so we
  178. * will never actually have a contested lock */
  179. assert(0);
  180. }
  181. v = ldq_p(hpte);
  182. r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
  183. if ((v & HPTE_V_VALID) == 0 ||
  184. ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
  185. ((flags & H_ANDCOND) && (v & avpn) != 0)) {
  186. stq_p(hpte, v & ~HPTE_V_HVLOCK);
  187. assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
  188. return REMOVE_NOT_FOUND;
  189. }
  190. *vp = v & ~HPTE_V_HVLOCK;
  191. *rp = r;
  192. stq_p(hpte, 0);
  193. rb = compute_tlbie_rb(v, r, ptex);
  194. ppc_tlb_invalidate_one(env, rb);
  195. assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
  196. return REMOVE_SUCCESS;
  197. }
  198. static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
  199. target_ulong opcode, target_ulong *args)
  200. {
  201. target_ulong flags = args[0];
  202. target_ulong pte_index = args[1];
  203. target_ulong avpn = args[2];
  204. int ret;
  205. ret = remove_hpte(env, pte_index, avpn, flags,
  206. &args[0], &args[1]);
  207. switch (ret) {
  208. case REMOVE_SUCCESS:
  209. return H_SUCCESS;
  210. case REMOVE_NOT_FOUND:
  211. return H_NOT_FOUND;
  212. case REMOVE_PARM:
  213. return H_PARAMETER;
  214. case REMOVE_HW:
  215. return H_HARDWARE;
  216. }
  217. assert(0);
  218. }
  219. #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
  220. #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
  221. #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
  222. #define H_BULK_REMOVE_END 0xc000000000000000ULL
  223. #define H_BULK_REMOVE_CODE 0x3000000000000000ULL
  224. #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
  225. #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
  226. #define H_BULK_REMOVE_PARM 0x2000000000000000ULL
  227. #define H_BULK_REMOVE_HW 0x3000000000000000ULL
  228. #define H_BULK_REMOVE_RC 0x0c00000000000000ULL
  229. #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
  230. #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
  231. #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
  232. #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
  233. #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
  234. #define H_BULK_REMOVE_MAX_BATCH 4
  235. static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr,
  236. target_ulong opcode, target_ulong *args)
  237. {
  238. int i;
  239. for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
  240. target_ulong *tsh = &args[i*2];
  241. target_ulong tsl = args[i*2 + 1];
  242. target_ulong v, r, ret;
  243. if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
  244. break;
  245. } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
  246. return H_PARAMETER;
  247. }
  248. *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
  249. *tsh |= H_BULK_REMOVE_RESPONSE;
  250. if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
  251. *tsh |= H_BULK_REMOVE_PARM;
  252. return H_PARAMETER;
  253. }
  254. ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl,
  255. (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
  256. &v, &r);
  257. *tsh |= ret << 60;
  258. switch (ret) {
  259. case REMOVE_SUCCESS:
  260. *tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
  261. break;
  262. case REMOVE_PARM:
  263. return H_PARAMETER;
  264. case REMOVE_HW:
  265. return H_HARDWARE;
  266. }
  267. }
  268. return H_SUCCESS;
  269. }
  270. static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
  271. target_ulong opcode, target_ulong *args)
  272. {
  273. target_ulong flags = args[0];
  274. target_ulong pte_index = args[1];
  275. target_ulong avpn = args[2];
  276. uint8_t *hpte;
  277. target_ulong v, r, rb;
  278. if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
  279. return H_PARAMETER;
  280. }
  281. hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
  282. while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
  283. /* We have no real concurrency in qemu soft-emulation, so we
  284. * will never actually have a contested lock */
  285. assert(0);
  286. }
  287. v = ldq_p(hpte);
  288. r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
  289. if ((v & HPTE_V_VALID) == 0 ||
  290. ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
  291. stq_p(hpte, v & ~HPTE_V_HVLOCK);
  292. assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
  293. return H_NOT_FOUND;
  294. }
  295. r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
  296. HPTE_R_KEY_HI | HPTE_R_KEY_LO);
  297. r |= (flags << 55) & HPTE_R_PP0;
  298. r |= (flags << 48) & HPTE_R_KEY_HI;
  299. r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
  300. rb = compute_tlbie_rb(v, r, pte_index);
  301. stq_p(hpte, v & ~HPTE_V_VALID);
  302. ppc_tlb_invalidate_one(env, rb);
  303. stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
  304. /* Don't need a memory barrier, due to qemu's global lock */
  305. stq_p(hpte, v & ~HPTE_V_HVLOCK);
  306. assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
  307. return H_SUCCESS;
  308. }
  309. static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
  310. target_ulong opcode, target_ulong *args)
  311. {
  312. /* FIXME: actually implement this */
  313. return H_HARDWARE;
  314. }
  315. #define FLAGS_REGISTER_VPA 0x0000200000000000ULL
  316. #define FLAGS_REGISTER_DTL 0x0000400000000000ULL
  317. #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
  318. #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
  319. #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
  320. #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
  321. #define VPA_MIN_SIZE 640
  322. #define VPA_SIZE_OFFSET 0x4
  323. #define VPA_SHARED_PROC_OFFSET 0x9
  324. #define VPA_SHARED_PROC_VAL 0x2
  325. static target_ulong register_vpa(CPUState *env, target_ulong vpa)
  326. {
  327. uint16_t size;
  328. uint8_t tmp;
  329. if (vpa == 0) {
  330. hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
  331. return H_HARDWARE;
  332. }
  333. if (vpa % env->dcache_line_size) {
  334. return H_PARAMETER;
  335. }
  336. /* FIXME: bounds check the address */
  337. size = lduw_be_phys(vpa + 0x4);
  338. if (size < VPA_MIN_SIZE) {
  339. return H_PARAMETER;
  340. }
  341. /* VPA is not allowed to cross a page boundary */
  342. if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
  343. return H_PARAMETER;
  344. }
  345. env->vpa = vpa;
  346. tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET);
  347. tmp |= VPA_SHARED_PROC_VAL;
  348. stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp);
  349. return H_SUCCESS;
  350. }
  351. static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
  352. {
  353. if (env->slb_shadow) {
  354. return H_RESOURCE;
  355. }
  356. if (env->dispatch_trace_log) {
  357. return H_RESOURCE;
  358. }
  359. env->vpa = 0;
  360. return H_SUCCESS;
  361. }
  362. static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
  363. {
  364. uint32_t size;
  365. if (addr == 0) {
  366. hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
  367. return H_HARDWARE;
  368. }
  369. size = ldl_be_phys(addr + 0x4);
  370. if (size < 0x8) {
  371. return H_PARAMETER;
  372. }
  373. if ((addr / 4096) != ((addr + size - 1) / 4096)) {
  374. return H_PARAMETER;
  375. }
  376. if (!env->vpa) {
  377. return H_RESOURCE;
  378. }
  379. env->slb_shadow = addr;
  380. return H_SUCCESS;
  381. }
  382. static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr)
  383. {
  384. env->slb_shadow = 0;
  385. return H_SUCCESS;
  386. }
  387. static target_ulong register_dtl(CPUState *env, target_ulong addr)
  388. {
  389. uint32_t size;
  390. if (addr == 0) {
  391. hcall_dprintf("Can't cope with DTL at logical 0\n");
  392. return H_HARDWARE;
  393. }
  394. size = ldl_be_phys(addr + 0x4);
  395. if (size < 48) {
  396. return H_PARAMETER;
  397. }
  398. if (!env->vpa) {
  399. return H_RESOURCE;
  400. }
  401. env->dispatch_trace_log = addr;
  402. env->dtl_size = size;
  403. return H_SUCCESS;
  404. }
  405. static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
  406. {
  407. env->dispatch_trace_log = 0;
  408. env->dtl_size = 0;
  409. return H_SUCCESS;
  410. }
  411. static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
  412. target_ulong opcode, target_ulong *args)
  413. {
  414. target_ulong flags = args[0];
  415. target_ulong procno = args[1];
  416. target_ulong vpa = args[2];
  417. target_ulong ret = H_PARAMETER;
  418. CPUState *tenv;
  419. for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
  420. if (tenv->cpu_index == procno) {
  421. break;
  422. }
  423. }
  424. if (!tenv) {
  425. return H_PARAMETER;
  426. }
  427. switch (flags) {
  428. case FLAGS_REGISTER_VPA:
  429. ret = register_vpa(tenv, vpa);
  430. break;
  431. case FLAGS_DEREGISTER_VPA:
  432. ret = deregister_vpa(tenv, vpa);
  433. break;
  434. case FLAGS_REGISTER_SLBSHADOW:
  435. ret = register_slb_shadow(tenv, vpa);
  436. break;
  437. case FLAGS_DEREGISTER_SLBSHADOW:
  438. ret = deregister_slb_shadow(tenv, vpa);
  439. break;
  440. case FLAGS_REGISTER_DTL:
  441. ret = register_dtl(tenv, vpa);
  442. break;
  443. case FLAGS_DEREGISTER_DTL:
  444. ret = deregister_dtl(tenv, vpa);
  445. break;
  446. }
  447. return ret;
  448. }
  449. static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
  450. target_ulong opcode, target_ulong *args)
  451. {
  452. env->msr |= (1ULL << MSR_EE);
  453. hreg_compute_hflags(env);
  454. if (!cpu_has_work(env)) {
  455. env->halted = 1;
  456. }
  457. return H_SUCCESS;
  458. }
  459. static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
  460. target_ulong opcode, target_ulong *args)
  461. {
  462. target_ulong rtas_r3 = args[0];
  463. uint32_t token = ldl_be_phys(rtas_r3);
  464. uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
  465. uint32_t nret = ldl_be_phys(rtas_r3 + 8);
  466. return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
  467. nret, rtas_r3 + 12 + 4*nargs);
  468. }
  469. static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr,
  470. target_ulong opcode, target_ulong *args)
  471. {
  472. target_ulong size = args[0];
  473. target_ulong addr = args[1];
  474. switch (size) {
  475. case 1:
  476. args[0] = ldub_phys(addr);
  477. return H_SUCCESS;
  478. case 2:
  479. args[0] = lduw_phys(addr);
  480. return H_SUCCESS;
  481. case 4:
  482. args[0] = ldl_phys(addr);
  483. return H_SUCCESS;
  484. case 8:
  485. args[0] = ldq_phys(addr);
  486. return H_SUCCESS;
  487. }
  488. return H_PARAMETER;
  489. }
  490. static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr,
  491. target_ulong opcode, target_ulong *args)
  492. {
  493. target_ulong size = args[0];
  494. target_ulong addr = args[1];
  495. target_ulong val = args[2];
  496. switch (size) {
  497. case 1:
  498. stb_phys(addr, val);
  499. return H_SUCCESS;
  500. case 2:
  501. stw_phys(addr, val);
  502. return H_SUCCESS;
  503. case 4:
  504. stl_phys(addr, val);
  505. return H_SUCCESS;
  506. case 8:
  507. stq_phys(addr, val);
  508. return H_SUCCESS;
  509. }
  510. return H_PARAMETER;
  511. }
  512. static target_ulong h_logical_icbi(CPUState *env, sPAPREnvironment *spapr,
  513. target_ulong opcode, target_ulong *args)
  514. {
  515. /* Nothing to do on emulation, KVM will trap this in the kernel */
  516. return H_SUCCESS;
  517. }
  518. static target_ulong h_logical_dcbf(CPUState *env, sPAPREnvironment *spapr,
  519. target_ulong opcode, target_ulong *args)
  520. {
  521. /* Nothing to do on emulation, KVM will trap this in the kernel */
  522. return H_SUCCESS;
  523. }
  524. static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
  525. static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
  526. void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
  527. {
  528. spapr_hcall_fn *slot;
  529. if (opcode <= MAX_HCALL_OPCODE) {
  530. assert((opcode & 0x3) == 0);
  531. slot = &papr_hypercall_table[opcode / 4];
  532. } else {
  533. assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
  534. slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
  535. }
  536. assert(!(*slot) || (fn == *slot));
  537. *slot = fn;
  538. }
  539. target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
  540. target_ulong *args)
  541. {
  542. if (msr_pr) {
  543. hcall_dprintf("Hypercall made with MSR[PR]=1\n");
  544. return H_PRIVILEGE;
  545. }
  546. if ((opcode <= MAX_HCALL_OPCODE)
  547. && ((opcode & 0x3) == 0)) {
  548. spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
  549. if (fn) {
  550. return fn(env, spapr, opcode, args);
  551. }
  552. } else if ((opcode >= KVMPPC_HCALL_BASE) &&
  553. (opcode <= KVMPPC_HCALL_MAX)) {
  554. spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
  555. if (fn) {
  556. return fn(env, spapr, opcode, args);
  557. }
  558. }
  559. hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
  560. return H_FUNCTION;
  561. }
  562. static void hypercall_init(void)
  563. {
  564. /* hcall-pft */
  565. spapr_register_hypercall(H_ENTER, h_enter);
  566. spapr_register_hypercall(H_REMOVE, h_remove);
  567. spapr_register_hypercall(H_PROTECT, h_protect);
  568. /* hcall-bulk */
  569. spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
  570. /* hcall-dabr */
  571. spapr_register_hypercall(H_SET_DABR, h_set_dabr);
  572. /* hcall-splpar */
  573. spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
  574. spapr_register_hypercall(H_CEDE, h_cede);
  575. /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
  576. * here between the "CI" and the "CACHE" variants, they will use whatever
  577. * mapping attributes qemu is using. When using KVM, the kernel will
  578. * enforce the attributes more strongly
  579. */
  580. spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
  581. spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
  582. spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
  583. spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
  584. spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
  585. spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
  586. /* qemu/KVM-PPC specific hcalls */
  587. spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
  588. }
  589. device_init(hypercall_init);