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spapr.c 20 KB

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  1. /*
  2. * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
  3. *
  4. * Copyright (c) 2004-2007 Fabrice Bellard
  5. * Copyright (c) 2007 Jocelyn Mayer
  6. * Copyright (c) 2010 David Gibson, IBM Corporation.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice shall be included in
  16. * all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. *
  26. */
  27. #include "sysemu.h"
  28. #include "hw.h"
  29. #include "elf.h"
  30. #include "net.h"
  31. #include "blockdev.h"
  32. #include "cpus.h"
  33. #include "kvm.h"
  34. #include "kvm_ppc.h"
  35. #include "hw/boards.h"
  36. #include "hw/ppc.h"
  37. #include "hw/loader.h"
  38. #include "hw/spapr.h"
  39. #include "hw/spapr_vio.h"
  40. #include "hw/spapr_pci.h"
  41. #include "hw/xics.h"
  42. #include "kvm.h"
  43. #include "kvm_ppc.h"
  44. #include "pci.h"
  45. #include "exec-memory.h"
  46. #include <libfdt.h>
  47. #define KERNEL_LOAD_ADDR 0x00000000
  48. #define INITRD_LOAD_ADDR 0x02800000
  49. #define FDT_MAX_SIZE 0x10000
  50. #define RTAS_MAX_SIZE 0x10000
  51. #define FW_MAX_SIZE 0x400000
  52. #define FW_FILE_NAME "slof.bin"
  53. #define MIN_RMA_SLOF 128UL
  54. #define TIMEBASE_FREQ 512000000ULL
  55. #define MAX_CPUS 256
  56. #define XICS_IRQS 1024
  57. #define SPAPR_PCI_BUID 0x800000020000001ULL
  58. #define SPAPR_PCI_MEM_WIN_ADDR (0x10000000000ULL + 0xA0000000)
  59. #define SPAPR_PCI_MEM_WIN_SIZE 0x20000000
  60. #define SPAPR_PCI_IO_WIN_ADDR (0x10000000000ULL + 0x80000000)
  61. #define PHANDLE_XICP 0x00001111
  62. sPAPREnvironment *spapr;
  63. qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
  64. {
  65. uint32_t irq;
  66. qemu_irq qirq;
  67. if (hint) {
  68. irq = hint;
  69. /* FIXME: we should probably check for collisions somehow */
  70. } else {
  71. irq = spapr->next_irq++;
  72. }
  73. qirq = xics_find_qirq(spapr->icp, irq);
  74. if (!qirq) {
  75. return NULL;
  76. }
  77. if (irq_num) {
  78. *irq_num = irq;
  79. }
  80. return qirq;
  81. }
  82. static void *spapr_create_fdt_skel(const char *cpu_model,
  83. target_phys_addr_t rma_size,
  84. target_phys_addr_t initrd_base,
  85. target_phys_addr_t initrd_size,
  86. const char *boot_device,
  87. const char *kernel_cmdline,
  88. long hash_shift)
  89. {
  90. void *fdt;
  91. CPUState *env;
  92. uint64_t mem_reg_property_rma[] = { 0, cpu_to_be64(rma_size) };
  93. uint64_t mem_reg_property_nonrma[] = { cpu_to_be64(rma_size),
  94. cpu_to_be64(ram_size - rma_size) };
  95. uint32_t start_prop = cpu_to_be32(initrd_base);
  96. uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
  97. uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
  98. char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
  99. "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
  100. uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
  101. int i;
  102. char *modelname;
  103. int smt = kvmppc_smt_threads();
  104. #define _FDT(exp) \
  105. do { \
  106. int ret = (exp); \
  107. if (ret < 0) { \
  108. fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
  109. #exp, fdt_strerror(ret)); \
  110. exit(1); \
  111. } \
  112. } while (0)
  113. fdt = g_malloc0(FDT_MAX_SIZE);
  114. _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
  115. _FDT((fdt_finish_reservemap(fdt)));
  116. /* Root node */
  117. _FDT((fdt_begin_node(fdt, "")));
  118. _FDT((fdt_property_string(fdt, "device_type", "chrp")));
  119. _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
  120. _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
  121. _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
  122. /* /chosen */
  123. _FDT((fdt_begin_node(fdt, "chosen")));
  124. _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
  125. _FDT((fdt_property(fdt, "linux,initrd-start",
  126. &start_prop, sizeof(start_prop))));
  127. _FDT((fdt_property(fdt, "linux,initrd-end",
  128. &end_prop, sizeof(end_prop))));
  129. _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
  130. /*
  131. * Because we don't always invoke any firmware, we can't rely on
  132. * that to do BAR allocation. Long term, we should probably do
  133. * that ourselves, but for now, this setting (plus advertising the
  134. * current BARs as 0) causes sufficiently recent kernels to to the
  135. * BAR assignment themselves */
  136. _FDT((fdt_property_cell(fdt, "linux,pci-probe-only", 0)));
  137. _FDT((fdt_end_node(fdt)));
  138. /* memory node(s) */
  139. _FDT((fdt_begin_node(fdt, "memory@0")));
  140. _FDT((fdt_property_string(fdt, "device_type", "memory")));
  141. _FDT((fdt_property(fdt, "reg", mem_reg_property_rma,
  142. sizeof(mem_reg_property_rma))));
  143. _FDT((fdt_end_node(fdt)));
  144. if (ram_size > rma_size) {
  145. char mem_name[32];
  146. sprintf(mem_name, "memory@%" PRIx64, (uint64_t)rma_size);
  147. _FDT((fdt_begin_node(fdt, mem_name)));
  148. _FDT((fdt_property_string(fdt, "device_type", "memory")));
  149. _FDT((fdt_property(fdt, "reg", mem_reg_property_nonrma,
  150. sizeof(mem_reg_property_nonrma))));
  151. _FDT((fdt_end_node(fdt)));
  152. }
  153. /* cpus */
  154. _FDT((fdt_begin_node(fdt, "cpus")));
  155. _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
  156. _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
  157. modelname = g_strdup(cpu_model);
  158. for (i = 0; i < strlen(modelname); i++) {
  159. modelname[i] = toupper(modelname[i]);
  160. }
  161. for (env = first_cpu; env != NULL; env = env->next_cpu) {
  162. int index = env->cpu_index;
  163. uint32_t servers_prop[smp_threads];
  164. uint32_t gservers_prop[smp_threads * 2];
  165. char *nodename;
  166. uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
  167. 0xffffffff, 0xffffffff};
  168. uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
  169. uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
  170. if ((index % smt) != 0) {
  171. continue;
  172. }
  173. if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
  174. fprintf(stderr, "Allocation failure\n");
  175. exit(1);
  176. }
  177. _FDT((fdt_begin_node(fdt, nodename)));
  178. free(nodename);
  179. _FDT((fdt_property_cell(fdt, "reg", index)));
  180. _FDT((fdt_property_string(fdt, "device_type", "cpu")));
  181. _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
  182. _FDT((fdt_property_cell(fdt, "dcache-block-size",
  183. env->dcache_line_size)));
  184. _FDT((fdt_property_cell(fdt, "icache-block-size",
  185. env->icache_line_size)));
  186. _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
  187. _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
  188. _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
  189. _FDT((fdt_property(fdt, "ibm,pft-size",
  190. pft_size_prop, sizeof(pft_size_prop))));
  191. _FDT((fdt_property_string(fdt, "status", "okay")));
  192. _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
  193. /* Build interrupt servers and gservers properties */
  194. for (i = 0; i < smp_threads; i++) {
  195. servers_prop[i] = cpu_to_be32(index + i);
  196. /* Hack, direct the group queues back to cpu 0 */
  197. gservers_prop[i*2] = cpu_to_be32(index + i);
  198. gservers_prop[i*2 + 1] = 0;
  199. }
  200. _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
  201. servers_prop, sizeof(servers_prop))));
  202. _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
  203. gservers_prop, sizeof(gservers_prop))));
  204. if (env->mmu_model & POWERPC_MMU_1TSEG) {
  205. _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
  206. segs, sizeof(segs))));
  207. }
  208. /* Advertise VMX/VSX (vector extensions) if available
  209. * 0 / no property == no vector extensions
  210. * 1 == VMX / Altivec available
  211. * 2 == VSX available */
  212. if (env->insns_flags & PPC_ALTIVEC) {
  213. uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
  214. _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
  215. }
  216. /* Advertise DFP (Decimal Floating Point) if available
  217. * 0 / no property == no DFP
  218. * 1 == DFP available */
  219. if (env->insns_flags2 & PPC2_DFP) {
  220. _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
  221. }
  222. _FDT((fdt_end_node(fdt)));
  223. }
  224. g_free(modelname);
  225. _FDT((fdt_end_node(fdt)));
  226. /* RTAS */
  227. _FDT((fdt_begin_node(fdt, "rtas")));
  228. _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
  229. sizeof(hypertas_prop))));
  230. _FDT((fdt_end_node(fdt)));
  231. /* interrupt controller */
  232. _FDT((fdt_begin_node(fdt, "interrupt-controller")));
  233. _FDT((fdt_property_string(fdt, "device_type",
  234. "PowerPC-External-Interrupt-Presentation")));
  235. _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
  236. _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
  237. _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
  238. interrupt_server_ranges_prop,
  239. sizeof(interrupt_server_ranges_prop))));
  240. _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
  241. _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
  242. _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
  243. _FDT((fdt_end_node(fdt)));
  244. /* vdevice */
  245. _FDT((fdt_begin_node(fdt, "vdevice")));
  246. _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
  247. _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
  248. _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
  249. _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
  250. _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
  251. _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
  252. _FDT((fdt_end_node(fdt)));
  253. _FDT((fdt_end_node(fdt))); /* close root node */
  254. _FDT((fdt_finish(fdt)));
  255. return fdt;
  256. }
  257. static void spapr_finalize_fdt(sPAPREnvironment *spapr,
  258. target_phys_addr_t fdt_addr,
  259. target_phys_addr_t rtas_addr,
  260. target_phys_addr_t rtas_size)
  261. {
  262. int ret;
  263. void *fdt;
  264. sPAPRPHBState *phb;
  265. fdt = g_malloc(FDT_MAX_SIZE);
  266. /* open out the base tree into a temp buffer for the final tweaks */
  267. _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
  268. ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
  269. if (ret < 0) {
  270. fprintf(stderr, "couldn't setup vio devices in fdt\n");
  271. exit(1);
  272. }
  273. QLIST_FOREACH(phb, &spapr->phbs, list) {
  274. ret = spapr_populate_pci_devices(phb, PHANDLE_XICP, fdt);
  275. }
  276. if (ret < 0) {
  277. fprintf(stderr, "couldn't setup PCI devices in fdt\n");
  278. exit(1);
  279. }
  280. /* RTAS */
  281. ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
  282. if (ret < 0) {
  283. fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
  284. }
  285. spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
  286. _FDT((fdt_pack(fdt)));
  287. cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
  288. g_free(fdt);
  289. }
  290. static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
  291. {
  292. return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
  293. }
  294. static void emulate_spapr_hypercall(CPUState *env)
  295. {
  296. env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
  297. }
  298. static void spapr_reset(void *opaque)
  299. {
  300. sPAPREnvironment *spapr = (sPAPREnvironment *)opaque;
  301. fprintf(stderr, "sPAPR reset\n");
  302. /* flush out the hash table */
  303. memset(spapr->htab, 0, spapr->htab_size);
  304. /* Load the fdt */
  305. spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
  306. spapr->rtas_size);
  307. /* Set up the entry state */
  308. first_cpu->gpr[3] = spapr->fdt_addr;
  309. first_cpu->gpr[5] = 0;
  310. first_cpu->halted = 0;
  311. first_cpu->nip = spapr->entry_point;
  312. }
  313. /* pSeries LPAR / sPAPR hardware init */
  314. static void ppc_spapr_init(ram_addr_t ram_size,
  315. const char *boot_device,
  316. const char *kernel_filename,
  317. const char *kernel_cmdline,
  318. const char *initrd_filename,
  319. const char *cpu_model)
  320. {
  321. CPUState *env;
  322. int i;
  323. MemoryRegion *sysmem = get_system_memory();
  324. MemoryRegion *ram = g_new(MemoryRegion, 1);
  325. target_phys_addr_t rma_alloc_size, rma_size;
  326. uint32_t initrd_base;
  327. long kernel_size, initrd_size, fw_size;
  328. long pteg_shift = 17;
  329. char *filename;
  330. spapr = g_malloc0(sizeof(*spapr));
  331. QLIST_INIT(&spapr->phbs);
  332. cpu_ppc_hypercall = emulate_spapr_hypercall;
  333. /* Allocate RMA if necessary */
  334. rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
  335. if (rma_alloc_size == -1) {
  336. hw_error("qemu: Unable to create RMA\n");
  337. exit(1);
  338. }
  339. if (rma_alloc_size && (rma_alloc_size < ram_size)) {
  340. rma_size = rma_alloc_size;
  341. } else {
  342. rma_size = ram_size;
  343. }
  344. /* We place the device tree just below either the top of the RMA,
  345. * or just below 2GB, whichever is lowere, so that it can be
  346. * processed with 32-bit real mode code if necessary */
  347. spapr->fdt_addr = MIN(rma_size, 0x80000000) - FDT_MAX_SIZE;
  348. spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE;
  349. /* init CPUs */
  350. if (cpu_model == NULL) {
  351. cpu_model = kvm_enabled() ? "host" : "POWER7";
  352. }
  353. for (i = 0; i < smp_cpus; i++) {
  354. env = cpu_init(cpu_model);
  355. if (!env) {
  356. fprintf(stderr, "Unable to find PowerPC CPU definition\n");
  357. exit(1);
  358. }
  359. /* Set time-base frequency to 512 MHz */
  360. cpu_ppc_tb_init(env, TIMEBASE_FREQ);
  361. qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
  362. env->hreset_vector = 0x60;
  363. env->hreset_excp_prefix = 0;
  364. env->gpr[3] = env->cpu_index;
  365. }
  366. /* allocate RAM */
  367. spapr->ram_limit = ram_size;
  368. if (spapr->ram_limit > rma_alloc_size) {
  369. ram_addr_t nonrma_base = rma_alloc_size;
  370. ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
  371. memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size);
  372. memory_region_add_subregion(sysmem, nonrma_base, ram);
  373. }
  374. /* allocate hash page table. For now we always make this 16mb,
  375. * later we should probably make it scale to the size of guest
  376. * RAM */
  377. spapr->htab_size = 1ULL << (pteg_shift + 7);
  378. spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);
  379. for (env = first_cpu; env != NULL; env = env->next_cpu) {
  380. env->external_htab = spapr->htab;
  381. env->htab_base = -1;
  382. env->htab_mask = spapr->htab_size - 1;
  383. /* Tell KVM that we're in PAPR mode */
  384. env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
  385. ((pteg_shift + 7) - 18);
  386. env->spr[SPR_HIOR] = 0;
  387. if (kvm_enabled()) {
  388. kvmppc_set_papr(env);
  389. }
  390. }
  391. filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
  392. spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
  393. ram_size - spapr->rtas_addr);
  394. if (spapr->rtas_size < 0) {
  395. hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
  396. exit(1);
  397. }
  398. g_free(filename);
  399. /* Set up Interrupt Controller */
  400. spapr->icp = xics_system_init(XICS_IRQS);
  401. spapr->next_irq = 16;
  402. /* Set up VIO bus */
  403. spapr->vio_bus = spapr_vio_bus_init();
  404. for (i = 0; i < MAX_SERIAL_PORTS; i++) {
  405. if (serial_hds[i]) {
  406. spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i,
  407. serial_hds[i]);
  408. }
  409. }
  410. /* Set up PCI */
  411. spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
  412. SPAPR_PCI_MEM_WIN_ADDR,
  413. SPAPR_PCI_MEM_WIN_SIZE,
  414. SPAPR_PCI_IO_WIN_ADDR);
  415. for (i = 0; i < nb_nics; i++) {
  416. NICInfo *nd = &nd_table[i];
  417. if (!nd->model) {
  418. nd->model = g_strdup("ibmveth");
  419. }
  420. if (strcmp(nd->model, "ibmveth") == 0) {
  421. spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
  422. } else {
  423. pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
  424. }
  425. }
  426. for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
  427. spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
  428. }
  429. if (kernel_filename) {
  430. uint64_t lowaddr = 0;
  431. kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
  432. NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
  433. if (kernel_size < 0) {
  434. kernel_size = load_image_targphys(kernel_filename,
  435. KERNEL_LOAD_ADDR,
  436. ram_size - KERNEL_LOAD_ADDR);
  437. }
  438. if (kernel_size < 0) {
  439. fprintf(stderr, "qemu: could not load kernel '%s'\n",
  440. kernel_filename);
  441. exit(1);
  442. }
  443. /* load initrd */
  444. if (initrd_filename) {
  445. initrd_base = INITRD_LOAD_ADDR;
  446. initrd_size = load_image_targphys(initrd_filename, initrd_base,
  447. ram_size - initrd_base);
  448. if (initrd_size < 0) {
  449. fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
  450. initrd_filename);
  451. exit(1);
  452. }
  453. } else {
  454. initrd_base = 0;
  455. initrd_size = 0;
  456. }
  457. spapr->entry_point = KERNEL_LOAD_ADDR;
  458. } else {
  459. if (rma_size < (MIN_RMA_SLOF << 20)) {
  460. fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
  461. "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
  462. exit(1);
  463. }
  464. filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
  465. fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
  466. if (fw_size < 0) {
  467. hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
  468. exit(1);
  469. }
  470. g_free(filename);
  471. spapr->entry_point = 0x100;
  472. initrd_base = 0;
  473. initrd_size = 0;
  474. /* SLOF will startup the secondary CPUs using RTAS,
  475. rather than expecting a kexec() style entry */
  476. for (env = first_cpu; env != NULL; env = env->next_cpu) {
  477. env->halted = 1;
  478. }
  479. }
  480. /* Prepare the device tree */
  481. spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, rma_size,
  482. initrd_base, initrd_size,
  483. boot_device, kernel_cmdline,
  484. pteg_shift + 7);
  485. assert(spapr->fdt_skel != NULL);
  486. qemu_register_reset(spapr_reset, spapr);
  487. }
  488. static QEMUMachine spapr_machine = {
  489. .name = "pseries",
  490. .desc = "pSeries Logical Partition (PAPR compliant)",
  491. .init = ppc_spapr_init,
  492. .max_cpus = MAX_CPUS,
  493. .no_vga = 1,
  494. .no_parallel = 1,
  495. .use_scsi = 1,
  496. };
  497. static void spapr_machine_init(void)
  498. {
  499. qemu_register_machine(&spapr_machine);
  500. }
  501. machine_init(spapr_machine_init);