pcnet.c 54 KB

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  1. /*
  2. * QEMU AMD PC-Net II (Am79C970A) emulation
  3. *
  4. * Copyright (c) 2004 Antony T Curtis
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. /* This software was written to be compatible with the specification:
  25. * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  26. * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
  27. */
  28. /*
  29. * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
  30. * produced as NCR89C100. See
  31. * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  32. * and
  33. * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
  34. */
  35. #include "qdev.h"
  36. #include "net.h"
  37. #include "qemu-timer.h"
  38. #include "qemu_socket.h"
  39. #include "sysemu.h"
  40. #include "pcnet.h"
  41. //#define PCNET_DEBUG
  42. //#define PCNET_DEBUG_IO
  43. //#define PCNET_DEBUG_BCR
  44. //#define PCNET_DEBUG_CSR
  45. //#define PCNET_DEBUG_RMD
  46. //#define PCNET_DEBUG_TMD
  47. //#define PCNET_DEBUG_MATCH
  48. struct qemu_ether_header {
  49. uint8_t ether_dhost[6];
  50. uint8_t ether_shost[6];
  51. uint16_t ether_type;
  52. };
  53. #define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
  54. #define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
  55. #define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
  56. #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
  57. #define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
  58. #define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
  59. #define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
  60. #define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
  61. #define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
  62. #define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
  63. #define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
  64. #define CSR_DPOLL(S) !!(((S)->csr[4])&0x1000)
  65. #define CSR_SPND(S) !!(((S)->csr[5])&0x0001)
  66. #define CSR_LTINTEN(S) !!(((S)->csr[5])&0x4000)
  67. #define CSR_TOKINTD(S) !!(((S)->csr[5])&0x8000)
  68. #define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
  69. #define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
  70. #define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
  71. #define CSR_DXMTFCS(S) !!(((S)->csr[15])&0x0008)
  72. #define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
  73. #define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
  74. #define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
  75. #define CSR_CRBC(S) ((S)->csr[40])
  76. #define CSR_CRST(S) ((S)->csr[41])
  77. #define CSR_CXBC(S) ((S)->csr[42])
  78. #define CSR_CXST(S) ((S)->csr[43])
  79. #define CSR_NRBC(S) ((S)->csr[44])
  80. #define CSR_NRST(S) ((S)->csr[45])
  81. #define CSR_POLL(S) ((S)->csr[46])
  82. #define CSR_PINT(S) ((S)->csr[47])
  83. #define CSR_RCVRC(S) ((S)->csr[72])
  84. #define CSR_XMTRC(S) ((S)->csr[74])
  85. #define CSR_RCVRL(S) ((S)->csr[76])
  86. #define CSR_XMTRL(S) ((S)->csr[78])
  87. #define CSR_MISSC(S) ((S)->csr[112])
  88. #define CSR_IADR(S) ((S)->csr[ 1] | ((uint32_t)(S)->csr[ 2] << 16))
  89. #define CSR_CRBA(S) ((S)->csr[18] | ((uint32_t)(S)->csr[19] << 16))
  90. #define CSR_CXBA(S) ((S)->csr[20] | ((uint32_t)(S)->csr[21] << 16))
  91. #define CSR_NRBA(S) ((S)->csr[22] | ((uint32_t)(S)->csr[23] << 16))
  92. #define CSR_BADR(S) ((S)->csr[24] | ((uint32_t)(S)->csr[25] << 16))
  93. #define CSR_NRDA(S) ((S)->csr[26] | ((uint32_t)(S)->csr[27] << 16))
  94. #define CSR_CRDA(S) ((S)->csr[28] | ((uint32_t)(S)->csr[29] << 16))
  95. #define CSR_BADX(S) ((S)->csr[30] | ((uint32_t)(S)->csr[31] << 16))
  96. #define CSR_NXDA(S) ((S)->csr[32] | ((uint32_t)(S)->csr[33] << 16))
  97. #define CSR_CXDA(S) ((S)->csr[34] | ((uint32_t)(S)->csr[35] << 16))
  98. #define CSR_NNRD(S) ((S)->csr[36] | ((uint32_t)(S)->csr[37] << 16))
  99. #define CSR_NNXD(S) ((S)->csr[38] | ((uint32_t)(S)->csr[39] << 16))
  100. #define CSR_PXDA(S) ((S)->csr[60] | ((uint32_t)(S)->csr[61] << 16))
  101. #define CSR_NXBA(S) ((S)->csr[64] | ((uint32_t)(S)->csr[65] << 16))
  102. #define PHYSADDR(S,A) \
  103. (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(S)->csr[2])<<16))
  104. struct pcnet_initblk16 {
  105. uint16_t mode;
  106. uint16_t padr[3];
  107. uint16_t ladrf[4];
  108. uint32_t rdra;
  109. uint32_t tdra;
  110. };
  111. struct pcnet_initblk32 {
  112. uint16_t mode;
  113. uint8_t rlen;
  114. uint8_t tlen;
  115. uint16_t padr[3];
  116. uint16_t _res;
  117. uint16_t ladrf[4];
  118. uint32_t rdra;
  119. uint32_t tdra;
  120. };
  121. struct pcnet_TMD {
  122. uint32_t tbadr;
  123. int16_t length;
  124. int16_t status;
  125. uint32_t misc;
  126. uint32_t res;
  127. };
  128. #define TMDL_BCNT_MASK 0x0fff
  129. #define TMDL_BCNT_SH 0
  130. #define TMDL_ONES_MASK 0xf000
  131. #define TMDL_ONES_SH 12
  132. #define TMDS_BPE_MASK 0x0080
  133. #define TMDS_BPE_SH 7
  134. #define TMDS_ENP_MASK 0x0100
  135. #define TMDS_ENP_SH 8
  136. #define TMDS_STP_MASK 0x0200
  137. #define TMDS_STP_SH 9
  138. #define TMDS_DEF_MASK 0x0400
  139. #define TMDS_DEF_SH 10
  140. #define TMDS_ONE_MASK 0x0800
  141. #define TMDS_ONE_SH 11
  142. #define TMDS_LTINT_MASK 0x1000
  143. #define TMDS_LTINT_SH 12
  144. #define TMDS_NOFCS_MASK 0x2000
  145. #define TMDS_NOFCS_SH 13
  146. #define TMDS_ADDFCS_MASK TMDS_NOFCS_MASK
  147. #define TMDS_ADDFCS_SH TMDS_NOFCS_SH
  148. #define TMDS_ERR_MASK 0x4000
  149. #define TMDS_ERR_SH 14
  150. #define TMDS_OWN_MASK 0x8000
  151. #define TMDS_OWN_SH 15
  152. #define TMDM_TRC_MASK 0x0000000f
  153. #define TMDM_TRC_SH 0
  154. #define TMDM_TDR_MASK 0x03ff0000
  155. #define TMDM_TDR_SH 16
  156. #define TMDM_RTRY_MASK 0x04000000
  157. #define TMDM_RTRY_SH 26
  158. #define TMDM_LCAR_MASK 0x08000000
  159. #define TMDM_LCAR_SH 27
  160. #define TMDM_LCOL_MASK 0x10000000
  161. #define TMDM_LCOL_SH 28
  162. #define TMDM_EXDEF_MASK 0x20000000
  163. #define TMDM_EXDEF_SH 29
  164. #define TMDM_UFLO_MASK 0x40000000
  165. #define TMDM_UFLO_SH 30
  166. #define TMDM_BUFF_MASK 0x80000000
  167. #define TMDM_BUFF_SH 31
  168. struct pcnet_RMD {
  169. uint32_t rbadr;
  170. int16_t buf_length;
  171. int16_t status;
  172. uint32_t msg_length;
  173. uint32_t res;
  174. };
  175. #define RMDL_BCNT_MASK 0x0fff
  176. #define RMDL_BCNT_SH 0
  177. #define RMDL_ONES_MASK 0xf000
  178. #define RMDL_ONES_SH 12
  179. #define RMDS_BAM_MASK 0x0010
  180. #define RMDS_BAM_SH 4
  181. #define RMDS_LFAM_MASK 0x0020
  182. #define RMDS_LFAM_SH 5
  183. #define RMDS_PAM_MASK 0x0040
  184. #define RMDS_PAM_SH 6
  185. #define RMDS_BPE_MASK 0x0080
  186. #define RMDS_BPE_SH 7
  187. #define RMDS_ENP_MASK 0x0100
  188. #define RMDS_ENP_SH 8
  189. #define RMDS_STP_MASK 0x0200
  190. #define RMDS_STP_SH 9
  191. #define RMDS_BUFF_MASK 0x0400
  192. #define RMDS_BUFF_SH 10
  193. #define RMDS_CRC_MASK 0x0800
  194. #define RMDS_CRC_SH 11
  195. #define RMDS_OFLO_MASK 0x1000
  196. #define RMDS_OFLO_SH 12
  197. #define RMDS_FRAM_MASK 0x2000
  198. #define RMDS_FRAM_SH 13
  199. #define RMDS_ERR_MASK 0x4000
  200. #define RMDS_ERR_SH 14
  201. #define RMDS_OWN_MASK 0x8000
  202. #define RMDS_OWN_SH 15
  203. #define RMDM_MCNT_MASK 0x00000fff
  204. #define RMDM_MCNT_SH 0
  205. #define RMDM_ZEROS_MASK 0x0000f000
  206. #define RMDM_ZEROS_SH 12
  207. #define RMDM_RPC_MASK 0x00ff0000
  208. #define RMDM_RPC_SH 16
  209. #define RMDM_RCC_MASK 0xff000000
  210. #define RMDM_RCC_SH 24
  211. #define SET_FIELD(regp, name, field, value) \
  212. (*(regp) = (*(regp) & ~(name ## _ ## field ## _MASK)) \
  213. | ((value) << name ## _ ## field ## _SH))
  214. #define GET_FIELD(reg, name, field) \
  215. (((reg) & name ## _ ## field ## _MASK) >> name ## _ ## field ## _SH)
  216. #define PRINT_TMD(T) printf( \
  217. "TMD0 : TBADR=0x%08x\n" \
  218. "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
  219. "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
  220. " BPE=%d, BCNT=%d\n" \
  221. "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
  222. "LCA=%d, RTR=%d,\n" \
  223. " TDR=%d, TRC=%d\n", \
  224. (T)->tbadr, \
  225. GET_FIELD((T)->status, TMDS, OWN), \
  226. GET_FIELD((T)->status, TMDS, ERR), \
  227. GET_FIELD((T)->status, TMDS, NOFCS), \
  228. GET_FIELD((T)->status, TMDS, LTINT), \
  229. GET_FIELD((T)->status, TMDS, ONE), \
  230. GET_FIELD((T)->status, TMDS, DEF), \
  231. GET_FIELD((T)->status, TMDS, STP), \
  232. GET_FIELD((T)->status, TMDS, ENP), \
  233. GET_FIELD((T)->status, TMDS, BPE), \
  234. 4096-GET_FIELD((T)->length, TMDL, BCNT), \
  235. GET_FIELD((T)->misc, TMDM, BUFF), \
  236. GET_FIELD((T)->misc, TMDM, UFLO), \
  237. GET_FIELD((T)->misc, TMDM, EXDEF), \
  238. GET_FIELD((T)->misc, TMDM, LCOL), \
  239. GET_FIELD((T)->misc, TMDM, LCAR), \
  240. GET_FIELD((T)->misc, TMDM, RTRY), \
  241. GET_FIELD((T)->misc, TMDM, TDR), \
  242. GET_FIELD((T)->misc, TMDM, TRC))
  243. #define PRINT_RMD(R) printf( \
  244. "RMD0 : RBADR=0x%08x\n" \
  245. "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
  246. "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
  247. "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
  248. "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
  249. (R)->rbadr, \
  250. GET_FIELD((R)->status, RMDS, OWN), \
  251. GET_FIELD((R)->status, RMDS, ERR), \
  252. GET_FIELD((R)->status, RMDS, FRAM), \
  253. GET_FIELD((R)->status, RMDS, OFLO), \
  254. GET_FIELD((R)->status, RMDS, CRC), \
  255. GET_FIELD((R)->status, RMDS, BUFF), \
  256. GET_FIELD((R)->status, RMDS, STP), \
  257. GET_FIELD((R)->status, RMDS, ENP), \
  258. GET_FIELD((R)->status, RMDS, BPE), \
  259. GET_FIELD((R)->status, RMDS, PAM), \
  260. GET_FIELD((R)->status, RMDS, LFAM), \
  261. GET_FIELD((R)->status, RMDS, BAM), \
  262. GET_FIELD((R)->buf_length, RMDL, ONES), \
  263. 4096-GET_FIELD((R)->buf_length, RMDL, BCNT), \
  264. GET_FIELD((R)->msg_length, RMDM, RCC), \
  265. GET_FIELD((R)->msg_length, RMDM, RPC), \
  266. GET_FIELD((R)->msg_length, RMDM, MCNT), \
  267. GET_FIELD((R)->msg_length, RMDM, ZEROS))
  268. static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
  269. target_phys_addr_t addr)
  270. {
  271. if (!BCR_SSIZE32(s)) {
  272. struct {
  273. uint32_t tbadr;
  274. int16_t length;
  275. int16_t status;
  276. } xda;
  277. s->phys_mem_read(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
  278. tmd->tbadr = le32_to_cpu(xda.tbadr) & 0xffffff;
  279. tmd->length = le16_to_cpu(xda.length);
  280. tmd->status = (le32_to_cpu(xda.tbadr) >> 16) & 0xff00;
  281. tmd->misc = le16_to_cpu(xda.status) << 16;
  282. tmd->res = 0;
  283. } else {
  284. s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, sizeof(*tmd), 0);
  285. le32_to_cpus(&tmd->tbadr);
  286. le16_to_cpus((uint16_t *)&tmd->length);
  287. le16_to_cpus((uint16_t *)&tmd->status);
  288. le32_to_cpus(&tmd->misc);
  289. le32_to_cpus(&tmd->res);
  290. if (BCR_SWSTYLE(s) == 3) {
  291. uint32_t tmp = tmd->tbadr;
  292. tmd->tbadr = tmd->misc;
  293. tmd->misc = tmp;
  294. }
  295. }
  296. }
  297. static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
  298. target_phys_addr_t addr)
  299. {
  300. if (!BCR_SSIZE32(s)) {
  301. struct {
  302. uint32_t tbadr;
  303. int16_t length;
  304. int16_t status;
  305. } xda;
  306. xda.tbadr = cpu_to_le32((tmd->tbadr & 0xffffff) |
  307. ((tmd->status & 0xff00) << 16));
  308. xda.length = cpu_to_le16(tmd->length);
  309. xda.status = cpu_to_le16(tmd->misc >> 16);
  310. s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
  311. } else {
  312. struct {
  313. uint32_t tbadr;
  314. int16_t length;
  315. int16_t status;
  316. uint32_t misc;
  317. uint32_t res;
  318. } xda;
  319. xda.tbadr = cpu_to_le32(tmd->tbadr);
  320. xda.length = cpu_to_le16(tmd->length);
  321. xda.status = cpu_to_le16(tmd->status);
  322. xda.misc = cpu_to_le32(tmd->misc);
  323. xda.res = cpu_to_le32(tmd->res);
  324. if (BCR_SWSTYLE(s) == 3) {
  325. uint32_t tmp = xda.tbadr;
  326. xda.tbadr = xda.misc;
  327. xda.misc = tmp;
  328. }
  329. s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
  330. }
  331. }
  332. static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
  333. target_phys_addr_t addr)
  334. {
  335. if (!BCR_SSIZE32(s)) {
  336. struct {
  337. uint32_t rbadr;
  338. int16_t buf_length;
  339. int16_t msg_length;
  340. } rda;
  341. s->phys_mem_read(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
  342. rmd->rbadr = le32_to_cpu(rda.rbadr) & 0xffffff;
  343. rmd->buf_length = le16_to_cpu(rda.buf_length);
  344. rmd->status = (le32_to_cpu(rda.rbadr) >> 16) & 0xff00;
  345. rmd->msg_length = le16_to_cpu(rda.msg_length);
  346. rmd->res = 0;
  347. } else {
  348. s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, sizeof(*rmd), 0);
  349. le32_to_cpus(&rmd->rbadr);
  350. le16_to_cpus((uint16_t *)&rmd->buf_length);
  351. le16_to_cpus((uint16_t *)&rmd->status);
  352. le32_to_cpus(&rmd->msg_length);
  353. le32_to_cpus(&rmd->res);
  354. if (BCR_SWSTYLE(s) == 3) {
  355. uint32_t tmp = rmd->rbadr;
  356. rmd->rbadr = rmd->msg_length;
  357. rmd->msg_length = tmp;
  358. }
  359. }
  360. }
  361. static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
  362. target_phys_addr_t addr)
  363. {
  364. if (!BCR_SSIZE32(s)) {
  365. struct {
  366. uint32_t rbadr;
  367. int16_t buf_length;
  368. int16_t msg_length;
  369. } rda;
  370. rda.rbadr = cpu_to_le32((rmd->rbadr & 0xffffff) |
  371. ((rmd->status & 0xff00) << 16));
  372. rda.buf_length = cpu_to_le16(rmd->buf_length);
  373. rda.msg_length = cpu_to_le16(rmd->msg_length);
  374. s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
  375. } else {
  376. struct {
  377. uint32_t rbadr;
  378. int16_t buf_length;
  379. int16_t status;
  380. uint32_t msg_length;
  381. uint32_t res;
  382. } rda;
  383. rda.rbadr = cpu_to_le32(rmd->rbadr);
  384. rda.buf_length = cpu_to_le16(rmd->buf_length);
  385. rda.status = cpu_to_le16(rmd->status);
  386. rda.msg_length = cpu_to_le32(rmd->msg_length);
  387. rda.res = cpu_to_le32(rmd->res);
  388. if (BCR_SWSTYLE(s) == 3) {
  389. uint32_t tmp = rda.rbadr;
  390. rda.rbadr = rda.msg_length;
  391. rda.msg_length = tmp;
  392. }
  393. s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
  394. }
  395. }
  396. #define TMDLOAD(TMD,ADDR) pcnet_tmd_load(s,TMD,ADDR)
  397. #define TMDSTORE(TMD,ADDR) pcnet_tmd_store(s,TMD,ADDR)
  398. #define RMDLOAD(RMD,ADDR) pcnet_rmd_load(s,RMD,ADDR)
  399. #define RMDSTORE(RMD,ADDR) pcnet_rmd_store(s,RMD,ADDR)
  400. #if 1
  401. #define CHECK_RMD(ADDR,RES) do { \
  402. struct pcnet_RMD rmd; \
  403. RMDLOAD(&rmd,(ADDR)); \
  404. (RES) |= (GET_FIELD(rmd.buf_length, RMDL, ONES) != 15) \
  405. || (GET_FIELD(rmd.msg_length, RMDM, ZEROS) != 0); \
  406. } while (0)
  407. #define CHECK_TMD(ADDR,RES) do { \
  408. struct pcnet_TMD tmd; \
  409. TMDLOAD(&tmd,(ADDR)); \
  410. (RES) |= (GET_FIELD(tmd.length, TMDL, ONES) != 15); \
  411. } while (0)
  412. #else
  413. #define CHECK_RMD(ADDR,RES) do { \
  414. switch (BCR_SWSTYLE(s)) { \
  415. case 0x00: \
  416. do { \
  417. uint16_t rda[4]; \
  418. s->phys_mem_read(s->dma_opaque, (ADDR), \
  419. (void *)&rda[0], sizeof(rda), 0); \
  420. (RES) |= (rda[2] & 0xf000)!=0xf000; \
  421. (RES) |= (rda[3] & 0xf000)!=0x0000; \
  422. } while (0); \
  423. break; \
  424. case 0x01: \
  425. case 0x02: \
  426. do { \
  427. uint32_t rda[4]; \
  428. s->phys_mem_read(s->dma_opaque, (ADDR), \
  429. (void *)&rda[0], sizeof(rda), 0); \
  430. (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
  431. (RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
  432. } while (0); \
  433. break; \
  434. case 0x03: \
  435. do { \
  436. uint32_t rda[4]; \
  437. s->phys_mem_read(s->dma_opaque, (ADDR), \
  438. (void *)&rda[0], sizeof(rda), 0); \
  439. (RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
  440. (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
  441. } while (0); \
  442. break; \
  443. } \
  444. } while (0)
  445. #define CHECK_TMD(ADDR,RES) do { \
  446. switch (BCR_SWSTYLE(s)) { \
  447. case 0x00: \
  448. do { \
  449. uint16_t xda[4]; \
  450. s->phys_mem_read(s->dma_opaque, (ADDR), \
  451. (void *)&xda[0], sizeof(xda), 0); \
  452. (RES) |= (xda[2] & 0xf000)!=0xf000; \
  453. } while (0); \
  454. break; \
  455. case 0x01: \
  456. case 0x02: \
  457. case 0x03: \
  458. do { \
  459. uint32_t xda[4]; \
  460. s->phys_mem_read(s->dma_opaque, (ADDR), \
  461. (void *)&xda[0], sizeof(xda), 0); \
  462. (RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
  463. } while (0); \
  464. break; \
  465. } \
  466. } while (0)
  467. #endif
  468. #define PRINT_PKTHDR(BUF) do { \
  469. struct qemu_ether_header *hdr = (void *)(BUF); \
  470. printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
  471. "shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
  472. "type=0x%04x\n", \
  473. hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
  474. hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
  475. hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
  476. hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
  477. be16_to_cpu(hdr->ether_type)); \
  478. } while (0)
  479. #define MULTICAST_FILTER_LEN 8
  480. static inline uint32_t lnc_mchash(const uint8_t *ether_addr)
  481. {
  482. #define LNC_POLYNOMIAL 0xEDB88320UL
  483. uint32_t crc = 0xFFFFFFFF;
  484. int idx, bit;
  485. uint8_t data;
  486. for (idx = 0; idx < 6; idx++) {
  487. for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
  488. crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
  489. data >>= 1;
  490. }
  491. }
  492. return crc;
  493. #undef LNC_POLYNOMIAL
  494. }
  495. #define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
  496. /* generated using the AUTODIN II polynomial
  497. * x^32 + x^26 + x^23 + x^22 + x^16 +
  498. * x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
  499. */
  500. static const uint32_t crctab[256] = {
  501. 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
  502. 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
  503. 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
  504. 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
  505. 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
  506. 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
  507. 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
  508. 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
  509. 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
  510. 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
  511. 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
  512. 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
  513. 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
  514. 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
  515. 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
  516. 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
  517. 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
  518. 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
  519. 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
  520. 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
  521. 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
  522. 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
  523. 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
  524. 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
  525. 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
  526. 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
  527. 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
  528. 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
  529. 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
  530. 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
  531. 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
  532. 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
  533. 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
  534. 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
  535. 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
  536. 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
  537. 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
  538. 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
  539. 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
  540. 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
  541. 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
  542. 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
  543. 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
  544. 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
  545. 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
  546. 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
  547. 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
  548. 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
  549. 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
  550. 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
  551. 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
  552. 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
  553. 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
  554. 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
  555. 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
  556. 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
  557. 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
  558. 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
  559. 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
  560. 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
  561. 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
  562. 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
  563. 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
  564. 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
  565. };
  566. static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
  567. {
  568. struct qemu_ether_header *hdr = (void *)buf;
  569. uint8_t padr[6] = {
  570. s->csr[12] & 0xff, s->csr[12] >> 8,
  571. s->csr[13] & 0xff, s->csr[13] >> 8,
  572. s->csr[14] & 0xff, s->csr[14] >> 8
  573. };
  574. int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);
  575. #ifdef PCNET_DEBUG_MATCH
  576. printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
  577. "padr=%02x:%02x:%02x:%02x:%02x:%02x\n",
  578. hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
  579. hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
  580. padr[0],padr[1],padr[2],padr[3],padr[4],padr[5]);
  581. printf("padr_match result=%d\n", result);
  582. #endif
  583. return result;
  584. }
  585. static inline int padr_bcast(PCNetState *s, const uint8_t *buf, int size)
  586. {
  587. static const uint8_t BCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  588. struct qemu_ether_header *hdr = (void *)buf;
  589. int result = !CSR_DRCVBC(s) && !memcmp(hdr->ether_dhost, BCAST, 6);
  590. #ifdef PCNET_DEBUG_MATCH
  591. printf("padr_bcast result=%d\n", result);
  592. #endif
  593. return result;
  594. }
  595. static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
  596. {
  597. struct qemu_ether_header *hdr = (void *)buf;
  598. if ((*(hdr->ether_dhost)&0x01) &&
  599. ((uint64_t *)&s->csr[8])[0] != 0LL) {
  600. uint8_t ladr[8] = {
  601. s->csr[8] & 0xff, s->csr[8] >> 8,
  602. s->csr[9] & 0xff, s->csr[9] >> 8,
  603. s->csr[10] & 0xff, s->csr[10] >> 8,
  604. s->csr[11] & 0xff, s->csr[11] >> 8
  605. };
  606. int index = lnc_mchash(hdr->ether_dhost) >> 26;
  607. return !!(ladr[index >> 3] & (1 << (index & 7)));
  608. }
  609. return 0;
  610. }
  611. static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
  612. {
  613. while (idx < 1) idx += CSR_RCVRL(s);
  614. return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
  615. }
  616. static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
  617. {
  618. int64_t next_time = current_time +
  619. muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
  620. get_ticks_per_sec(), 33000000L);
  621. if (next_time <= current_time)
  622. next_time = current_time + 1;
  623. return next_time;
  624. }
  625. static void pcnet_poll(PCNetState *s);
  626. static void pcnet_poll_timer(void *opaque);
  627. static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap);
  628. static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value);
  629. static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val);
  630. static void pcnet_s_reset(PCNetState *s)
  631. {
  632. #ifdef PCNET_DEBUG
  633. printf("pcnet_s_reset\n");
  634. #endif
  635. s->lnkst = 0x40;
  636. s->rdra = 0;
  637. s->tdra = 0;
  638. s->rap = 0;
  639. s->bcr[BCR_BSBC] &= ~0x0080;
  640. s->csr[0] = 0x0004;
  641. s->csr[3] = 0x0000;
  642. s->csr[4] = 0x0115;
  643. s->csr[5] = 0x0000;
  644. s->csr[6] = 0x0000;
  645. s->csr[8] = 0;
  646. s->csr[9] = 0;
  647. s->csr[10] = 0;
  648. s->csr[11] = 0;
  649. s->csr[12] = le16_to_cpu(((uint16_t *)&s->prom[0])[0]);
  650. s->csr[13] = le16_to_cpu(((uint16_t *)&s->prom[0])[1]);
  651. s->csr[14] = le16_to_cpu(((uint16_t *)&s->prom[0])[2]);
  652. s->csr[15] &= 0x21c4;
  653. s->csr[72] = 1;
  654. s->csr[74] = 1;
  655. s->csr[76] = 1;
  656. s->csr[78] = 1;
  657. s->csr[80] = 0x1410;
  658. s->csr[88] = 0x1003;
  659. s->csr[89] = 0x0262;
  660. s->csr[94] = 0x0000;
  661. s->csr[100] = 0x0200;
  662. s->csr[103] = 0x0105;
  663. s->csr[103] = 0x0105;
  664. s->csr[112] = 0x0000;
  665. s->csr[114] = 0x0000;
  666. s->csr[122] = 0x0000;
  667. s->csr[124] = 0x0000;
  668. s->tx_busy = 0;
  669. }
  670. static void pcnet_update_irq(PCNetState *s)
  671. {
  672. int isr = 0;
  673. s->csr[0] &= ~0x0080;
  674. #if 1
  675. if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
  676. (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
  677. (((s->csr[5]>>1) & s->csr[5]) & 0x0048))
  678. #else
  679. if ((!(s->csr[3] & 0x4000) && !!(s->csr[0] & 0x4000)) /* BABL */ ||
  680. (!(s->csr[3] & 0x1000) && !!(s->csr[0] & 0x1000)) /* MISS */ ||
  681. (!(s->csr[3] & 0x0100) && !!(s->csr[0] & 0x0100)) /* IDON */ ||
  682. (!(s->csr[3] & 0x0200) && !!(s->csr[0] & 0x0200)) /* TINT */ ||
  683. (!(s->csr[3] & 0x0400) && !!(s->csr[0] & 0x0400)) /* RINT */ ||
  684. (!(s->csr[3] & 0x0800) && !!(s->csr[0] & 0x0800)) /* MERR */ ||
  685. (!(s->csr[4] & 0x0001) && !!(s->csr[4] & 0x0002)) /* JAB */ ||
  686. (!(s->csr[4] & 0x0004) && !!(s->csr[4] & 0x0008)) /* TXSTRT */ ||
  687. (!(s->csr[4] & 0x0010) && !!(s->csr[4] & 0x0020)) /* RCVO */ ||
  688. (!(s->csr[4] & 0x0100) && !!(s->csr[4] & 0x0200)) /* MFCO */ ||
  689. (!!(s->csr[5] & 0x0040) && !!(s->csr[5] & 0x0080)) /* EXDINT */ ||
  690. (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
  691. #endif
  692. {
  693. isr = CSR_INEA(s);
  694. s->csr[0] |= 0x0080;
  695. }
  696. if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
  697. s->csr[4] &= ~0x0080;
  698. s->csr[4] |= 0x0040;
  699. s->csr[0] |= 0x0080;
  700. isr = 1;
  701. #ifdef PCNET_DEBUG
  702. printf("pcnet user int\n");
  703. #endif
  704. }
  705. #if 1
  706. if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
  707. #else
  708. if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
  709. (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
  710. #endif
  711. {
  712. isr = 1;
  713. s->csr[0] |= 0x0080;
  714. }
  715. if (isr != s->isr) {
  716. #ifdef PCNET_DEBUG
  717. printf("pcnet: INTA=%d\n", isr);
  718. #endif
  719. }
  720. qemu_set_irq(s->irq, isr);
  721. s->isr = isr;
  722. }
  723. static void pcnet_init(PCNetState *s)
  724. {
  725. int rlen, tlen;
  726. uint16_t padr[3], ladrf[4], mode;
  727. uint32_t rdra, tdra;
  728. #ifdef PCNET_DEBUG
  729. printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
  730. #endif
  731. if (BCR_SSIZE32(s)) {
  732. struct pcnet_initblk32 initblk;
  733. s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
  734. (uint8_t *)&initblk, sizeof(initblk), 0);
  735. mode = le16_to_cpu(initblk.mode);
  736. rlen = initblk.rlen >> 4;
  737. tlen = initblk.tlen >> 4;
  738. ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
  739. ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
  740. ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
  741. ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
  742. padr[0] = le16_to_cpu(initblk.padr[0]);
  743. padr[1] = le16_to_cpu(initblk.padr[1]);
  744. padr[2] = le16_to_cpu(initblk.padr[2]);
  745. rdra = le32_to_cpu(initblk.rdra);
  746. tdra = le32_to_cpu(initblk.tdra);
  747. } else {
  748. struct pcnet_initblk16 initblk;
  749. s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
  750. (uint8_t *)&initblk, sizeof(initblk), 0);
  751. mode = le16_to_cpu(initblk.mode);
  752. ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
  753. ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
  754. ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
  755. ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
  756. padr[0] = le16_to_cpu(initblk.padr[0]);
  757. padr[1] = le16_to_cpu(initblk.padr[1]);
  758. padr[2] = le16_to_cpu(initblk.padr[2]);
  759. rdra = le32_to_cpu(initblk.rdra);
  760. tdra = le32_to_cpu(initblk.tdra);
  761. rlen = rdra >> 29;
  762. tlen = tdra >> 29;
  763. rdra &= 0x00ffffff;
  764. tdra &= 0x00ffffff;
  765. }
  766. #if defined(PCNET_DEBUG)
  767. printf("rlen=%d tlen=%d\n", rlen, tlen);
  768. #endif
  769. CSR_RCVRL(s) = (rlen < 9) ? (1 << rlen) : 512;
  770. CSR_XMTRL(s) = (tlen < 9) ? (1 << tlen) : 512;
  771. s->csr[ 6] = (tlen << 12) | (rlen << 8);
  772. s->csr[15] = mode;
  773. s->csr[ 8] = ladrf[0];
  774. s->csr[ 9] = ladrf[1];
  775. s->csr[10] = ladrf[2];
  776. s->csr[11] = ladrf[3];
  777. s->csr[12] = padr[0];
  778. s->csr[13] = padr[1];
  779. s->csr[14] = padr[2];
  780. s->rdra = PHYSADDR(s, rdra);
  781. s->tdra = PHYSADDR(s, tdra);
  782. CSR_RCVRC(s) = CSR_RCVRL(s);
  783. CSR_XMTRC(s) = CSR_XMTRL(s);
  784. #ifdef PCNET_DEBUG
  785. printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n",
  786. BCR_SSIZE32(s),
  787. s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
  788. #endif
  789. s->csr[0] |= 0x0101;
  790. s->csr[0] &= ~0x0004; /* clear STOP bit */
  791. }
  792. static void pcnet_start(PCNetState *s)
  793. {
  794. #ifdef PCNET_DEBUG
  795. printf("pcnet_start\n");
  796. #endif
  797. if (!CSR_DTX(s))
  798. s->csr[0] |= 0x0010; /* set TXON */
  799. if (!CSR_DRX(s))
  800. s->csr[0] |= 0x0020; /* set RXON */
  801. s->csr[0] &= ~0x0004; /* clear STOP bit */
  802. s->csr[0] |= 0x0002;
  803. pcnet_poll_timer(s);
  804. }
  805. static void pcnet_stop(PCNetState *s)
  806. {
  807. #ifdef PCNET_DEBUG
  808. printf("pcnet_stop\n");
  809. #endif
  810. s->csr[0] &= ~0x7feb;
  811. s->csr[0] |= 0x0014;
  812. s->csr[4] &= ~0x02c2;
  813. s->csr[5] &= ~0x0011;
  814. pcnet_poll_timer(s);
  815. }
  816. static void pcnet_rdte_poll(PCNetState *s)
  817. {
  818. s->csr[28] = s->csr[29] = 0;
  819. if (s->rdra) {
  820. int bad = 0;
  821. #if 1
  822. target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
  823. target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
  824. target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
  825. #else
  826. target_phys_addr_t crda = s->rdra +
  827. (CSR_RCVRL(s) - CSR_RCVRC(s)) *
  828. (BCR_SWSTYLE(s) ? 16 : 8 );
  829. int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
  830. target_phys_addr_t nrda = s->rdra +
  831. (CSR_RCVRL(s) - nrdc) *
  832. (BCR_SWSTYLE(s) ? 16 : 8 );
  833. int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
  834. target_phys_addr_t nnrd = s->rdra +
  835. (CSR_RCVRL(s) - nnrc) *
  836. (BCR_SWSTYLE(s) ? 16 : 8 );
  837. #endif
  838. CHECK_RMD(crda, bad);
  839. if (!bad) {
  840. CHECK_RMD(nrda, bad);
  841. if (bad || (nrda == crda)) nrda = 0;
  842. CHECK_RMD(nnrd, bad);
  843. if (bad || (nnrd == crda)) nnrd = 0;
  844. s->csr[28] = crda & 0xffff;
  845. s->csr[29] = crda >> 16;
  846. s->csr[26] = nrda & 0xffff;
  847. s->csr[27] = nrda >> 16;
  848. s->csr[36] = nnrd & 0xffff;
  849. s->csr[37] = nnrd >> 16;
  850. #ifdef PCNET_DEBUG
  851. if (bad) {
  852. printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
  853. crda);
  854. }
  855. } else {
  856. printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n",
  857. crda);
  858. #endif
  859. }
  860. }
  861. if (CSR_CRDA(s)) {
  862. struct pcnet_RMD rmd;
  863. RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
  864. CSR_CRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
  865. CSR_CRST(s) = rmd.status;
  866. #ifdef PCNET_DEBUG_RMD_X
  867. printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMDL=0x%04x RMDS=0x%04x RMDM=0x%08x\n",
  868. PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
  869. rmd.buf_length, rmd.status, rmd.msg_length);
  870. PRINT_RMD(&rmd);
  871. #endif
  872. } else {
  873. CSR_CRBC(s) = CSR_CRST(s) = 0;
  874. }
  875. if (CSR_NRDA(s)) {
  876. struct pcnet_RMD rmd;
  877. RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
  878. CSR_NRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
  879. CSR_NRST(s) = rmd.status;
  880. } else {
  881. CSR_NRBC(s) = CSR_NRST(s) = 0;
  882. }
  883. }
  884. static int pcnet_tdte_poll(PCNetState *s)
  885. {
  886. s->csr[34] = s->csr[35] = 0;
  887. if (s->tdra) {
  888. target_phys_addr_t cxda = s->tdra +
  889. (CSR_XMTRL(s) - CSR_XMTRC(s)) *
  890. (BCR_SWSTYLE(s) ? 16 : 8);
  891. int bad = 0;
  892. CHECK_TMD(cxda, bad);
  893. if (!bad) {
  894. if (CSR_CXDA(s) != cxda) {
  895. s->csr[60] = s->csr[34];
  896. s->csr[61] = s->csr[35];
  897. s->csr[62] = CSR_CXBC(s);
  898. s->csr[63] = CSR_CXST(s);
  899. }
  900. s->csr[34] = cxda & 0xffff;
  901. s->csr[35] = cxda >> 16;
  902. #ifdef PCNET_DEBUG_X
  903. printf("pcnet: BAD TMD XDA=0x%08x\n", cxda);
  904. #endif
  905. }
  906. }
  907. if (CSR_CXDA(s)) {
  908. struct pcnet_TMD tmd;
  909. TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
  910. CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
  911. CSR_CXST(s) = tmd.status;
  912. } else {
  913. CSR_CXBC(s) = CSR_CXST(s) = 0;
  914. }
  915. return !!(CSR_CXST(s) & 0x8000);
  916. }
  917. int pcnet_can_receive(VLANClientState *nc)
  918. {
  919. PCNetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
  920. if (CSR_STOP(s) || CSR_SPND(s))
  921. return 0;
  922. return sizeof(s->buffer)-16;
  923. }
  924. #define MIN_BUF_SIZE 60
  925. ssize_t pcnet_receive(VLANClientState *nc, const uint8_t *buf, size_t size_)
  926. {
  927. PCNetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
  928. int is_padr = 0, is_bcast = 0, is_ladr = 0;
  929. uint8_t buf1[60];
  930. int remaining;
  931. int crc_err = 0;
  932. int size = size_;
  933. if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size ||
  934. (CSR_LOOP(s) && !s->looptest)) {
  935. return -1;
  936. }
  937. #ifdef PCNET_DEBUG
  938. printf("pcnet_receive size=%d\n", size);
  939. #endif
  940. /* if too small buffer, then expand it */
  941. if (size < MIN_BUF_SIZE) {
  942. memcpy(buf1, buf, size);
  943. memset(buf1 + size, 0, MIN_BUF_SIZE - size);
  944. buf = buf1;
  945. size = MIN_BUF_SIZE;
  946. }
  947. if (CSR_PROM(s)
  948. || (is_padr=padr_match(s, buf, size))
  949. || (is_bcast=padr_bcast(s, buf, size))
  950. || (is_ladr=ladr_match(s, buf, size))) {
  951. pcnet_rdte_poll(s);
  952. if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
  953. struct pcnet_RMD rmd;
  954. int rcvrc = CSR_RCVRC(s)-1,i;
  955. target_phys_addr_t nrda;
  956. for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
  957. if (rcvrc <= 1)
  958. rcvrc = CSR_RCVRL(s);
  959. nrda = s->rdra +
  960. (CSR_RCVRL(s) - rcvrc) *
  961. (BCR_SWSTYLE(s) ? 16 : 8 );
  962. RMDLOAD(&rmd, nrda);
  963. if (GET_FIELD(rmd.status, RMDS, OWN)) {
  964. #ifdef PCNET_DEBUG_RMD
  965. printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
  966. rcvrc, CSR_RCVRC(s));
  967. #endif
  968. CSR_RCVRC(s) = rcvrc;
  969. pcnet_rdte_poll(s);
  970. break;
  971. }
  972. }
  973. }
  974. if (!(CSR_CRST(s) & 0x8000)) {
  975. #ifdef PCNET_DEBUG_RMD
  976. printf("pcnet - no buffer: RCVRC=%d\n", CSR_RCVRC(s));
  977. #endif
  978. s->csr[0] |= 0x1000; /* Set MISS flag */
  979. CSR_MISSC(s)++;
  980. } else {
  981. uint8_t *src = s->buffer;
  982. target_phys_addr_t crda = CSR_CRDA(s);
  983. struct pcnet_RMD rmd;
  984. int pktcount = 0;
  985. if (!s->looptest) {
  986. memcpy(src, buf, size);
  987. /* no need to compute the CRC */
  988. src[size] = 0;
  989. src[size + 1] = 0;
  990. src[size + 2] = 0;
  991. src[size + 3] = 0;
  992. size += 4;
  993. } else if (s->looptest == PCNET_LOOPTEST_CRC ||
  994. !CSR_DXMTFCS(s) || size < MIN_BUF_SIZE+4) {
  995. uint32_t fcs = ~0;
  996. uint8_t *p = src;
  997. while (p != &src[size])
  998. CRC(fcs, *p++);
  999. *(uint32_t *)p = htonl(fcs);
  1000. size += 4;
  1001. } else {
  1002. uint32_t fcs = ~0;
  1003. uint8_t *p = src;
  1004. while (p != &src[size-4])
  1005. CRC(fcs, *p++);
  1006. crc_err = (*(uint32_t *)p != htonl(fcs));
  1007. }
  1008. #ifdef PCNET_DEBUG_MATCH
  1009. PRINT_PKTHDR(buf);
  1010. #endif
  1011. RMDLOAD(&rmd, PHYSADDR(s,crda));
  1012. /*if (!CSR_LAPPEN(s))*/
  1013. SET_FIELD(&rmd.status, RMDS, STP, 1);
  1014. #define PCNET_RECV_STORE() do { \
  1015. int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
  1016. target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
  1017. s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
  1018. src += count; remaining -= count; \
  1019. SET_FIELD(&rmd.status, RMDS, OWN, 0); \
  1020. RMDSTORE(&rmd, PHYSADDR(s,crda)); \
  1021. pktcount++; \
  1022. } while (0)
  1023. remaining = size;
  1024. PCNET_RECV_STORE();
  1025. if ((remaining > 0) && CSR_NRDA(s)) {
  1026. target_phys_addr_t nrda = CSR_NRDA(s);
  1027. #ifdef PCNET_DEBUG_RMD
  1028. PRINT_RMD(&rmd);
  1029. #endif
  1030. RMDLOAD(&rmd, PHYSADDR(s,nrda));
  1031. if (GET_FIELD(rmd.status, RMDS, OWN)) {
  1032. crda = nrda;
  1033. PCNET_RECV_STORE();
  1034. #ifdef PCNET_DEBUG_RMD
  1035. PRINT_RMD(&rmd);
  1036. #endif
  1037. if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
  1038. RMDLOAD(&rmd, PHYSADDR(s,nrda));
  1039. if (GET_FIELD(rmd.status, RMDS, OWN)) {
  1040. crda = nrda;
  1041. PCNET_RECV_STORE();
  1042. }
  1043. }
  1044. }
  1045. }
  1046. #undef PCNET_RECV_STORE
  1047. RMDLOAD(&rmd, PHYSADDR(s,crda));
  1048. if (remaining == 0) {
  1049. SET_FIELD(&rmd.msg_length, RMDM, MCNT, size);
  1050. SET_FIELD(&rmd.status, RMDS, ENP, 1);
  1051. SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
  1052. SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
  1053. SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
  1054. if (crc_err) {
  1055. SET_FIELD(&rmd.status, RMDS, CRC, 1);
  1056. SET_FIELD(&rmd.status, RMDS, ERR, 1);
  1057. }
  1058. } else {
  1059. SET_FIELD(&rmd.status, RMDS, OFLO, 1);
  1060. SET_FIELD(&rmd.status, RMDS, BUFF, 1);
  1061. SET_FIELD(&rmd.status, RMDS, ERR, 1);
  1062. }
  1063. RMDSTORE(&rmd, PHYSADDR(s,crda));
  1064. s->csr[0] |= 0x0400;
  1065. #ifdef PCNET_DEBUG
  1066. printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
  1067. CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
  1068. #endif
  1069. #ifdef PCNET_DEBUG_RMD
  1070. PRINT_RMD(&rmd);
  1071. #endif
  1072. while (pktcount--) {
  1073. if (CSR_RCVRC(s) <= 1)
  1074. CSR_RCVRC(s) = CSR_RCVRL(s);
  1075. else
  1076. CSR_RCVRC(s)--;
  1077. }
  1078. pcnet_rdte_poll(s);
  1079. }
  1080. }
  1081. pcnet_poll(s);
  1082. pcnet_update_irq(s);
  1083. return size_;
  1084. }
  1085. void pcnet_set_link_status(VLANClientState *nc)
  1086. {
  1087. PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
  1088. d->lnkst = nc->link_down ? 0 : 0x40;
  1089. }
  1090. static void pcnet_transmit(PCNetState *s)
  1091. {
  1092. target_phys_addr_t xmit_cxda = 0;
  1093. int count = CSR_XMTRL(s)-1;
  1094. int add_crc = 0;
  1095. s->xmit_pos = -1;
  1096. if (!CSR_TXON(s)) {
  1097. s->csr[0] &= ~0x0008;
  1098. return;
  1099. }
  1100. s->tx_busy = 1;
  1101. txagain:
  1102. if (pcnet_tdte_poll(s)) {
  1103. struct pcnet_TMD tmd;
  1104. TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
  1105. #ifdef PCNET_DEBUG_TMD
  1106. printf(" TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
  1107. PRINT_TMD(&tmd);
  1108. #endif
  1109. if (GET_FIELD(tmd.status, TMDS, STP)) {
  1110. s->xmit_pos = 0;
  1111. xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
  1112. if (BCR_SWSTYLE(s) != 1)
  1113. add_crc = GET_FIELD(tmd.status, TMDS, ADDFCS);
  1114. }
  1115. if (!GET_FIELD(tmd.status, TMDS, ENP)) {
  1116. int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
  1117. s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
  1118. s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
  1119. s->xmit_pos += bcnt;
  1120. } else if (s->xmit_pos >= 0) {
  1121. int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
  1122. s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
  1123. s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
  1124. s->xmit_pos += bcnt;
  1125. #ifdef PCNET_DEBUG
  1126. printf("pcnet_transmit size=%d\n", s->xmit_pos);
  1127. #endif
  1128. if (CSR_LOOP(s)) {
  1129. if (BCR_SWSTYLE(s) == 1)
  1130. add_crc = !GET_FIELD(tmd.status, TMDS, NOFCS);
  1131. s->looptest = add_crc ? PCNET_LOOPTEST_CRC : PCNET_LOOPTEST_NOCRC;
  1132. pcnet_receive(&s->nic->nc, s->buffer, s->xmit_pos);
  1133. s->looptest = 0;
  1134. } else
  1135. if (s->nic)
  1136. qemu_send_packet(&s->nic->nc, s->buffer, s->xmit_pos);
  1137. s->csr[0] &= ~0x0008; /* clear TDMD */
  1138. s->csr[4] |= 0x0004; /* set TXSTRT */
  1139. s->xmit_pos = -1;
  1140. }
  1141. SET_FIELD(&tmd.status, TMDS, OWN, 0);
  1142. TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
  1143. if (!CSR_TOKINTD(s) || (CSR_LTINTEN(s) && GET_FIELD(tmd.status, TMDS, LTINT)))
  1144. s->csr[0] |= 0x0200; /* set TINT */
  1145. if (CSR_XMTRC(s)<=1)
  1146. CSR_XMTRC(s) = CSR_XMTRL(s);
  1147. else
  1148. CSR_XMTRC(s)--;
  1149. if (count--)
  1150. goto txagain;
  1151. } else
  1152. if (s->xmit_pos >= 0) {
  1153. struct pcnet_TMD tmd;
  1154. TMDLOAD(&tmd, xmit_cxda);
  1155. SET_FIELD(&tmd.misc, TMDM, BUFF, 1);
  1156. SET_FIELD(&tmd.misc, TMDM, UFLO, 1);
  1157. SET_FIELD(&tmd.status, TMDS, ERR, 1);
  1158. SET_FIELD(&tmd.status, TMDS, OWN, 0);
  1159. TMDSTORE(&tmd, xmit_cxda);
  1160. s->csr[0] |= 0x0200; /* set TINT */
  1161. if (!CSR_DXSUFLO(s)) {
  1162. s->csr[0] &= ~0x0010;
  1163. } else
  1164. if (count--)
  1165. goto txagain;
  1166. }
  1167. s->tx_busy = 0;
  1168. }
  1169. static void pcnet_poll(PCNetState *s)
  1170. {
  1171. if (CSR_RXON(s)) {
  1172. pcnet_rdte_poll(s);
  1173. }
  1174. if (CSR_TDMD(s) ||
  1175. (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
  1176. {
  1177. /* prevent recursion */
  1178. if (s->tx_busy)
  1179. return;
  1180. pcnet_transmit(s);
  1181. }
  1182. }
  1183. static void pcnet_poll_timer(void *opaque)
  1184. {
  1185. PCNetState *s = opaque;
  1186. qemu_del_timer(s->poll_timer);
  1187. if (CSR_TDMD(s)) {
  1188. pcnet_transmit(s);
  1189. }
  1190. pcnet_update_irq(s);
  1191. if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
  1192. uint64_t now = qemu_get_clock_ns(vm_clock) * 33;
  1193. if (!s->timer || !now)
  1194. s->timer = now;
  1195. else {
  1196. uint64_t t = now - s->timer + CSR_POLL(s);
  1197. if (t > 0xffffLL) {
  1198. pcnet_poll(s);
  1199. CSR_POLL(s) = CSR_PINT(s);
  1200. } else
  1201. CSR_POLL(s) = t;
  1202. }
  1203. qemu_mod_timer(s->poll_timer,
  1204. pcnet_get_next_poll_time(s,qemu_get_clock_ns(vm_clock)));
  1205. }
  1206. }
  1207. static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value)
  1208. {
  1209. uint16_t val = new_value;
  1210. #ifdef PCNET_DEBUG_CSR
  1211. printf("pcnet_csr_writew rap=%d val=0x%04x\n", rap, val);
  1212. #endif
  1213. switch (rap) {
  1214. case 0:
  1215. s->csr[0] &= ~(val & 0x7f00); /* Clear any interrupt flags */
  1216. s->csr[0] = (s->csr[0] & ~0x0040) | (val & 0x0048);
  1217. val = (val & 0x007f) | (s->csr[0] & 0x7f00);
  1218. /* IFF STOP, STRT and INIT are set, clear STRT and INIT */
  1219. if ((val&7) == 7)
  1220. val &= ~3;
  1221. if (!CSR_STOP(s) && (val & 4))
  1222. pcnet_stop(s);
  1223. if (!CSR_INIT(s) && (val & 1))
  1224. pcnet_init(s);
  1225. if (!CSR_STRT(s) && (val & 2))
  1226. pcnet_start(s);
  1227. if (CSR_TDMD(s))
  1228. pcnet_transmit(s);
  1229. return;
  1230. case 1:
  1231. case 2:
  1232. case 8:
  1233. case 9:
  1234. case 10:
  1235. case 11:
  1236. case 12:
  1237. case 13:
  1238. case 14:
  1239. case 15:
  1240. case 18: /* CRBAL */
  1241. case 19: /* CRBAU */
  1242. case 20: /* CXBAL */
  1243. case 21: /* CXBAU */
  1244. case 22: /* NRBAU */
  1245. case 23: /* NRBAU */
  1246. case 24:
  1247. case 25:
  1248. case 26:
  1249. case 27:
  1250. case 28:
  1251. case 29:
  1252. case 30:
  1253. case 31:
  1254. case 32:
  1255. case 33:
  1256. case 34:
  1257. case 35:
  1258. case 36:
  1259. case 37:
  1260. case 38:
  1261. case 39:
  1262. case 40: /* CRBC */
  1263. case 41:
  1264. case 42: /* CXBC */
  1265. case 43:
  1266. case 44:
  1267. case 45:
  1268. case 46: /* POLL */
  1269. case 47: /* POLLINT */
  1270. case 72:
  1271. case 74:
  1272. case 76: /* RCVRL */
  1273. case 78: /* XMTRL */
  1274. case 112:
  1275. if (CSR_STOP(s) || CSR_SPND(s))
  1276. break;
  1277. return;
  1278. case 3:
  1279. break;
  1280. case 4:
  1281. s->csr[4] &= ~(val & 0x026a);
  1282. val &= ~0x026a; val |= s->csr[4] & 0x026a;
  1283. break;
  1284. case 5:
  1285. s->csr[5] &= ~(val & 0x0a90);
  1286. val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
  1287. break;
  1288. case 16:
  1289. pcnet_csr_writew(s,1,val);
  1290. return;
  1291. case 17:
  1292. pcnet_csr_writew(s,2,val);
  1293. return;
  1294. case 58:
  1295. pcnet_bcr_writew(s,BCR_SWS,val);
  1296. break;
  1297. default:
  1298. return;
  1299. }
  1300. s->csr[rap] = val;
  1301. }
  1302. static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
  1303. {
  1304. uint32_t val;
  1305. switch (rap) {
  1306. case 0:
  1307. pcnet_update_irq(s);
  1308. val = s->csr[0];
  1309. val |= (val & 0x7800) ? 0x8000 : 0;
  1310. break;
  1311. case 16:
  1312. return pcnet_csr_readw(s,1);
  1313. case 17:
  1314. return pcnet_csr_readw(s,2);
  1315. case 58:
  1316. return pcnet_bcr_readw(s,BCR_SWS);
  1317. case 88:
  1318. val = s->csr[89];
  1319. val <<= 16;
  1320. val |= s->csr[88];
  1321. break;
  1322. default:
  1323. val = s->csr[rap];
  1324. }
  1325. #ifdef PCNET_DEBUG_CSR
  1326. printf("pcnet_csr_readw rap=%d val=0x%04x\n", rap, val);
  1327. #endif
  1328. return val;
  1329. }
  1330. static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
  1331. {
  1332. rap &= 127;
  1333. #ifdef PCNET_DEBUG_BCR
  1334. printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
  1335. #endif
  1336. switch (rap) {
  1337. case BCR_SWS:
  1338. if (!(CSR_STOP(s) || CSR_SPND(s)))
  1339. return;
  1340. val &= ~0x0300;
  1341. switch (val & 0x00ff) {
  1342. case 0:
  1343. val |= 0x0200;
  1344. break;
  1345. case 1:
  1346. val |= 0x0100;
  1347. break;
  1348. case 2:
  1349. case 3:
  1350. val |= 0x0300;
  1351. break;
  1352. default:
  1353. printf("Bad SWSTYLE=0x%02x\n", val & 0xff);
  1354. val = 0x0200;
  1355. break;
  1356. }
  1357. #ifdef PCNET_DEBUG
  1358. printf("BCR_SWS=0x%04x\n", val);
  1359. #endif
  1360. case BCR_LNKST:
  1361. case BCR_LED1:
  1362. case BCR_LED2:
  1363. case BCR_LED3:
  1364. case BCR_MC:
  1365. case BCR_FDC:
  1366. case BCR_BSBC:
  1367. case BCR_EECAS:
  1368. case BCR_PLAT:
  1369. s->bcr[rap] = val;
  1370. break;
  1371. default:
  1372. break;
  1373. }
  1374. }
  1375. uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
  1376. {
  1377. uint32_t val;
  1378. rap &= 127;
  1379. switch (rap) {
  1380. case BCR_LNKST:
  1381. case BCR_LED1:
  1382. case BCR_LED2:
  1383. case BCR_LED3:
  1384. val = s->bcr[rap] & ~0x8000;
  1385. val |= (val & 0x017f & s->lnkst) ? 0x8000 : 0;
  1386. break;
  1387. default:
  1388. val = rap < 32 ? s->bcr[rap] : 0;
  1389. break;
  1390. }
  1391. #ifdef PCNET_DEBUG_BCR
  1392. printf("pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
  1393. #endif
  1394. return val;
  1395. }
  1396. void pcnet_h_reset(void *opaque)
  1397. {
  1398. PCNetState *s = opaque;
  1399. s->bcr[BCR_MSRDA] = 0x0005;
  1400. s->bcr[BCR_MSWRA] = 0x0005;
  1401. s->bcr[BCR_MC ] = 0x0002;
  1402. s->bcr[BCR_LNKST] = 0x00c0;
  1403. s->bcr[BCR_LED1 ] = 0x0084;
  1404. s->bcr[BCR_LED2 ] = 0x0088;
  1405. s->bcr[BCR_LED3 ] = 0x0090;
  1406. s->bcr[BCR_FDC ] = 0x0000;
  1407. s->bcr[BCR_BSBC ] = 0x9001;
  1408. s->bcr[BCR_EECAS] = 0x0002;
  1409. s->bcr[BCR_SWS ] = 0x0200;
  1410. s->bcr[BCR_PLAT ] = 0xff06;
  1411. pcnet_s_reset(s);
  1412. pcnet_update_irq(s);
  1413. pcnet_poll_timer(s);
  1414. }
  1415. void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
  1416. {
  1417. PCNetState *s = opaque;
  1418. pcnet_poll_timer(s);
  1419. #ifdef PCNET_DEBUG_IO
  1420. printf("pcnet_ioport_writew addr=0x%08x val=0x%04x\n", addr, val);
  1421. #endif
  1422. if (!BCR_DWIO(s)) {
  1423. switch (addr & 0x0f) {
  1424. case 0x00: /* RDP */
  1425. pcnet_csr_writew(s, s->rap, val);
  1426. break;
  1427. case 0x02:
  1428. s->rap = val & 0x7f;
  1429. break;
  1430. case 0x06:
  1431. pcnet_bcr_writew(s, s->rap, val);
  1432. break;
  1433. }
  1434. }
  1435. pcnet_update_irq(s);
  1436. }
  1437. uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
  1438. {
  1439. PCNetState *s = opaque;
  1440. uint32_t val = -1;
  1441. pcnet_poll_timer(s);
  1442. if (!BCR_DWIO(s)) {
  1443. switch (addr & 0x0f) {
  1444. case 0x00: /* RDP */
  1445. val = pcnet_csr_readw(s, s->rap);
  1446. break;
  1447. case 0x02:
  1448. val = s->rap;
  1449. break;
  1450. case 0x04:
  1451. pcnet_s_reset(s);
  1452. val = 0;
  1453. break;
  1454. case 0x06:
  1455. val = pcnet_bcr_readw(s, s->rap);
  1456. break;
  1457. }
  1458. }
  1459. pcnet_update_irq(s);
  1460. #ifdef PCNET_DEBUG_IO
  1461. printf("pcnet_ioport_readw addr=0x%08x val=0x%04x\n", addr, val & 0xffff);
  1462. #endif
  1463. return val;
  1464. }
  1465. void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
  1466. {
  1467. PCNetState *s = opaque;
  1468. pcnet_poll_timer(s);
  1469. #ifdef PCNET_DEBUG_IO
  1470. printf("pcnet_ioport_writel addr=0x%08x val=0x%08x\n", addr, val);
  1471. #endif
  1472. if (BCR_DWIO(s)) {
  1473. switch (addr & 0x0f) {
  1474. case 0x00: /* RDP */
  1475. pcnet_csr_writew(s, s->rap, val & 0xffff);
  1476. break;
  1477. case 0x04:
  1478. s->rap = val & 0x7f;
  1479. break;
  1480. case 0x0c:
  1481. pcnet_bcr_writew(s, s->rap, val & 0xffff);
  1482. break;
  1483. }
  1484. } else
  1485. if ((addr & 0x0f) == 0) {
  1486. /* switch device to dword i/o mode */
  1487. pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
  1488. #ifdef PCNET_DEBUG_IO
  1489. printf("device switched into dword i/o mode\n");
  1490. #endif
  1491. }
  1492. pcnet_update_irq(s);
  1493. }
  1494. uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
  1495. {
  1496. PCNetState *s = opaque;
  1497. uint32_t val = -1;
  1498. pcnet_poll_timer(s);
  1499. if (BCR_DWIO(s)) {
  1500. switch (addr & 0x0f) {
  1501. case 0x00: /* RDP */
  1502. val = pcnet_csr_readw(s, s->rap);
  1503. break;
  1504. case 0x04:
  1505. val = s->rap;
  1506. break;
  1507. case 0x08:
  1508. pcnet_s_reset(s);
  1509. val = 0;
  1510. break;
  1511. case 0x0c:
  1512. val = pcnet_bcr_readw(s, s->rap);
  1513. break;
  1514. }
  1515. }
  1516. pcnet_update_irq(s);
  1517. #ifdef PCNET_DEBUG_IO
  1518. printf("pcnet_ioport_readl addr=0x%08x val=0x%08x\n", addr, val);
  1519. #endif
  1520. return val;
  1521. }
  1522. static bool is_version_2(void *opaque, int version_id)
  1523. {
  1524. return version_id == 2;
  1525. }
  1526. const VMStateDescription vmstate_pcnet = {
  1527. .name = "pcnet",
  1528. .version_id = 3,
  1529. .minimum_version_id = 2,
  1530. .minimum_version_id_old = 2,
  1531. .fields = (VMStateField []) {
  1532. VMSTATE_INT32(rap, PCNetState),
  1533. VMSTATE_INT32(isr, PCNetState),
  1534. VMSTATE_INT32(lnkst, PCNetState),
  1535. VMSTATE_UINT32(rdra, PCNetState),
  1536. VMSTATE_UINT32(tdra, PCNetState),
  1537. VMSTATE_BUFFER(prom, PCNetState),
  1538. VMSTATE_UINT16_ARRAY(csr, PCNetState, 128),
  1539. VMSTATE_UINT16_ARRAY(bcr, PCNetState, 32),
  1540. VMSTATE_UINT64(timer, PCNetState),
  1541. VMSTATE_INT32(xmit_pos, PCNetState),
  1542. VMSTATE_BUFFER(buffer, PCNetState),
  1543. VMSTATE_UNUSED_TEST(is_version_2, 4),
  1544. VMSTATE_INT32(tx_busy, PCNetState),
  1545. VMSTATE_TIMER(poll_timer, PCNetState),
  1546. VMSTATE_END_OF_LIST()
  1547. }
  1548. };
  1549. void pcnet_common_cleanup(PCNetState *d)
  1550. {
  1551. d->nic = NULL;
  1552. }
  1553. int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
  1554. {
  1555. int i;
  1556. uint16_t checksum;
  1557. s->poll_timer = qemu_new_timer_ns(vm_clock, pcnet_poll_timer, s);
  1558. qemu_macaddr_default_if_unset(&s->conf.macaddr);
  1559. s->nic = qemu_new_nic(info, &s->conf, dev->info->name, dev->id, s);
  1560. qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
  1561. add_boot_device_path(s->conf.bootindex, dev, "/ethernet-phy@0");
  1562. /* Initialize the PROM */
  1563. /*
  1564. Datasheet: http://pdfdata.datasheetsite.com/web/24528/AM79C970A.pdf
  1565. page 95
  1566. */
  1567. memcpy(s->prom, s->conf.macaddr.a, 6);
  1568. /* Reserved Location: must be 00h */
  1569. s->prom[6] = s->prom[7] = 0x00;
  1570. /* Reserved Location: must be 00h */
  1571. s->prom[8] = 0x00;
  1572. /* Hardware ID: must be 11h if compatibility to AMD drivers is desired */
  1573. s->prom[9] = 0x11;
  1574. /* User programmable space, init with 0 */
  1575. s->prom[10] = s->prom[11] = 0x00;
  1576. /* LSByte of two-byte checksum, which is the sum of bytes 00h-0Bh
  1577. and bytes 0Eh and 0Fh, must therefore be initialized with 0! */
  1578. s->prom[12] = s->prom[13] = 0x00;
  1579. /* Must be ASCII W (57h) if compatibility to AMD
  1580. driver software is desired */
  1581. s->prom[14] = s->prom[15] = 0x57;
  1582. for (i = 0, checksum = 0; i < 16; i++) {
  1583. checksum += s->prom[i];
  1584. }
  1585. *(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
  1586. return 0;
  1587. }