pckbd.c 16 KB

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  1. /*
  2. * QEMU PC keyboard emulation
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "isa.h"
  26. #include "pc.h"
  27. #include "ps2.h"
  28. #include "sysemu.h"
  29. /* debug PC keyboard */
  30. //#define DEBUG_KBD
  31. #ifdef DEBUG_KBD
  32. #define DPRINTF(fmt, ...) \
  33. do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
  34. #else
  35. #define DPRINTF(fmt, ...)
  36. #endif
  37. /* Keyboard Controller Commands */
  38. #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
  39. #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
  40. #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
  41. #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
  42. #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
  43. #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
  44. #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
  45. #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
  46. #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
  47. #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
  48. #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
  49. #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
  50. #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
  51. #define KBD_CCMD_WRITE_OBUF 0xD2
  52. #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
  53. initiated by the auxiliary device */
  54. #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
  55. #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
  56. #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
  57. #define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
  58. #define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
  59. #define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
  60. /* Keyboard Commands */
  61. #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
  62. #define KBD_CMD_ECHO 0xEE
  63. #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
  64. #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
  65. #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
  66. #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
  67. #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
  68. #define KBD_CMD_RESET 0xFF /* Reset */
  69. /* Keyboard Replies */
  70. #define KBD_REPLY_POR 0xAA /* Power on reset */
  71. #define KBD_REPLY_ACK 0xFA /* Command ACK */
  72. #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
  73. /* Status Register Bits */
  74. #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
  75. #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
  76. #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
  77. #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
  78. #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
  79. #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
  80. #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
  81. #define KBD_STAT_PERR 0x80 /* Parity error */
  82. /* Controller Mode Register Bits */
  83. #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
  84. #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
  85. #define KBD_MODE_SYS 0x04 /* The system flag (?) */
  86. #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
  87. #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
  88. #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
  89. #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
  90. #define KBD_MODE_RFU 0x80
  91. /* Output Port Bits */
  92. #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
  93. #define KBD_OUT_A20 0x02 /* x86 only */
  94. #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
  95. #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
  96. /* Mouse Commands */
  97. #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
  98. #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
  99. #define AUX_SET_RES 0xE8 /* Set resolution */
  100. #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
  101. #define AUX_SET_STREAM 0xEA /* Set stream mode */
  102. #define AUX_POLL 0xEB /* Poll */
  103. #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
  104. #define AUX_SET_WRAP 0xEE /* Set wrap mode */
  105. #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
  106. #define AUX_GET_TYPE 0xF2 /* Get type */
  107. #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
  108. #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
  109. #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
  110. #define AUX_SET_DEFAULT 0xF6
  111. #define AUX_RESET 0xFF /* Reset aux device */
  112. #define AUX_ACK 0xFA /* Command byte ACK. */
  113. #define MOUSE_STATUS_REMOTE 0x40
  114. #define MOUSE_STATUS_ENABLED 0x20
  115. #define MOUSE_STATUS_SCALE21 0x10
  116. #define KBD_PENDING_KBD 1
  117. #define KBD_PENDING_AUX 2
  118. typedef struct KBDState {
  119. uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
  120. uint8_t status;
  121. uint8_t mode;
  122. uint8_t outport;
  123. /* Bitmask of devices with data available. */
  124. uint8_t pending;
  125. void *kbd;
  126. void *mouse;
  127. qemu_irq irq_kbd;
  128. qemu_irq irq_mouse;
  129. qemu_irq *a20_out;
  130. target_phys_addr_t mask;
  131. } KBDState;
  132. /* update irq and KBD_STAT_[MOUSE_]OBF */
  133. /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
  134. incorrect, but it avoids having to simulate exact delays */
  135. static void kbd_update_irq(KBDState *s)
  136. {
  137. int irq_kbd_level, irq_mouse_level;
  138. irq_kbd_level = 0;
  139. irq_mouse_level = 0;
  140. s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
  141. s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
  142. if (s->pending) {
  143. s->status |= KBD_STAT_OBF;
  144. s->outport |= KBD_OUT_OBF;
  145. /* kbd data takes priority over aux data. */
  146. if (s->pending == KBD_PENDING_AUX) {
  147. s->status |= KBD_STAT_MOUSE_OBF;
  148. s->outport |= KBD_OUT_MOUSE_OBF;
  149. if (s->mode & KBD_MODE_MOUSE_INT)
  150. irq_mouse_level = 1;
  151. } else {
  152. if ((s->mode & KBD_MODE_KBD_INT) &&
  153. !(s->mode & KBD_MODE_DISABLE_KBD))
  154. irq_kbd_level = 1;
  155. }
  156. }
  157. qemu_set_irq(s->irq_kbd, irq_kbd_level);
  158. qemu_set_irq(s->irq_mouse, irq_mouse_level);
  159. }
  160. static void kbd_update_kbd_irq(void *opaque, int level)
  161. {
  162. KBDState *s = (KBDState *)opaque;
  163. if (level)
  164. s->pending |= KBD_PENDING_KBD;
  165. else
  166. s->pending &= ~KBD_PENDING_KBD;
  167. kbd_update_irq(s);
  168. }
  169. static void kbd_update_aux_irq(void *opaque, int level)
  170. {
  171. KBDState *s = (KBDState *)opaque;
  172. if (level)
  173. s->pending |= KBD_PENDING_AUX;
  174. else
  175. s->pending &= ~KBD_PENDING_AUX;
  176. kbd_update_irq(s);
  177. }
  178. static uint32_t kbd_read_status(void *opaque, uint32_t addr)
  179. {
  180. KBDState *s = opaque;
  181. int val;
  182. val = s->status;
  183. DPRINTF("kbd: read status=0x%02x\n", val);
  184. return val;
  185. }
  186. static void kbd_queue(KBDState *s, int b, int aux)
  187. {
  188. if (aux)
  189. ps2_queue(s->mouse, b);
  190. else
  191. ps2_queue(s->kbd, b);
  192. }
  193. static void outport_write(KBDState *s, uint32_t val)
  194. {
  195. DPRINTF("kbd: write outport=0x%02x\n", val);
  196. s->outport = val;
  197. if (s->a20_out) {
  198. qemu_set_irq(*s->a20_out, (val >> 1) & 1);
  199. }
  200. if (!(val & 1)) {
  201. qemu_system_reset_request();
  202. }
  203. }
  204. static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
  205. {
  206. KBDState *s = opaque;
  207. DPRINTF("kbd: write cmd=0x%02x\n", val);
  208. /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
  209. * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
  210. * command specify the output port bits to be pulsed.
  211. * 0: Bit should be pulsed. 1: Bit should not be modified.
  212. * The only useful version of this command is pulsing bit 0,
  213. * which does a CPU reset.
  214. */
  215. if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
  216. if(!(val & 1))
  217. val = KBD_CCMD_RESET;
  218. else
  219. val = KBD_CCMD_NO_OP;
  220. }
  221. switch(val) {
  222. case KBD_CCMD_READ_MODE:
  223. kbd_queue(s, s->mode, 0);
  224. break;
  225. case KBD_CCMD_WRITE_MODE:
  226. case KBD_CCMD_WRITE_OBUF:
  227. case KBD_CCMD_WRITE_AUX_OBUF:
  228. case KBD_CCMD_WRITE_MOUSE:
  229. case KBD_CCMD_WRITE_OUTPORT:
  230. s->write_cmd = val;
  231. break;
  232. case KBD_CCMD_MOUSE_DISABLE:
  233. s->mode |= KBD_MODE_DISABLE_MOUSE;
  234. break;
  235. case KBD_CCMD_MOUSE_ENABLE:
  236. s->mode &= ~KBD_MODE_DISABLE_MOUSE;
  237. break;
  238. case KBD_CCMD_TEST_MOUSE:
  239. kbd_queue(s, 0x00, 0);
  240. break;
  241. case KBD_CCMD_SELF_TEST:
  242. s->status |= KBD_STAT_SELFTEST;
  243. kbd_queue(s, 0x55, 0);
  244. break;
  245. case KBD_CCMD_KBD_TEST:
  246. kbd_queue(s, 0x00, 0);
  247. break;
  248. case KBD_CCMD_KBD_DISABLE:
  249. s->mode |= KBD_MODE_DISABLE_KBD;
  250. kbd_update_irq(s);
  251. break;
  252. case KBD_CCMD_KBD_ENABLE:
  253. s->mode &= ~KBD_MODE_DISABLE_KBD;
  254. kbd_update_irq(s);
  255. break;
  256. case KBD_CCMD_READ_INPORT:
  257. kbd_queue(s, 0x00, 0);
  258. break;
  259. case KBD_CCMD_READ_OUTPORT:
  260. kbd_queue(s, s->outport, 0);
  261. break;
  262. case KBD_CCMD_ENABLE_A20:
  263. if (s->a20_out) {
  264. qemu_irq_raise(*s->a20_out);
  265. }
  266. s->outport |= KBD_OUT_A20;
  267. break;
  268. case KBD_CCMD_DISABLE_A20:
  269. if (s->a20_out) {
  270. qemu_irq_lower(*s->a20_out);
  271. }
  272. s->outport &= ~KBD_OUT_A20;
  273. break;
  274. case KBD_CCMD_RESET:
  275. qemu_system_reset_request();
  276. break;
  277. case KBD_CCMD_NO_OP:
  278. /* ignore that */
  279. break;
  280. default:
  281. fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
  282. break;
  283. }
  284. }
  285. static uint32_t kbd_read_data(void *opaque, uint32_t addr)
  286. {
  287. KBDState *s = opaque;
  288. uint32_t val;
  289. if (s->pending == KBD_PENDING_AUX)
  290. val = ps2_read_data(s->mouse);
  291. else
  292. val = ps2_read_data(s->kbd);
  293. DPRINTF("kbd: read data=0x%02x\n", val);
  294. return val;
  295. }
  296. static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
  297. {
  298. KBDState *s = opaque;
  299. DPRINTF("kbd: write data=0x%02x\n", val);
  300. switch(s->write_cmd) {
  301. case 0:
  302. ps2_write_keyboard(s->kbd, val);
  303. break;
  304. case KBD_CCMD_WRITE_MODE:
  305. s->mode = val;
  306. ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
  307. /* ??? */
  308. kbd_update_irq(s);
  309. break;
  310. case KBD_CCMD_WRITE_OBUF:
  311. kbd_queue(s, val, 0);
  312. break;
  313. case KBD_CCMD_WRITE_AUX_OBUF:
  314. kbd_queue(s, val, 1);
  315. break;
  316. case KBD_CCMD_WRITE_OUTPORT:
  317. outport_write(s, val);
  318. break;
  319. case KBD_CCMD_WRITE_MOUSE:
  320. ps2_write_mouse(s->mouse, val);
  321. break;
  322. default:
  323. break;
  324. }
  325. s->write_cmd = 0;
  326. }
  327. static void kbd_reset(void *opaque)
  328. {
  329. KBDState *s = opaque;
  330. s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
  331. s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
  332. s->outport = KBD_OUT_RESET | KBD_OUT_A20;
  333. }
  334. static const VMStateDescription vmstate_kbd = {
  335. .name = "pckbd",
  336. .version_id = 3,
  337. .minimum_version_id = 3,
  338. .minimum_version_id_old = 3,
  339. .fields = (VMStateField []) {
  340. VMSTATE_UINT8(write_cmd, KBDState),
  341. VMSTATE_UINT8(status, KBDState),
  342. VMSTATE_UINT8(mode, KBDState),
  343. VMSTATE_UINT8(pending, KBDState),
  344. VMSTATE_END_OF_LIST()
  345. }
  346. };
  347. /* Memory mapped interface */
  348. static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
  349. {
  350. KBDState *s = opaque;
  351. if (addr & s->mask)
  352. return kbd_read_status(s, 0) & 0xff;
  353. else
  354. return kbd_read_data(s, 0) & 0xff;
  355. }
  356. static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
  357. {
  358. KBDState *s = opaque;
  359. if (addr & s->mask)
  360. kbd_write_command(s, 0, value & 0xff);
  361. else
  362. kbd_write_data(s, 0, value & 0xff);
  363. }
  364. static const MemoryRegionOps i8042_mmio_ops = {
  365. .endianness = DEVICE_NATIVE_ENDIAN,
  366. .old_mmio = {
  367. .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
  368. .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
  369. },
  370. };
  371. void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  372. MemoryRegion *region, ram_addr_t size,
  373. target_phys_addr_t mask)
  374. {
  375. KBDState *s = g_malloc0(sizeof(KBDState));
  376. s->irq_kbd = kbd_irq;
  377. s->irq_mouse = mouse_irq;
  378. s->mask = mask;
  379. vmstate_register(NULL, 0, &vmstate_kbd, s);
  380. memory_region_init_io(region, &i8042_mmio_ops, s, "i8042", size);
  381. s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
  382. s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
  383. qemu_register_reset(kbd_reset, s);
  384. }
  385. typedef struct ISAKBDState {
  386. ISADevice dev;
  387. KBDState kbd;
  388. MemoryRegion io[2];
  389. } ISAKBDState;
  390. void i8042_isa_mouse_fake_event(void *opaque)
  391. {
  392. ISADevice *dev = opaque;
  393. KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
  394. ps2_mouse_fake_event(s->mouse);
  395. }
  396. void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
  397. {
  398. KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
  399. s->a20_out = a20_out;
  400. }
  401. static const VMStateDescription vmstate_kbd_isa = {
  402. .name = "pckbd",
  403. .version_id = 3,
  404. .minimum_version_id = 3,
  405. .minimum_version_id_old = 3,
  406. .fields = (VMStateField []) {
  407. VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
  408. VMSTATE_END_OF_LIST()
  409. }
  410. };
  411. static const MemoryRegionPortio i8042_data_portio[] = {
  412. { 0, 1, 1, .read = kbd_read_data, .write = kbd_write_data },
  413. PORTIO_END_OF_LIST()
  414. };
  415. static const MemoryRegionPortio i8042_cmd_portio[] = {
  416. { 0, 1, 1, .read = kbd_read_status, .write = kbd_write_command },
  417. PORTIO_END_OF_LIST()
  418. };
  419. static const MemoryRegionOps i8042_data_ops = {
  420. .old_portio = i8042_data_portio
  421. };
  422. static const MemoryRegionOps i8042_cmd_ops = {
  423. .old_portio = i8042_cmd_portio
  424. };
  425. static int i8042_initfn(ISADevice *dev)
  426. {
  427. ISAKBDState *isa_s = DO_UPCAST(ISAKBDState, dev, dev);
  428. KBDState *s = &isa_s->kbd;
  429. isa_init_irq(dev, &s->irq_kbd, 1);
  430. isa_init_irq(dev, &s->irq_mouse, 12);
  431. memory_region_init_io(isa_s->io + 0, &i8042_data_ops, s, "i8042-data", 1);
  432. isa_register_ioport(dev, isa_s->io + 0, 0x60);
  433. memory_region_init_io(isa_s->io + 1, &i8042_cmd_ops, s, "i8042-cmd", 1);
  434. isa_register_ioport(dev, isa_s->io + 1, 0x64);
  435. s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
  436. s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
  437. qemu_register_reset(kbd_reset, s);
  438. return 0;
  439. }
  440. static ISADeviceInfo i8042_info = {
  441. .qdev.name = "i8042",
  442. .qdev.size = sizeof(ISAKBDState),
  443. .qdev.vmsd = &vmstate_kbd_isa,
  444. .qdev.no_user = 1,
  445. .init = i8042_initfn,
  446. };
  447. static void i8042_register(void)
  448. {
  449. isa_qdev_register(&i8042_info);
  450. }
  451. device_init(i8042_register)