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omap_gpmc.c 28 KB

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  1. /*
  2. * TI OMAP general purpose memory controller emulation.
  3. *
  4. * Copyright (C) 2007-2009 Nokia Corporation
  5. * Original code written by Andrzej Zaborowski <andrew@openedhand.com>
  6. * Enhancements for OMAP3 and NAND support written by Juha Riihimäki
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 or
  11. * (at your option) any later version of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include "hw.h"
  22. #include "flash.h"
  23. #include "omap.h"
  24. #include "memory.h"
  25. #include "exec-memory.h"
  26. /* General-Purpose Memory Controller */
  27. struct omap_gpmc_s {
  28. qemu_irq irq;
  29. qemu_irq drq;
  30. MemoryRegion iomem;
  31. int accept_256;
  32. uint8_t revision;
  33. uint8_t sysconfig;
  34. uint16_t irqst;
  35. uint16_t irqen;
  36. uint16_t lastirq;
  37. uint16_t timeout;
  38. uint16_t config;
  39. struct omap_gpmc_cs_file_s {
  40. uint32_t config[7];
  41. MemoryRegion *iomem;
  42. MemoryRegion container;
  43. MemoryRegion nandiomem;
  44. DeviceState *dev;
  45. } cs_file[8];
  46. int ecc_cs;
  47. int ecc_ptr;
  48. uint32_t ecc_cfg;
  49. ECCState ecc[9];
  50. struct prefetch {
  51. uint32_t config1; /* GPMC_PREFETCH_CONFIG1 */
  52. uint32_t transfercount; /* GPMC_PREFETCH_CONFIG2:TRANSFERCOUNT */
  53. int startengine; /* GPMC_PREFETCH_CONTROL:STARTENGINE */
  54. int fifopointer; /* GPMC_PREFETCH_STATUS:FIFOPOINTER */
  55. int count; /* GPMC_PREFETCH_STATUS:COUNTVALUE */
  56. MemoryRegion iomem;
  57. uint8_t fifo[64];
  58. } prefetch;
  59. };
  60. #define OMAP_GPMC_8BIT 0
  61. #define OMAP_GPMC_16BIT 1
  62. #define OMAP_GPMC_NOR 0
  63. #define OMAP_GPMC_NAND 2
  64. static int omap_gpmc_devtype(struct omap_gpmc_cs_file_s *f)
  65. {
  66. return (f->config[0] >> 10) & 3;
  67. }
  68. static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
  69. {
  70. /* devsize field is really 2 bits but we ignore the high
  71. * bit to ensure consistent behaviour if the guest sets
  72. * it (values 2 and 3 are reserved in the TRM)
  73. */
  74. return (f->config[0] >> 12) & 1;
  75. }
  76. /* Extract the chip-select value from the prefetch config1 register */
  77. static int prefetch_cs(uint32_t config1)
  78. {
  79. return (config1 >> 24) & 7;
  80. }
  81. static int prefetch_threshold(uint32_t config1)
  82. {
  83. return (config1 >> 8) & 0x7f;
  84. }
  85. static void omap_gpmc_int_update(struct omap_gpmc_s *s)
  86. {
  87. /* The TRM is a bit unclear, but it seems to say that
  88. * the TERMINALCOUNTSTATUS bit is set only on the
  89. * transition when the prefetch engine goes from
  90. * active to inactive, whereas the FIFOEVENTSTATUS
  91. * bit is held high as long as the fifo has at
  92. * least THRESHOLD bytes available.
  93. * So we do the latter here, but TERMINALCOUNTSTATUS
  94. * is set elsewhere.
  95. */
  96. if (s->prefetch.fifopointer >= prefetch_threshold(s->prefetch.config1)) {
  97. s->irqst |= 1;
  98. }
  99. if ((s->irqen & s->irqst) != s->lastirq) {
  100. s->lastirq = s->irqen & s->irqst;
  101. qemu_set_irq(s->irq, s->lastirq);
  102. }
  103. }
  104. static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
  105. {
  106. if (s->prefetch.config1 & 4) {
  107. qemu_set_irq(s->drq, value);
  108. }
  109. }
  110. /* Access functions for when a NAND-like device is mapped into memory:
  111. * all addresses in the region behave like accesses to the relevant
  112. * GPMC_NAND_DATA_i register (which is actually implemented to call these)
  113. */
  114. static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
  115. unsigned size)
  116. {
  117. struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
  118. uint64_t v;
  119. nand_setpins(f->dev, 0, 0, 0, 1, 0);
  120. switch (omap_gpmc_devsize(f)) {
  121. case OMAP_GPMC_8BIT:
  122. v = nand_getio(f->dev);
  123. if (size == 1) {
  124. return v;
  125. }
  126. v |= (nand_getio(f->dev) << 8);
  127. if (size == 2) {
  128. return v;
  129. }
  130. v |= (nand_getio(f->dev) << 16);
  131. v |= (nand_getio(f->dev) << 24);
  132. return v;
  133. case OMAP_GPMC_16BIT:
  134. v = nand_getio(f->dev);
  135. if (size == 1) {
  136. /* 8 bit read from 16 bit device : probably a guest bug */
  137. return v & 0xff;
  138. }
  139. if (size == 2) {
  140. return v;
  141. }
  142. v |= (nand_getio(f->dev) << 16);
  143. return v;
  144. default:
  145. abort();
  146. }
  147. }
  148. static void omap_nand_setio(DeviceState *dev, uint64_t value,
  149. int nandsize, int size)
  150. {
  151. /* Write the specified value to the NAND device, respecting
  152. * both size of the NAND device and size of the write access.
  153. */
  154. switch (nandsize) {
  155. case OMAP_GPMC_8BIT:
  156. switch (size) {
  157. case 1:
  158. nand_setio(dev, value & 0xff);
  159. break;
  160. case 2:
  161. nand_setio(dev, value & 0xff);
  162. nand_setio(dev, (value >> 8) & 0xff);
  163. break;
  164. case 4:
  165. default:
  166. nand_setio(dev, value & 0xff);
  167. nand_setio(dev, (value >> 8) & 0xff);
  168. nand_setio(dev, (value >> 16) & 0xff);
  169. nand_setio(dev, (value >> 24) & 0xff);
  170. break;
  171. }
  172. break;
  173. case OMAP_GPMC_16BIT:
  174. switch (size) {
  175. case 1:
  176. /* writing to a 16bit device with 8bit access is probably a guest
  177. * bug; pass the value through anyway.
  178. */
  179. case 2:
  180. nand_setio(dev, value & 0xffff);
  181. break;
  182. case 4:
  183. default:
  184. nand_setio(dev, value & 0xffff);
  185. nand_setio(dev, (value >> 16) & 0xffff);
  186. break;
  187. }
  188. break;
  189. }
  190. }
  191. static void omap_nand_write(void *opaque, target_phys_addr_t addr,
  192. uint64_t value, unsigned size)
  193. {
  194. struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
  195. nand_setpins(f->dev, 0, 0, 0, 1, 0);
  196. omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
  197. }
  198. static const MemoryRegionOps omap_nand_ops = {
  199. .read = omap_nand_read,
  200. .write = omap_nand_write,
  201. .endianness = DEVICE_NATIVE_ENDIAN,
  202. };
  203. static void fill_prefetch_fifo(struct omap_gpmc_s *s)
  204. {
  205. /* Fill the prefetch FIFO by reading data from NAND.
  206. * We do this synchronously, unlike the hardware which
  207. * will do this asynchronously. We refill when the
  208. * FIFO has THRESHOLD bytes free, and we always refill
  209. * as much data as possible starting at the top end
  210. * of the FIFO.
  211. * (We have to refill at THRESHOLD rather than waiting
  212. * for the FIFO to empty to allow for the case where
  213. * the FIFO size isn't an exact multiple of THRESHOLD
  214. * and we're doing DMA transfers.)
  215. * This means we never need to handle wrap-around in
  216. * the fifo-reading code, and the next byte of data
  217. * to read is always fifo[63 - fifopointer].
  218. */
  219. int fptr;
  220. int cs = prefetch_cs(s->prefetch.config1);
  221. int is16bit = (((s->cs_file[cs].config[0] >> 12) & 3) != 0);
  222. int bytes;
  223. /* Don't believe the bit of the OMAP TRM that says that COUNTVALUE
  224. * and TRANSFERCOUNT are in units of 16 bit words for 16 bit NAND.
  225. * Instead believe the bit that says it is always a byte count.
  226. */
  227. bytes = 64 - s->prefetch.fifopointer;
  228. if (bytes > s->prefetch.count) {
  229. bytes = s->prefetch.count;
  230. }
  231. s->prefetch.count -= bytes;
  232. s->prefetch.fifopointer += bytes;
  233. fptr = 64 - s->prefetch.fifopointer;
  234. /* Move the existing data in the FIFO so it sits just
  235. * before what we're about to read in
  236. */
  237. while (fptr < (64 - bytes)) {
  238. s->prefetch.fifo[fptr] = s->prefetch.fifo[fptr + bytes];
  239. fptr++;
  240. }
  241. while (fptr < 64) {
  242. if (is16bit) {
  243. uint32_t v = omap_nand_read(&s->cs_file[cs], 0, 2);
  244. s->prefetch.fifo[fptr++] = v & 0xff;
  245. s->prefetch.fifo[fptr++] = (v >> 8) & 0xff;
  246. } else {
  247. s->prefetch.fifo[fptr++] = omap_nand_read(&s->cs_file[cs], 0, 1);
  248. }
  249. }
  250. if (s->prefetch.startengine && (s->prefetch.count == 0)) {
  251. /* This was the final transfer: raise TERMINALCOUNTSTATUS */
  252. s->irqst |= 2;
  253. s->prefetch.startengine = 0;
  254. }
  255. /* If there are any bytes in the FIFO at this point then
  256. * we must raise a DMA request (either this is a final part
  257. * transfer, or we filled the FIFO in which case we certainly
  258. * have THRESHOLD bytes available)
  259. */
  260. if (s->prefetch.fifopointer != 0) {
  261. omap_gpmc_dma_update(s, 1);
  262. }
  263. omap_gpmc_int_update(s);
  264. }
  265. /* Access functions for a NAND-like device when the prefetch/postwrite
  266. * engine is enabled -- all addresses in the region behave alike:
  267. * data is read or written to the FIFO.
  268. */
  269. static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
  270. unsigned size)
  271. {
  272. struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
  273. uint32_t data;
  274. if (s->prefetch.config1 & 1) {
  275. /* The TRM doesn't define the behaviour if you read from the
  276. * FIFO when the prefetch engine is in write mode. We choose
  277. * to always return zero.
  278. */
  279. return 0;
  280. }
  281. /* Note that trying to read an empty fifo repeats the last byte */
  282. if (s->prefetch.fifopointer) {
  283. s->prefetch.fifopointer--;
  284. }
  285. data = s->prefetch.fifo[63 - s->prefetch.fifopointer];
  286. if (s->prefetch.fifopointer ==
  287. (64 - prefetch_threshold(s->prefetch.config1))) {
  288. /* We've drained THRESHOLD bytes now. So deassert the
  289. * DMA request, then refill the FIFO (which will probably
  290. * assert it again.)
  291. */
  292. omap_gpmc_dma_update(s, 0);
  293. fill_prefetch_fifo(s);
  294. }
  295. omap_gpmc_int_update(s);
  296. return data;
  297. }
  298. static void omap_gpmc_prefetch_write(void *opaque, target_phys_addr_t addr,
  299. uint64_t value, unsigned size)
  300. {
  301. struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
  302. int cs = prefetch_cs(s->prefetch.config1);
  303. if ((s->prefetch.config1 & 1) == 0) {
  304. /* The TRM doesn't define the behaviour of writing to the
  305. * FIFO when the prefetch engine is in read mode. We
  306. * choose to ignore the write.
  307. */
  308. return;
  309. }
  310. if (s->prefetch.count == 0) {
  311. /* The TRM doesn't define the behaviour of writing to the
  312. * FIFO if the transfer is complete. We choose to ignore.
  313. */
  314. return;
  315. }
  316. /* The only reason we do any data buffering in postwrite
  317. * mode is if we are talking to a 16 bit NAND device, in
  318. * which case we need to buffer the first byte of the
  319. * 16 bit word until the other byte arrives.
  320. */
  321. int is16bit = (((s->cs_file[cs].config[0] >> 12) & 3) != 0);
  322. if (is16bit) {
  323. /* fifopointer alternates between 64 (waiting for first
  324. * byte of word) and 63 (waiting for second byte)
  325. */
  326. if (s->prefetch.fifopointer == 64) {
  327. s->prefetch.fifo[0] = value;
  328. s->prefetch.fifopointer--;
  329. } else {
  330. value = (value << 8) | s->prefetch.fifo[0];
  331. omap_nand_write(&s->cs_file[cs], 0, value, 2);
  332. s->prefetch.count--;
  333. s->prefetch.fifopointer = 64;
  334. }
  335. } else {
  336. /* Just write the byte : fifopointer remains 64 at all times */
  337. omap_nand_write(&s->cs_file[cs], 0, value, 1);
  338. s->prefetch.count--;
  339. }
  340. if (s->prefetch.count == 0) {
  341. /* Final transfer: raise TERMINALCOUNTSTATUS */
  342. s->irqst |= 2;
  343. s->prefetch.startengine = 0;
  344. }
  345. omap_gpmc_int_update(s);
  346. }
  347. static const MemoryRegionOps omap_prefetch_ops = {
  348. .read = omap_gpmc_prefetch_read,
  349. .write = omap_gpmc_prefetch_write,
  350. .endianness = DEVICE_NATIVE_ENDIAN,
  351. .impl.min_access_size = 1,
  352. .impl.max_access_size = 1,
  353. };
  354. static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
  355. {
  356. /* Return the MemoryRegion* to map/unmap for this chipselect */
  357. struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
  358. if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
  359. return f->iomem;
  360. }
  361. if ((s->prefetch.config1 & 0x80) &&
  362. (prefetch_cs(s->prefetch.config1) == cs)) {
  363. /* The prefetch engine is enabled for this CS: map the FIFO */
  364. return &s->prefetch.iomem;
  365. }
  366. return &f->nandiomem;
  367. }
  368. static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
  369. {
  370. struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
  371. uint32_t mask = (f->config[6] >> 8) & 0xf;
  372. uint32_t base = f->config[6] & 0x3f;
  373. uint32_t size;
  374. if (!f->iomem && !f->dev) {
  375. return;
  376. }
  377. if (!(f->config[6] & (1 << 6))) {
  378. /* Do nothing unless CSVALID */
  379. return;
  380. }
  381. /* TODO: check for overlapping regions and report access errors */
  382. if (mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf
  383. && !(s->accept_256 && !mask)) {
  384. fprintf(stderr, "%s: invalid chip-select mask address (0x%x)\n",
  385. __func__, mask);
  386. }
  387. base <<= 24;
  388. size = (0x0fffffff & ~(mask << 24)) + 1;
  389. /* TODO: rather than setting the size of the mapping (which should be
  390. * constant), the mask should cause wrapping of the address space, so
  391. * that the same memory becomes accessible at every <i>size</i> bytes
  392. * starting from <i>base</i>. */
  393. memory_region_init(&f->container, "omap-gpmc-file", size);
  394. memory_region_add_subregion(&f->container, 0,
  395. omap_gpmc_cs_memregion(s, cs));
  396. memory_region_add_subregion(get_system_memory(), base,
  397. &f->container);
  398. }
  399. static void omap_gpmc_cs_unmap(struct omap_gpmc_s *s, int cs)
  400. {
  401. struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
  402. if (!(f->config[6] & (1 << 6))) {
  403. /* Do nothing unless CSVALID */
  404. return;
  405. }
  406. if (!f->iomem && !f->dev) {
  407. return;
  408. }
  409. memory_region_del_subregion(get_system_memory(), &f->container);
  410. memory_region_del_subregion(&f->container, omap_gpmc_cs_memregion(s, cs));
  411. memory_region_destroy(&f->container);
  412. }
  413. void omap_gpmc_reset(struct omap_gpmc_s *s)
  414. {
  415. int i;
  416. s->sysconfig = 0;
  417. s->irqst = 0;
  418. s->irqen = 0;
  419. omap_gpmc_int_update(s);
  420. s->timeout = 0;
  421. s->config = 0xa00;
  422. s->prefetch.config1 = 0x00004000;
  423. s->prefetch.transfercount = 0x00000000;
  424. s->prefetch.startengine = 0;
  425. s->prefetch.fifopointer = 0;
  426. s->prefetch.count = 0;
  427. for (i = 0; i < 8; i ++) {
  428. omap_gpmc_cs_unmap(s, i);
  429. s->cs_file[i].config[1] = 0x101001;
  430. s->cs_file[i].config[2] = 0x020201;
  431. s->cs_file[i].config[3] = 0x10031003;
  432. s->cs_file[i].config[4] = 0x10f1111;
  433. s->cs_file[i].config[5] = 0;
  434. s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
  435. s->cs_file[i].config[6] = 0xf00;
  436. /* In theory we could probe attached devices for some CFG1
  437. * bits here, but we just retain them across resets as they
  438. * were set initially by omap_gpmc_attach().
  439. */
  440. if (i == 0) {
  441. s->cs_file[i].config[0] &= 0x00433e00;
  442. s->cs_file[i].config[6] |= 1 << 6; /* CSVALID */
  443. omap_gpmc_cs_map(s, i);
  444. } else {
  445. s->cs_file[i].config[0] &= 0x00403c00;
  446. }
  447. }
  448. s->ecc_cs = 0;
  449. s->ecc_ptr = 0;
  450. s->ecc_cfg = 0x3fcff000;
  451. for (i = 0; i < 9; i ++)
  452. ecc_reset(&s->ecc[i]);
  453. }
  454. static int gpmc_wordaccess_only(target_phys_addr_t addr)
  455. {
  456. /* Return true if the register offset is to a register that
  457. * only permits word width accesses.
  458. * Non-word accesses are only OK for GPMC_NAND_DATA/ADDRESS/COMMAND
  459. * for any chipselect.
  460. */
  461. if (addr >= 0x60 && addr <= 0x1d4) {
  462. int cs = (addr - 0x60) / 0x30;
  463. addr -= cs * 0x30;
  464. if (addr >= 0x7c && addr < 0x88) {
  465. /* GPMC_NAND_COMMAND, GPMC_NAND_ADDRESS, GPMC_NAND_DATA */
  466. return 0;
  467. }
  468. }
  469. return 1;
  470. }
  471. static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
  472. unsigned size)
  473. {
  474. struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
  475. int cs;
  476. struct omap_gpmc_cs_file_s *f;
  477. if (size != 4 && gpmc_wordaccess_only(addr)) {
  478. return omap_badwidth_read32(opaque, addr);
  479. }
  480. switch (addr) {
  481. case 0x000: /* GPMC_REVISION */
  482. return s->revision;
  483. case 0x010: /* GPMC_SYSCONFIG */
  484. return s->sysconfig;
  485. case 0x014: /* GPMC_SYSSTATUS */
  486. return 1; /* RESETDONE */
  487. case 0x018: /* GPMC_IRQSTATUS */
  488. return s->irqst;
  489. case 0x01c: /* GPMC_IRQENABLE */
  490. return s->irqen;
  491. case 0x040: /* GPMC_TIMEOUT_CONTROL */
  492. return s->timeout;
  493. case 0x044: /* GPMC_ERR_ADDRESS */
  494. case 0x048: /* GPMC_ERR_TYPE */
  495. return 0;
  496. case 0x050: /* GPMC_CONFIG */
  497. return s->config;
  498. case 0x054: /* GPMC_STATUS */
  499. return 0x001;
  500. case 0x060 ... 0x1d4:
  501. cs = (addr - 0x060) / 0x30;
  502. addr -= cs * 0x30;
  503. f = s->cs_file + cs;
  504. switch (addr) {
  505. case 0x60: /* GPMC_CONFIG1 */
  506. return f->config[0];
  507. case 0x64: /* GPMC_CONFIG2 */
  508. return f->config[1];
  509. case 0x68: /* GPMC_CONFIG3 */
  510. return f->config[2];
  511. case 0x6c: /* GPMC_CONFIG4 */
  512. return f->config[3];
  513. case 0x70: /* GPMC_CONFIG5 */
  514. return f->config[4];
  515. case 0x74: /* GPMC_CONFIG6 */
  516. return f->config[5];
  517. case 0x78: /* GPMC_CONFIG7 */
  518. return f->config[6];
  519. case 0x84 ... 0x87: /* GPMC_NAND_DATA */
  520. if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
  521. return omap_nand_read(f, 0, size);
  522. }
  523. return 0;
  524. }
  525. break;
  526. case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
  527. return s->prefetch.config1;
  528. case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
  529. return s->prefetch.transfercount;
  530. case 0x1ec: /* GPMC_PREFETCH_CONTROL */
  531. return s->prefetch.startengine;
  532. case 0x1f0: /* GPMC_PREFETCH_STATUS */
  533. /* NB: The OMAP3 TRM is inconsistent about whether the GPMC
  534. * FIFOTHRESHOLDSTATUS bit should be set when
  535. * FIFOPOINTER > FIFOTHRESHOLD or when it is >= FIFOTHRESHOLD.
  536. * Apparently the underlying functional spec from which the TRM was
  537. * created states that the behaviour is ">=", and this also
  538. * makes more conceptual sense.
  539. */
  540. return (s->prefetch.fifopointer << 24) |
  541. ((s->prefetch.fifopointer >=
  542. ((s->prefetch.config1 >> 8) & 0x7f) ? 1 : 0) << 16) |
  543. s->prefetch.count;
  544. case 0x1f4: /* GPMC_ECC_CONFIG */
  545. return s->ecc_cs;
  546. case 0x1f8: /* GPMC_ECC_CONTROL */
  547. return s->ecc_ptr;
  548. case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
  549. return s->ecc_cfg;
  550. case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
  551. cs = (addr & 0x1f) >> 2;
  552. /* TODO: check correctness */
  553. return
  554. ((s->ecc[cs].cp & 0x07) << 0) |
  555. ((s->ecc[cs].cp & 0x38) << 13) |
  556. ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
  557. ((s->ecc[cs].lp[1] & 0x1ff) << 19);
  558. case 0x230: /* GPMC_TESTMODE_CTRL */
  559. return 0;
  560. case 0x234: /* GPMC_PSA_LSB */
  561. case 0x238: /* GPMC_PSA_MSB */
  562. return 0x00000000;
  563. }
  564. OMAP_BAD_REG(addr);
  565. return 0;
  566. }
  567. static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
  568. uint64_t value, unsigned size)
  569. {
  570. struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
  571. int cs;
  572. struct omap_gpmc_cs_file_s *f;
  573. if (size != 4 && gpmc_wordaccess_only(addr)) {
  574. return omap_badwidth_write32(opaque, addr, value);
  575. }
  576. switch (addr) {
  577. case 0x000: /* GPMC_REVISION */
  578. case 0x014: /* GPMC_SYSSTATUS */
  579. case 0x054: /* GPMC_STATUS */
  580. case 0x1f0: /* GPMC_PREFETCH_STATUS */
  581. case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
  582. case 0x234: /* GPMC_PSA_LSB */
  583. case 0x238: /* GPMC_PSA_MSB */
  584. OMAP_RO_REG(addr);
  585. break;
  586. case 0x010: /* GPMC_SYSCONFIG */
  587. if ((value >> 3) == 0x3)
  588. fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
  589. __FUNCTION__, value >> 3);
  590. if (value & 2)
  591. omap_gpmc_reset(s);
  592. s->sysconfig = value & 0x19;
  593. break;
  594. case 0x018: /* GPMC_IRQSTATUS */
  595. s->irqst &= ~value;
  596. omap_gpmc_int_update(s);
  597. break;
  598. case 0x01c: /* GPMC_IRQENABLE */
  599. s->irqen = value & 0xf03;
  600. omap_gpmc_int_update(s);
  601. break;
  602. case 0x040: /* GPMC_TIMEOUT_CONTROL */
  603. s->timeout = value & 0x1ff1;
  604. break;
  605. case 0x044: /* GPMC_ERR_ADDRESS */
  606. case 0x048: /* GPMC_ERR_TYPE */
  607. break;
  608. case 0x050: /* GPMC_CONFIG */
  609. s->config = value & 0xf13;
  610. break;
  611. case 0x060 ... 0x1d4:
  612. cs = (addr - 0x060) / 0x30;
  613. addr -= cs * 0x30;
  614. f = s->cs_file + cs;
  615. switch (addr) {
  616. case 0x60: /* GPMC_CONFIG1 */
  617. f->config[0] = value & 0xffef3e13;
  618. break;
  619. case 0x64: /* GPMC_CONFIG2 */
  620. f->config[1] = value & 0x001f1f8f;
  621. break;
  622. case 0x68: /* GPMC_CONFIG3 */
  623. f->config[2] = value & 0x001f1f8f;
  624. break;
  625. case 0x6c: /* GPMC_CONFIG4 */
  626. f->config[3] = value & 0x1f8f1f8f;
  627. break;
  628. case 0x70: /* GPMC_CONFIG5 */
  629. f->config[4] = value & 0x0f1f1f1f;
  630. break;
  631. case 0x74: /* GPMC_CONFIG6 */
  632. f->config[5] = value & 0x00000fcf;
  633. break;
  634. case 0x78: /* GPMC_CONFIG7 */
  635. if ((f->config[6] ^ value) & 0xf7f) {
  636. omap_gpmc_cs_unmap(s, cs);
  637. f->config[6] = value & 0x00000f7f;
  638. omap_gpmc_cs_map(s, cs);
  639. }
  640. break;
  641. case 0x7c ... 0x7f: /* GPMC_NAND_COMMAND */
  642. if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
  643. nand_setpins(f->dev, 1, 0, 0, 1, 0); /* CLE */
  644. omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
  645. }
  646. break;
  647. case 0x80 ... 0x83: /* GPMC_NAND_ADDRESS */
  648. if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
  649. nand_setpins(f->dev, 0, 1, 0, 1, 0); /* ALE */
  650. omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
  651. }
  652. break;
  653. case 0x84 ... 0x87: /* GPMC_NAND_DATA */
  654. if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
  655. omap_nand_write(f, 0, value, size);
  656. }
  657. break;
  658. default:
  659. goto bad_reg;
  660. }
  661. break;
  662. case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
  663. if (!s->prefetch.startengine) {
  664. uint32_t oldconfig1 = s->prefetch.config1;
  665. uint32_t changed;
  666. s->prefetch.config1 = value & 0x7f8f7fbf;
  667. changed = oldconfig1 ^ s->prefetch.config1;
  668. if (changed & (0x80 | 0x7000000)) {
  669. /* Turning the engine on or off, or mapping it somewhere else.
  670. * cs_map() and cs_unmap() check the prefetch config and
  671. * overall CSVALID bits, so it is sufficient to unmap-and-map
  672. * both the old cs and the new one.
  673. */
  674. int oldcs = prefetch_cs(oldconfig1);
  675. int newcs = prefetch_cs(s->prefetch.config1);
  676. omap_gpmc_cs_unmap(s, oldcs);
  677. omap_gpmc_cs_map(s, oldcs);
  678. if (newcs != oldcs) {
  679. omap_gpmc_cs_unmap(s, newcs);
  680. omap_gpmc_cs_map(s, newcs);
  681. }
  682. }
  683. }
  684. break;
  685. case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
  686. if (!s->prefetch.startengine) {
  687. s->prefetch.transfercount = value & 0x3fff;
  688. }
  689. break;
  690. case 0x1ec: /* GPMC_PREFETCH_CONTROL */
  691. if (s->prefetch.startengine != (value & 1)) {
  692. s->prefetch.startengine = value & 1;
  693. if (s->prefetch.startengine) {
  694. /* Prefetch engine start */
  695. s->prefetch.count = s->prefetch.transfercount;
  696. if (s->prefetch.config1 & 1) {
  697. /* Write */
  698. s->prefetch.fifopointer = 64;
  699. } else {
  700. /* Read */
  701. s->prefetch.fifopointer = 0;
  702. fill_prefetch_fifo(s);
  703. }
  704. } else {
  705. /* Prefetch engine forcibly stopped. The TRM
  706. * doesn't define the behaviour if you do this.
  707. * We clear the prefetch count, which means that
  708. * we permit no more writes, and don't read any
  709. * more data from NAND. The CPU can still drain
  710. * the FIFO of unread data.
  711. */
  712. s->prefetch.count = 0;
  713. }
  714. omap_gpmc_int_update(s);
  715. }
  716. break;
  717. case 0x1f4: /* GPMC_ECC_CONFIG */
  718. s->ecc_cs = 0x8f;
  719. break;
  720. case 0x1f8: /* GPMC_ECC_CONTROL */
  721. if (value & (1 << 8))
  722. for (cs = 0; cs < 9; cs ++)
  723. ecc_reset(&s->ecc[cs]);
  724. s->ecc_ptr = value & 0xf;
  725. if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
  726. s->ecc_ptr = 0;
  727. s->ecc_cs &= ~1;
  728. }
  729. break;
  730. case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
  731. s->ecc_cfg = value & 0x3fcff1ff;
  732. break;
  733. case 0x230: /* GPMC_TESTMODE_CTRL */
  734. if (value & 7)
  735. fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
  736. break;
  737. default:
  738. bad_reg:
  739. OMAP_BAD_REG(addr);
  740. return;
  741. }
  742. }
  743. static const MemoryRegionOps omap_gpmc_ops = {
  744. .read = omap_gpmc_read,
  745. .write = omap_gpmc_write,
  746. .endianness = DEVICE_NATIVE_ENDIAN,
  747. };
  748. struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
  749. target_phys_addr_t base,
  750. qemu_irq irq, qemu_irq drq)
  751. {
  752. int cs;
  753. struct omap_gpmc_s *s = (struct omap_gpmc_s *)
  754. g_malloc0(sizeof(struct omap_gpmc_s));
  755. memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
  756. memory_region_add_subregion(get_system_memory(), base, &s->iomem);
  757. s->irq = irq;
  758. s->drq = drq;
  759. s->accept_256 = cpu_is_omap3630(mpu);
  760. s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
  761. s->lastirq = 0;
  762. omap_gpmc_reset(s);
  763. /* We have to register a different IO memory handler for each
  764. * chip select region in case a NAND device is mapped there. We
  765. * make the region the worst-case size of 256MB and rely on the
  766. * container memory region in cs_map to chop it down to the actual
  767. * guest-requested size.
  768. */
  769. for (cs = 0; cs < 8; cs++) {
  770. memory_region_init_io(&s->cs_file[cs].nandiomem,
  771. &omap_nand_ops,
  772. &s->cs_file[cs],
  773. "omap-nand",
  774. 256 * 1024 * 1024);
  775. }
  776. memory_region_init_io(&s->prefetch.iomem, &omap_prefetch_ops, s,
  777. "omap-gpmc-prefetch", 256 * 1024 * 1024);
  778. return s;
  779. }
  780. void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem)
  781. {
  782. struct omap_gpmc_cs_file_s *f;
  783. assert(iomem);
  784. if (cs < 0 || cs >= 8) {
  785. fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
  786. exit(-1);
  787. }
  788. f = &s->cs_file[cs];
  789. omap_gpmc_cs_unmap(s, cs);
  790. f->config[0] &= ~(0xf << 10);
  791. f->iomem = iomem;
  792. omap_gpmc_cs_map(s, cs);
  793. }
  794. void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand)
  795. {
  796. struct omap_gpmc_cs_file_s *f;
  797. assert(nand);
  798. if (cs < 0 || cs >= 8) {
  799. fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
  800. exit(-1);
  801. }
  802. f = &s->cs_file[cs];
  803. omap_gpmc_cs_unmap(s, cs);
  804. f->config[0] &= ~(0xf << 10);
  805. f->config[0] |= (OMAP_GPMC_NAND << 10);
  806. f->dev = nand;
  807. if (nand_getbuswidth(f->dev) == 16) {
  808. f->config[0] |= OMAP_GPMC_16BIT << 12;
  809. }
  810. omap_gpmc_cs_map(s, cs);
  811. }