esp.c 20 KB

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  1. /*
  2. * QEMU ESP/NCR53C9x emulation
  3. *
  4. * Copyright (c) 2005-2006 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "sysbus.h"
  25. #include "scsi.h"
  26. #include "esp.h"
  27. #include "trace.h"
  28. /*
  29. * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  30. * also produced as NCR89C100. See
  31. * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  32. * and
  33. * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  34. */
  35. #define ESP_ERROR(fmt, ...) \
  36. do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  37. #define ESP_REGS 16
  38. #define TI_BUFSZ 16
  39. typedef struct ESPState ESPState;
  40. struct ESPState {
  41. SysBusDevice busdev;
  42. uint8_t rregs[ESP_REGS];
  43. uint8_t wregs[ESP_REGS];
  44. qemu_irq irq;
  45. uint32_t it_shift;
  46. int32_t ti_size;
  47. uint32_t ti_rptr, ti_wptr;
  48. uint32_t status;
  49. uint32_t dma;
  50. uint8_t ti_buf[TI_BUFSZ];
  51. SCSIBus bus;
  52. SCSIDevice *current_dev;
  53. SCSIRequest *current_req;
  54. uint8_t cmdbuf[TI_BUFSZ];
  55. uint32_t cmdlen;
  56. uint32_t do_cmd;
  57. /* The amount of data left in the current DMA transfer. */
  58. uint32_t dma_left;
  59. /* The size of the current DMA transfer. Zero if no transfer is in
  60. progress. */
  61. uint32_t dma_counter;
  62. int dma_enabled;
  63. uint32_t async_len;
  64. uint8_t *async_buf;
  65. ESPDMAMemoryReadWriteFunc dma_memory_read;
  66. ESPDMAMemoryReadWriteFunc dma_memory_write;
  67. void *dma_opaque;
  68. void (*dma_cb)(ESPState *s);
  69. };
  70. #define ESP_TCLO 0x0
  71. #define ESP_TCMID 0x1
  72. #define ESP_FIFO 0x2
  73. #define ESP_CMD 0x3
  74. #define ESP_RSTAT 0x4
  75. #define ESP_WBUSID 0x4
  76. #define ESP_RINTR 0x5
  77. #define ESP_WSEL 0x5
  78. #define ESP_RSEQ 0x6
  79. #define ESP_WSYNTP 0x6
  80. #define ESP_RFLAGS 0x7
  81. #define ESP_WSYNO 0x7
  82. #define ESP_CFG1 0x8
  83. #define ESP_RRES1 0x9
  84. #define ESP_WCCF 0x9
  85. #define ESP_RRES2 0xa
  86. #define ESP_WTEST 0xa
  87. #define ESP_CFG2 0xb
  88. #define ESP_CFG3 0xc
  89. #define ESP_RES3 0xd
  90. #define ESP_TCHI 0xe
  91. #define ESP_RES4 0xf
  92. #define CMD_DMA 0x80
  93. #define CMD_CMD 0x7f
  94. #define CMD_NOP 0x00
  95. #define CMD_FLUSH 0x01
  96. #define CMD_RESET 0x02
  97. #define CMD_BUSRESET 0x03
  98. #define CMD_TI 0x10
  99. #define CMD_ICCS 0x11
  100. #define CMD_MSGACC 0x12
  101. #define CMD_PAD 0x18
  102. #define CMD_SATN 0x1a
  103. #define CMD_SEL 0x41
  104. #define CMD_SELATN 0x42
  105. #define CMD_SELATNS 0x43
  106. #define CMD_ENSEL 0x44
  107. #define STAT_DO 0x00
  108. #define STAT_DI 0x01
  109. #define STAT_CD 0x02
  110. #define STAT_ST 0x03
  111. #define STAT_MO 0x06
  112. #define STAT_MI 0x07
  113. #define STAT_PIO_MASK 0x06
  114. #define STAT_TC 0x10
  115. #define STAT_PE 0x20
  116. #define STAT_GE 0x40
  117. #define STAT_INT 0x80
  118. #define BUSID_DID 0x07
  119. #define INTR_FC 0x08
  120. #define INTR_BS 0x10
  121. #define INTR_DC 0x20
  122. #define INTR_RST 0x80
  123. #define SEQ_0 0x0
  124. #define SEQ_CD 0x4
  125. #define CFG1_RESREPT 0x40
  126. #define TCHI_FAS100A 0x4
  127. static void esp_raise_irq(ESPState *s)
  128. {
  129. if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  130. s->rregs[ESP_RSTAT] |= STAT_INT;
  131. qemu_irq_raise(s->irq);
  132. trace_esp_raise_irq();
  133. }
  134. }
  135. static void esp_lower_irq(ESPState *s)
  136. {
  137. if (s->rregs[ESP_RSTAT] & STAT_INT) {
  138. s->rregs[ESP_RSTAT] &= ~STAT_INT;
  139. qemu_irq_lower(s->irq);
  140. trace_esp_lower_irq();
  141. }
  142. }
  143. static void esp_dma_enable(void *opaque, int irq, int level)
  144. {
  145. DeviceState *d = opaque;
  146. ESPState *s = container_of(d, ESPState, busdev.qdev);
  147. if (level) {
  148. s->dma_enabled = 1;
  149. trace_esp_dma_enable();
  150. if (s->dma_cb) {
  151. s->dma_cb(s);
  152. s->dma_cb = NULL;
  153. }
  154. } else {
  155. trace_esp_dma_disable();
  156. s->dma_enabled = 0;
  157. }
  158. }
  159. static void esp_request_cancelled(SCSIRequest *req)
  160. {
  161. ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
  162. if (req == s->current_req) {
  163. scsi_req_unref(s->current_req);
  164. s->current_req = NULL;
  165. s->current_dev = NULL;
  166. }
  167. }
  168. static uint32_t get_cmd(ESPState *s, uint8_t *buf)
  169. {
  170. uint32_t dmalen;
  171. int target;
  172. target = s->wregs[ESP_WBUSID] & BUSID_DID;
  173. if (s->dma) {
  174. dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
  175. s->dma_memory_read(s->dma_opaque, buf, dmalen);
  176. } else {
  177. dmalen = s->ti_size;
  178. memcpy(buf, s->ti_buf, dmalen);
  179. buf[0] = buf[2] >> 5;
  180. }
  181. trace_esp_get_cmd(dmalen, target);
  182. s->ti_size = 0;
  183. s->ti_rptr = 0;
  184. s->ti_wptr = 0;
  185. if (s->current_req) {
  186. /* Started a new command before the old one finished. Cancel it. */
  187. scsi_req_cancel(s->current_req);
  188. s->async_len = 0;
  189. }
  190. s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
  191. if (!s->current_dev) {
  192. // No such drive
  193. s->rregs[ESP_RSTAT] = 0;
  194. s->rregs[ESP_RINTR] = INTR_DC;
  195. s->rregs[ESP_RSEQ] = SEQ_0;
  196. esp_raise_irq(s);
  197. return 0;
  198. }
  199. return dmalen;
  200. }
  201. static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
  202. {
  203. int32_t datalen;
  204. int lun;
  205. SCSIDevice *current_lun;
  206. trace_esp_do_busid_cmd(busid);
  207. lun = busid & 7;
  208. current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
  209. s->current_req = scsi_req_new(current_lun, 0, lun, buf, NULL);
  210. datalen = scsi_req_enqueue(s->current_req);
  211. s->ti_size = datalen;
  212. if (datalen != 0) {
  213. s->rregs[ESP_RSTAT] = STAT_TC;
  214. s->dma_left = 0;
  215. s->dma_counter = 0;
  216. if (datalen > 0) {
  217. s->rregs[ESP_RSTAT] |= STAT_DI;
  218. } else {
  219. s->rregs[ESP_RSTAT] |= STAT_DO;
  220. }
  221. scsi_req_continue(s->current_req);
  222. }
  223. s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
  224. s->rregs[ESP_RSEQ] = SEQ_CD;
  225. esp_raise_irq(s);
  226. }
  227. static void do_cmd(ESPState *s, uint8_t *buf)
  228. {
  229. uint8_t busid = buf[0];
  230. do_busid_cmd(s, &buf[1], busid);
  231. }
  232. static void handle_satn(ESPState *s)
  233. {
  234. uint8_t buf[32];
  235. int len;
  236. if (!s->dma_enabled) {
  237. s->dma_cb = handle_satn;
  238. return;
  239. }
  240. len = get_cmd(s, buf);
  241. if (len)
  242. do_cmd(s, buf);
  243. }
  244. static void handle_s_without_atn(ESPState *s)
  245. {
  246. uint8_t buf[32];
  247. int len;
  248. if (!s->dma_enabled) {
  249. s->dma_cb = handle_s_without_atn;
  250. return;
  251. }
  252. len = get_cmd(s, buf);
  253. if (len) {
  254. do_busid_cmd(s, buf, 0);
  255. }
  256. }
  257. static void handle_satn_stop(ESPState *s)
  258. {
  259. if (!s->dma_enabled) {
  260. s->dma_cb = handle_satn_stop;
  261. return;
  262. }
  263. s->cmdlen = get_cmd(s, s->cmdbuf);
  264. if (s->cmdlen) {
  265. trace_esp_handle_satn_stop(s->cmdlen);
  266. s->do_cmd = 1;
  267. s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
  268. s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
  269. s->rregs[ESP_RSEQ] = SEQ_CD;
  270. esp_raise_irq(s);
  271. }
  272. }
  273. static void write_response(ESPState *s)
  274. {
  275. trace_esp_write_response(s->status);
  276. s->ti_buf[0] = s->status;
  277. s->ti_buf[1] = 0;
  278. if (s->dma) {
  279. s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
  280. s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
  281. s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
  282. s->rregs[ESP_RSEQ] = SEQ_CD;
  283. } else {
  284. s->ti_size = 2;
  285. s->ti_rptr = 0;
  286. s->ti_wptr = 0;
  287. s->rregs[ESP_RFLAGS] = 2;
  288. }
  289. esp_raise_irq(s);
  290. }
  291. static void esp_dma_done(ESPState *s)
  292. {
  293. s->rregs[ESP_RSTAT] |= STAT_TC;
  294. s->rregs[ESP_RINTR] = INTR_BS;
  295. s->rregs[ESP_RSEQ] = 0;
  296. s->rregs[ESP_RFLAGS] = 0;
  297. s->rregs[ESP_TCLO] = 0;
  298. s->rregs[ESP_TCMID] = 0;
  299. esp_raise_irq(s);
  300. }
  301. static void esp_do_dma(ESPState *s)
  302. {
  303. uint32_t len;
  304. int to_device;
  305. to_device = (s->ti_size < 0);
  306. len = s->dma_left;
  307. if (s->do_cmd) {
  308. trace_esp_do_dma(s->cmdlen, len);
  309. s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
  310. s->ti_size = 0;
  311. s->cmdlen = 0;
  312. s->do_cmd = 0;
  313. do_cmd(s, s->cmdbuf);
  314. return;
  315. }
  316. if (s->async_len == 0) {
  317. /* Defer until data is available. */
  318. return;
  319. }
  320. if (len > s->async_len) {
  321. len = s->async_len;
  322. }
  323. if (to_device) {
  324. s->dma_memory_read(s->dma_opaque, s->async_buf, len);
  325. } else {
  326. s->dma_memory_write(s->dma_opaque, s->async_buf, len);
  327. }
  328. s->dma_left -= len;
  329. s->async_buf += len;
  330. s->async_len -= len;
  331. if (to_device)
  332. s->ti_size += len;
  333. else
  334. s->ti_size -= len;
  335. if (s->async_len == 0) {
  336. scsi_req_continue(s->current_req);
  337. /* If there is still data to be read from the device then
  338. complete the DMA operation immediately. Otherwise defer
  339. until the scsi layer has completed. */
  340. if (to_device || s->dma_left != 0 || s->ti_size == 0) {
  341. return;
  342. }
  343. }
  344. /* Partially filled a scsi buffer. Complete immediately. */
  345. esp_dma_done(s);
  346. }
  347. static void esp_command_complete(SCSIRequest *req, uint32_t status)
  348. {
  349. ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
  350. trace_esp_command_complete();
  351. if (s->ti_size != 0) {
  352. trace_esp_command_complete_unexpected();
  353. }
  354. s->ti_size = 0;
  355. s->dma_left = 0;
  356. s->async_len = 0;
  357. if (status) {
  358. trace_esp_command_complete_fail();
  359. }
  360. s->status = status;
  361. s->rregs[ESP_RSTAT] = STAT_ST;
  362. esp_dma_done(s);
  363. if (s->current_req) {
  364. scsi_req_unref(s->current_req);
  365. s->current_req = NULL;
  366. s->current_dev = NULL;
  367. }
  368. }
  369. static void esp_transfer_data(SCSIRequest *req, uint32_t len)
  370. {
  371. ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
  372. trace_esp_transfer_data(s->dma_left, s->ti_size);
  373. s->async_len = len;
  374. s->async_buf = scsi_req_get_buf(req);
  375. if (s->dma_left) {
  376. esp_do_dma(s);
  377. } else if (s->dma_counter != 0 && s->ti_size <= 0) {
  378. /* If this was the last part of a DMA transfer then the
  379. completion interrupt is deferred to here. */
  380. esp_dma_done(s);
  381. }
  382. }
  383. static void handle_ti(ESPState *s)
  384. {
  385. uint32_t dmalen, minlen;
  386. dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
  387. if (dmalen==0) {
  388. dmalen=0x10000;
  389. }
  390. s->dma_counter = dmalen;
  391. if (s->do_cmd)
  392. minlen = (dmalen < 32) ? dmalen : 32;
  393. else if (s->ti_size < 0)
  394. minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
  395. else
  396. minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
  397. trace_esp_handle_ti(minlen);
  398. if (s->dma) {
  399. s->dma_left = minlen;
  400. s->rregs[ESP_RSTAT] &= ~STAT_TC;
  401. esp_do_dma(s);
  402. } else if (s->do_cmd) {
  403. trace_esp_handle_ti_cmd(s->cmdlen);
  404. s->ti_size = 0;
  405. s->cmdlen = 0;
  406. s->do_cmd = 0;
  407. do_cmd(s, s->cmdbuf);
  408. return;
  409. }
  410. }
  411. static void esp_hard_reset(DeviceState *d)
  412. {
  413. ESPState *s = container_of(d, ESPState, busdev.qdev);
  414. memset(s->rregs, 0, ESP_REGS);
  415. memset(s->wregs, 0, ESP_REGS);
  416. s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
  417. s->ti_size = 0;
  418. s->ti_rptr = 0;
  419. s->ti_wptr = 0;
  420. s->dma = 0;
  421. s->do_cmd = 0;
  422. s->dma_cb = NULL;
  423. s->rregs[ESP_CFG1] = 7;
  424. }
  425. static void esp_soft_reset(DeviceState *d)
  426. {
  427. ESPState *s = container_of(d, ESPState, busdev.qdev);
  428. qemu_irq_lower(s->irq);
  429. esp_hard_reset(d);
  430. }
  431. static void parent_esp_reset(void *opaque, int irq, int level)
  432. {
  433. if (level) {
  434. esp_soft_reset(opaque);
  435. }
  436. }
  437. static void esp_gpio_demux(void *opaque, int irq, int level)
  438. {
  439. switch (irq) {
  440. case 0:
  441. parent_esp_reset(opaque, irq, level);
  442. break;
  443. case 1:
  444. esp_dma_enable(opaque, irq, level);
  445. break;
  446. }
  447. }
  448. static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
  449. {
  450. ESPState *s = opaque;
  451. uint32_t saddr, old_val;
  452. saddr = addr >> s->it_shift;
  453. trace_esp_mem_readb(saddr, s->rregs[saddr]);
  454. switch (saddr) {
  455. case ESP_FIFO:
  456. if (s->ti_size > 0) {
  457. s->ti_size--;
  458. if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
  459. /* Data out. */
  460. ESP_ERROR("PIO data read not implemented\n");
  461. s->rregs[ESP_FIFO] = 0;
  462. } else {
  463. s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
  464. }
  465. esp_raise_irq(s);
  466. }
  467. if (s->ti_size == 0) {
  468. s->ti_rptr = 0;
  469. s->ti_wptr = 0;
  470. }
  471. break;
  472. case ESP_RINTR:
  473. /* Clear sequence step, interrupt register and all status bits
  474. except TC */
  475. old_val = s->rregs[ESP_RINTR];
  476. s->rregs[ESP_RINTR] = 0;
  477. s->rregs[ESP_RSTAT] &= ~STAT_TC;
  478. s->rregs[ESP_RSEQ] = SEQ_CD;
  479. esp_lower_irq(s);
  480. return old_val;
  481. default:
  482. break;
  483. }
  484. return s->rregs[saddr];
  485. }
  486. static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  487. {
  488. ESPState *s = opaque;
  489. uint32_t saddr;
  490. saddr = addr >> s->it_shift;
  491. trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
  492. switch (saddr) {
  493. case ESP_TCLO:
  494. case ESP_TCMID:
  495. s->rregs[ESP_RSTAT] &= ~STAT_TC;
  496. break;
  497. case ESP_FIFO:
  498. if (s->do_cmd) {
  499. s->cmdbuf[s->cmdlen++] = val & 0xff;
  500. } else if (s->ti_size == TI_BUFSZ - 1) {
  501. ESP_ERROR("fifo overrun\n");
  502. } else {
  503. s->ti_size++;
  504. s->ti_buf[s->ti_wptr++] = val & 0xff;
  505. }
  506. break;
  507. case ESP_CMD:
  508. s->rregs[saddr] = val;
  509. if (val & CMD_DMA) {
  510. s->dma = 1;
  511. /* Reload DMA counter. */
  512. s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
  513. s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
  514. } else {
  515. s->dma = 0;
  516. }
  517. switch(val & CMD_CMD) {
  518. case CMD_NOP:
  519. trace_esp_mem_writeb_cmd_nop(val);
  520. break;
  521. case CMD_FLUSH:
  522. trace_esp_mem_writeb_cmd_flush(val);
  523. //s->ti_size = 0;
  524. s->rregs[ESP_RINTR] = INTR_FC;
  525. s->rregs[ESP_RSEQ] = 0;
  526. s->rregs[ESP_RFLAGS] = 0;
  527. break;
  528. case CMD_RESET:
  529. trace_esp_mem_writeb_cmd_reset(val);
  530. esp_soft_reset(&s->busdev.qdev);
  531. break;
  532. case CMD_BUSRESET:
  533. trace_esp_mem_writeb_cmd_bus_reset(val);
  534. s->rregs[ESP_RINTR] = INTR_RST;
  535. if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
  536. esp_raise_irq(s);
  537. }
  538. break;
  539. case CMD_TI:
  540. handle_ti(s);
  541. break;
  542. case CMD_ICCS:
  543. trace_esp_mem_writeb_cmd_iccs(val);
  544. write_response(s);
  545. s->rregs[ESP_RINTR] = INTR_FC;
  546. s->rregs[ESP_RSTAT] |= STAT_MI;
  547. break;
  548. case CMD_MSGACC:
  549. trace_esp_mem_writeb_cmd_msgacc(val);
  550. s->rregs[ESP_RINTR] = INTR_DC;
  551. s->rregs[ESP_RSEQ] = 0;
  552. s->rregs[ESP_RFLAGS] = 0;
  553. esp_raise_irq(s);
  554. break;
  555. case CMD_PAD:
  556. trace_esp_mem_writeb_cmd_pad(val);
  557. s->rregs[ESP_RSTAT] = STAT_TC;
  558. s->rregs[ESP_RINTR] = INTR_FC;
  559. s->rregs[ESP_RSEQ] = 0;
  560. break;
  561. case CMD_SATN:
  562. trace_esp_mem_writeb_cmd_satn(val);
  563. break;
  564. case CMD_SEL:
  565. trace_esp_mem_writeb_cmd_sel(val);
  566. handle_s_without_atn(s);
  567. break;
  568. case CMD_SELATN:
  569. trace_esp_mem_writeb_cmd_selatn(val);
  570. handle_satn(s);
  571. break;
  572. case CMD_SELATNS:
  573. trace_esp_mem_writeb_cmd_selatns(val);
  574. handle_satn_stop(s);
  575. break;
  576. case CMD_ENSEL:
  577. trace_esp_mem_writeb_cmd_ensel(val);
  578. s->rregs[ESP_RINTR] = 0;
  579. break;
  580. default:
  581. ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
  582. break;
  583. }
  584. break;
  585. case ESP_WBUSID ... ESP_WSYNO:
  586. break;
  587. case ESP_CFG1:
  588. s->rregs[saddr] = val;
  589. break;
  590. case ESP_WCCF ... ESP_WTEST:
  591. break;
  592. case ESP_CFG2 ... ESP_RES4:
  593. s->rregs[saddr] = val;
  594. break;
  595. default:
  596. ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
  597. return;
  598. }
  599. s->wregs[saddr] = val;
  600. }
  601. static CPUReadMemoryFunc * const esp_mem_read[3] = {
  602. esp_mem_readb,
  603. NULL,
  604. NULL,
  605. };
  606. static CPUWriteMemoryFunc * const esp_mem_write[3] = {
  607. esp_mem_writeb,
  608. NULL,
  609. esp_mem_writeb,
  610. };
  611. static const VMStateDescription vmstate_esp = {
  612. .name ="esp",
  613. .version_id = 3,
  614. .minimum_version_id = 3,
  615. .minimum_version_id_old = 3,
  616. .fields = (VMStateField []) {
  617. VMSTATE_BUFFER(rregs, ESPState),
  618. VMSTATE_BUFFER(wregs, ESPState),
  619. VMSTATE_INT32(ti_size, ESPState),
  620. VMSTATE_UINT32(ti_rptr, ESPState),
  621. VMSTATE_UINT32(ti_wptr, ESPState),
  622. VMSTATE_BUFFER(ti_buf, ESPState),
  623. VMSTATE_UINT32(status, ESPState),
  624. VMSTATE_UINT32(dma, ESPState),
  625. VMSTATE_BUFFER(cmdbuf, ESPState),
  626. VMSTATE_UINT32(cmdlen, ESPState),
  627. VMSTATE_UINT32(do_cmd, ESPState),
  628. VMSTATE_UINT32(dma_left, ESPState),
  629. VMSTATE_END_OF_LIST()
  630. }
  631. };
  632. void esp_init(target_phys_addr_t espaddr, int it_shift,
  633. ESPDMAMemoryReadWriteFunc dma_memory_read,
  634. ESPDMAMemoryReadWriteFunc dma_memory_write,
  635. void *dma_opaque, qemu_irq irq, qemu_irq *reset,
  636. qemu_irq *dma_enable)
  637. {
  638. DeviceState *dev;
  639. SysBusDevice *s;
  640. ESPState *esp;
  641. dev = qdev_create(NULL, "esp");
  642. esp = DO_UPCAST(ESPState, busdev.qdev, dev);
  643. esp->dma_memory_read = dma_memory_read;
  644. esp->dma_memory_write = dma_memory_write;
  645. esp->dma_opaque = dma_opaque;
  646. esp->it_shift = it_shift;
  647. /* XXX for now until rc4030 has been changed to use DMA enable signal */
  648. esp->dma_enabled = 1;
  649. qdev_init_nofail(dev);
  650. s = sysbus_from_qdev(dev);
  651. sysbus_connect_irq(s, 0, irq);
  652. sysbus_mmio_map(s, 0, espaddr);
  653. *reset = qdev_get_gpio_in(dev, 0);
  654. *dma_enable = qdev_get_gpio_in(dev, 1);
  655. }
  656. static const struct SCSIBusInfo esp_scsi_info = {
  657. .tcq = false,
  658. .max_target = ESP_MAX_DEVS,
  659. .max_lun = 7,
  660. .transfer_data = esp_transfer_data,
  661. .complete = esp_command_complete,
  662. .cancel = esp_request_cancelled
  663. };
  664. static int esp_init1(SysBusDevice *dev)
  665. {
  666. ESPState *s = FROM_SYSBUS(ESPState, dev);
  667. int esp_io_memory;
  668. sysbus_init_irq(dev, &s->irq);
  669. assert(s->it_shift != -1);
  670. esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
  671. DEVICE_NATIVE_ENDIAN);
  672. sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
  673. qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
  674. scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
  675. return scsi_bus_legacy_handle_cmdline(&s->bus);
  676. }
  677. static SysBusDeviceInfo esp_info = {
  678. .init = esp_init1,
  679. .qdev.name = "esp",
  680. .qdev.size = sizeof(ESPState),
  681. .qdev.vmsd = &vmstate_esp,
  682. .qdev.reset = esp_hard_reset,
  683. .qdev.props = (Property[]) {
  684. {.name = NULL}
  685. }
  686. };
  687. static void esp_register_devices(void)
  688. {
  689. sysbus_register_withprop(&esp_info);
  690. }
  691. device_init(esp_register_devices)