ds1225y.c 5.1 KB

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  1. /*
  2. * QEMU NVRAM emulation for DS1225Y chip
  3. *
  4. * Copyright (c) 2007-2008 Hervé Poussineau
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "sysbus.h"
  25. #include "trace.h"
  26. typedef struct {
  27. DeviceState qdev;
  28. uint32_t chip_size;
  29. char *filename;
  30. FILE *file;
  31. uint8_t *contents;
  32. } NvRamState;
  33. static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
  34. {
  35. NvRamState *s = opaque;
  36. uint32_t val;
  37. val = s->contents[addr];
  38. trace_nvram_read(addr, val);
  39. return val;
  40. }
  41. static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
  42. {
  43. uint32_t v;
  44. v = nvram_readb(opaque, addr);
  45. v |= nvram_readb(opaque, addr + 1) << 8;
  46. return v;
  47. }
  48. static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
  49. {
  50. uint32_t v;
  51. v = nvram_readb(opaque, addr);
  52. v |= nvram_readb(opaque, addr + 1) << 8;
  53. v |= nvram_readb(opaque, addr + 2) << 16;
  54. v |= nvram_readb(opaque, addr + 3) << 24;
  55. return v;
  56. }
  57. static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  58. {
  59. NvRamState *s = opaque;
  60. val &= 0xff;
  61. trace_nvram_write(addr, s->contents[addr], val);
  62. s->contents[addr] = val;
  63. if (s->file) {
  64. fseek(s->file, addr, SEEK_SET);
  65. fputc(val, s->file);
  66. fflush(s->file);
  67. }
  68. }
  69. static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  70. {
  71. nvram_writeb(opaque, addr, val & 0xff);
  72. nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
  73. }
  74. static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  75. {
  76. nvram_writeb(opaque, addr, val & 0xff);
  77. nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
  78. nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff);
  79. nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
  80. }
  81. static CPUReadMemoryFunc * const nvram_read[] = {
  82. &nvram_readb,
  83. &nvram_readw,
  84. &nvram_readl,
  85. };
  86. static CPUWriteMemoryFunc * const nvram_write[] = {
  87. &nvram_writeb,
  88. &nvram_writew,
  89. &nvram_writel,
  90. };
  91. static int nvram_post_load(void *opaque, int version_id)
  92. {
  93. NvRamState *s = opaque;
  94. /* Close file, as filename may has changed in load/store process */
  95. if (s->file) {
  96. fclose(s->file);
  97. }
  98. /* Write back nvram contents */
  99. s->file = fopen(s->filename, "wb");
  100. if (s->file) {
  101. /* Write back contents, as 'wb' mode cleaned the file */
  102. if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) {
  103. printf("nvram_post_load: short write\n");
  104. }
  105. fflush(s->file);
  106. }
  107. return 0;
  108. }
  109. static const VMStateDescription vmstate_nvram = {
  110. .name = "nvram",
  111. .version_id = 0,
  112. .minimum_version_id = 0,
  113. .minimum_version_id_old = 0,
  114. .post_load = nvram_post_load,
  115. .fields = (VMStateField[]) {
  116. VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
  117. vmstate_info_uint8, uint8_t),
  118. VMSTATE_END_OF_LIST()
  119. }
  120. };
  121. typedef struct {
  122. SysBusDevice busdev;
  123. NvRamState nvram;
  124. } SysBusNvRamState;
  125. static int nvram_sysbus_initfn(SysBusDevice *dev)
  126. {
  127. NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
  128. FILE *file;
  129. int s_io;
  130. s->contents = g_malloc0(s->chip_size);
  131. s_io = cpu_register_io_memory(nvram_read, nvram_write, s,
  132. DEVICE_NATIVE_ENDIAN);
  133. sysbus_init_mmio(dev, s->chip_size, s_io);
  134. /* Read current file */
  135. file = fopen(s->filename, "rb");
  136. if (file) {
  137. /* Read nvram contents */
  138. if (fread(s->contents, s->chip_size, 1, file) != 1) {
  139. printf("nvram_sysbus_initfn: short read\n");
  140. }
  141. fclose(file);
  142. }
  143. nvram_post_load(s, 0);
  144. return 0;
  145. }
  146. static SysBusDeviceInfo nvram_sysbus_info = {
  147. .qdev.name = "ds1225y",
  148. .qdev.size = sizeof(SysBusNvRamState),
  149. .qdev.vmsd = &vmstate_nvram,
  150. .init = nvram_sysbus_initfn,
  151. .qdev.props = (Property[]) {
  152. DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
  153. DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
  154. DEFINE_PROP_END_OF_LIST(),
  155. },
  156. };
  157. static void nvram_register(void)
  158. {
  159. sysbus_register_withprop(&nvram_sysbus_info);
  160. }
  161. device_init(nvram_register)