ac97.c 37 KB

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  1. /*
  2. * Copyright (C) 2006 InnoTek Systemberatung GmbH
  3. *
  4. * This file is part of VirtualBox Open Source Edition (OSE), as
  5. * available from http://www.virtualbox.org. This file is free software;
  6. * you can redistribute it and/or modify it under the terms of the GNU
  7. * General Public License as published by the Free Software Foundation,
  8. * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
  9. * distribution. VirtualBox OSE is distributed in the hope that it will
  10. * be useful, but WITHOUT ANY WARRANTY of any kind.
  11. *
  12. * If you received this file as part of a commercial VirtualBox
  13. * distribution, then only the terms of your commercial VirtualBox
  14. * license agreement apply instead of the previous paragraph.
  15. */
  16. #include "hw.h"
  17. #include "audiodev.h"
  18. #include "audio/audio.h"
  19. #include "pci.h"
  20. #include "dma.h"
  21. enum {
  22. AC97_Reset = 0x00,
  23. AC97_Master_Volume_Mute = 0x02,
  24. AC97_Headphone_Volume_Mute = 0x04,
  25. AC97_Master_Volume_Mono_Mute = 0x06,
  26. AC97_Master_Tone_RL = 0x08,
  27. AC97_PC_BEEP_Volume_Mute = 0x0A,
  28. AC97_Phone_Volume_Mute = 0x0C,
  29. AC97_Mic_Volume_Mute = 0x0E,
  30. AC97_Line_In_Volume_Mute = 0x10,
  31. AC97_CD_Volume_Mute = 0x12,
  32. AC97_Video_Volume_Mute = 0x14,
  33. AC97_Aux_Volume_Mute = 0x16,
  34. AC97_PCM_Out_Volume_Mute = 0x18,
  35. AC97_Record_Select = 0x1A,
  36. AC97_Record_Gain_Mute = 0x1C,
  37. AC97_Record_Gain_Mic_Mute = 0x1E,
  38. AC97_General_Purpose = 0x20,
  39. AC97_3D_Control = 0x22,
  40. AC97_AC_97_RESERVED = 0x24,
  41. AC97_Powerdown_Ctrl_Stat = 0x26,
  42. AC97_Extended_Audio_ID = 0x28,
  43. AC97_Extended_Audio_Ctrl_Stat = 0x2A,
  44. AC97_PCM_Front_DAC_Rate = 0x2C,
  45. AC97_PCM_Surround_DAC_Rate = 0x2E,
  46. AC97_PCM_LFE_DAC_Rate = 0x30,
  47. AC97_PCM_LR_ADC_Rate = 0x32,
  48. AC97_MIC_ADC_Rate = 0x34,
  49. AC97_6Ch_Vol_C_LFE_Mute = 0x36,
  50. AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
  51. AC97_Vendor_Reserved = 0x58,
  52. AC97_Vendor_ID1 = 0x7c,
  53. AC97_Vendor_ID2 = 0x7e
  54. };
  55. #define SOFT_VOLUME
  56. #define SR_FIFOE 16 /* rwc */
  57. #define SR_BCIS 8 /* rwc */
  58. #define SR_LVBCI 4 /* rwc */
  59. #define SR_CELV 2 /* ro */
  60. #define SR_DCH 1 /* ro */
  61. #define SR_VALID_MASK ((1 << 5) - 1)
  62. #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
  63. #define SR_RO_MASK (SR_DCH | SR_CELV)
  64. #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
  65. #define CR_IOCE 16 /* rw */
  66. #define CR_FEIE 8 /* rw */
  67. #define CR_LVBIE 4 /* rw */
  68. #define CR_RR 2 /* rw */
  69. #define CR_RPBM 1 /* rw */
  70. #define CR_VALID_MASK ((1 << 5) - 1)
  71. #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
  72. #define GC_WR 4 /* rw */
  73. #define GC_CR 2 /* rw */
  74. #define GC_VALID_MASK ((1 << 6) - 1)
  75. #define GS_MD3 (1<<17) /* rw */
  76. #define GS_AD3 (1<<16) /* rw */
  77. #define GS_RCS (1<<15) /* rwc */
  78. #define GS_B3S12 (1<<14) /* ro */
  79. #define GS_B2S12 (1<<13) /* ro */
  80. #define GS_B1S12 (1<<12) /* ro */
  81. #define GS_S1R1 (1<<11) /* rwc */
  82. #define GS_S0R1 (1<<10) /* rwc */
  83. #define GS_S1CR (1<<9) /* ro */
  84. #define GS_S0CR (1<<8) /* ro */
  85. #define GS_MINT (1<<7) /* ro */
  86. #define GS_POINT (1<<6) /* ro */
  87. #define GS_PIINT (1<<5) /* ro */
  88. #define GS_RSRVD ((1<<4)|(1<<3))
  89. #define GS_MOINT (1<<2) /* ro */
  90. #define GS_MIINT (1<<1) /* ro */
  91. #define GS_GSCI 1 /* rwc */
  92. #define GS_RO_MASK (GS_B3S12| \
  93. GS_B2S12| \
  94. GS_B1S12| \
  95. GS_S1CR| \
  96. GS_S0CR| \
  97. GS_MINT| \
  98. GS_POINT| \
  99. GS_PIINT| \
  100. GS_RSRVD| \
  101. GS_MOINT| \
  102. GS_MIINT)
  103. #define GS_VALID_MASK ((1 << 18) - 1)
  104. #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
  105. #define BD_IOC (1<<31)
  106. #define BD_BUP (1<<30)
  107. #define EACS_VRA 1
  108. #define EACS_VRM 8
  109. #define VOL_MASK 0x1f
  110. #define MUTE_SHIFT 15
  111. #define REC_MASK 7
  112. enum {
  113. REC_MIC = 0,
  114. REC_CD,
  115. REC_VIDEO,
  116. REC_AUX,
  117. REC_LINE_IN,
  118. REC_STEREO_MIX,
  119. REC_MONO_MIX,
  120. REC_PHONE
  121. };
  122. typedef struct BD {
  123. uint32_t addr;
  124. uint32_t ctl_len;
  125. } BD;
  126. typedef struct AC97BusMasterRegs {
  127. uint32_t bdbar; /* rw 0 */
  128. uint8_t civ; /* ro 0 */
  129. uint8_t lvi; /* rw 0 */
  130. uint16_t sr; /* rw 1 */
  131. uint16_t picb; /* ro 0 */
  132. uint8_t piv; /* ro 0 */
  133. uint8_t cr; /* rw 0 */
  134. unsigned int bd_valid;
  135. BD bd;
  136. } AC97BusMasterRegs;
  137. typedef struct AC97LinkState {
  138. PCIDevice dev;
  139. QEMUSoundCard card;
  140. uint32_t use_broken_id;
  141. uint32_t glob_cnt;
  142. uint32_t glob_sta;
  143. uint32_t cas;
  144. uint32_t last_samp;
  145. AC97BusMasterRegs bm_regs[3];
  146. uint8_t mixer_data[256];
  147. SWVoiceIn *voice_pi;
  148. SWVoiceOut *voice_po;
  149. SWVoiceIn *voice_mc;
  150. int invalid_freq[3];
  151. uint8_t silence[128];
  152. int bup_flag;
  153. MemoryRegion io_nam;
  154. MemoryRegion io_nabm;
  155. } AC97LinkState;
  156. enum {
  157. BUP_SET = 1,
  158. BUP_LAST = 2
  159. };
  160. #ifdef DEBUG_AC97
  161. #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
  162. #else
  163. #define dolog(...)
  164. #endif
  165. #define MKREGS(prefix, start) \
  166. enum { \
  167. prefix ## _BDBAR = start, \
  168. prefix ## _CIV = start + 4, \
  169. prefix ## _LVI = start + 5, \
  170. prefix ## _SR = start + 6, \
  171. prefix ## _PICB = start + 8, \
  172. prefix ## _PIV = start + 10, \
  173. prefix ## _CR = start + 11 \
  174. }
  175. enum {
  176. PI_INDEX = 0,
  177. PO_INDEX,
  178. MC_INDEX,
  179. LAST_INDEX
  180. };
  181. MKREGS (PI, PI_INDEX * 16);
  182. MKREGS (PO, PO_INDEX * 16);
  183. MKREGS (MC, MC_INDEX * 16);
  184. enum {
  185. GLOB_CNT = 0x2c,
  186. GLOB_STA = 0x30,
  187. CAS = 0x34
  188. };
  189. #define GET_BM(index) (((index) >> 4) & 3)
  190. static void po_callback (void *opaque, int free);
  191. static void pi_callback (void *opaque, int avail);
  192. static void mc_callback (void *opaque, int avail);
  193. static void warm_reset (AC97LinkState *s)
  194. {
  195. (void) s;
  196. }
  197. static void cold_reset (AC97LinkState * s)
  198. {
  199. (void) s;
  200. }
  201. static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
  202. {
  203. uint8_t b[8];
  204. pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
  205. r->bd_valid = 1;
  206. r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
  207. r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
  208. r->picb = r->bd.ctl_len & 0xffff;
  209. dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
  210. r->civ, r->bd.addr, r->bd.ctl_len >> 16,
  211. r->bd.ctl_len & 0xffff,
  212. (r->bd.ctl_len & 0xffff) << 1);
  213. }
  214. static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
  215. {
  216. int event = 0;
  217. int level = 0;
  218. uint32_t new_mask = new_sr & SR_INT_MASK;
  219. uint32_t old_mask = r->sr & SR_INT_MASK;
  220. uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
  221. if (new_mask ^ old_mask) {
  222. /** @todo is IRQ deasserted when only one of status bits is cleared? */
  223. if (!new_mask) {
  224. event = 1;
  225. level = 0;
  226. }
  227. else {
  228. if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
  229. event = 1;
  230. level = 1;
  231. }
  232. if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
  233. event = 1;
  234. level = 1;
  235. }
  236. }
  237. }
  238. r->sr = new_sr;
  239. dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
  240. r->sr & SR_BCIS, r->sr & SR_LVBCI,
  241. r->sr,
  242. event, level);
  243. if (!event)
  244. return;
  245. if (level) {
  246. s->glob_sta |= masks[r - s->bm_regs];
  247. dolog ("set irq level=1\n");
  248. qemu_set_irq (s->dev.irq[0], 1);
  249. }
  250. else {
  251. s->glob_sta &= ~masks[r - s->bm_regs];
  252. dolog ("set irq level=0\n");
  253. qemu_set_irq (s->dev.irq[0], 0);
  254. }
  255. }
  256. static void voice_set_active (AC97LinkState *s, int bm_index, int on)
  257. {
  258. switch (bm_index) {
  259. case PI_INDEX:
  260. AUD_set_active_in (s->voice_pi, on);
  261. break;
  262. case PO_INDEX:
  263. AUD_set_active_out (s->voice_po, on);
  264. break;
  265. case MC_INDEX:
  266. AUD_set_active_in (s->voice_mc, on);
  267. break;
  268. default:
  269. AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
  270. break;
  271. }
  272. }
  273. static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
  274. {
  275. dolog ("reset_bm_regs\n");
  276. r->bdbar = 0;
  277. r->civ = 0;
  278. r->lvi = 0;
  279. /** todo do we need to do that? */
  280. update_sr (s, r, SR_DCH);
  281. r->picb = 0;
  282. r->piv = 0;
  283. r->cr = r->cr & CR_DONT_CLEAR_MASK;
  284. r->bd_valid = 0;
  285. voice_set_active (s, r - s->bm_regs, 0);
  286. memset (s->silence, 0, sizeof (s->silence));
  287. }
  288. static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
  289. {
  290. if (i + 2 > sizeof (s->mixer_data)) {
  291. dolog ("mixer_store: index %d out of bounds %zd\n",
  292. i, sizeof (s->mixer_data));
  293. return;
  294. }
  295. s->mixer_data[i + 0] = v & 0xff;
  296. s->mixer_data[i + 1] = v >> 8;
  297. }
  298. static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
  299. {
  300. uint16_t val = 0xffff;
  301. if (i + 2 > sizeof (s->mixer_data)) {
  302. dolog ("mixer_store: index %d out of bounds %zd\n",
  303. i, sizeof (s->mixer_data));
  304. }
  305. else {
  306. val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
  307. }
  308. return val;
  309. }
  310. static void open_voice (AC97LinkState *s, int index, int freq)
  311. {
  312. struct audsettings as;
  313. as.freq = freq;
  314. as.nchannels = 2;
  315. as.fmt = AUD_FMT_S16;
  316. as.endianness = 0;
  317. if (freq > 0) {
  318. s->invalid_freq[index] = 0;
  319. switch (index) {
  320. case PI_INDEX:
  321. s->voice_pi = AUD_open_in (
  322. &s->card,
  323. s->voice_pi,
  324. "ac97.pi",
  325. s,
  326. pi_callback,
  327. &as
  328. );
  329. break;
  330. case PO_INDEX:
  331. s->voice_po = AUD_open_out (
  332. &s->card,
  333. s->voice_po,
  334. "ac97.po",
  335. s,
  336. po_callback,
  337. &as
  338. );
  339. break;
  340. case MC_INDEX:
  341. s->voice_mc = AUD_open_in (
  342. &s->card,
  343. s->voice_mc,
  344. "ac97.mc",
  345. s,
  346. mc_callback,
  347. &as
  348. );
  349. break;
  350. }
  351. }
  352. else {
  353. s->invalid_freq[index] = freq;
  354. switch (index) {
  355. case PI_INDEX:
  356. AUD_close_in (&s->card, s->voice_pi);
  357. s->voice_pi = NULL;
  358. break;
  359. case PO_INDEX:
  360. AUD_close_out (&s->card, s->voice_po);
  361. s->voice_po = NULL;
  362. break;
  363. case MC_INDEX:
  364. AUD_close_in (&s->card, s->voice_mc);
  365. s->voice_mc = NULL;
  366. break;
  367. }
  368. }
  369. }
  370. static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
  371. {
  372. uint16_t freq;
  373. freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
  374. open_voice (s, PI_INDEX, freq);
  375. AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
  376. freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
  377. open_voice (s, PO_INDEX, freq);
  378. AUD_set_active_out (s->voice_po, active[PO_INDEX]);
  379. freq = mixer_load (s, AC97_MIC_ADC_Rate);
  380. open_voice (s, MC_INDEX, freq);
  381. AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
  382. }
  383. #ifdef USE_MIXER
  384. static void set_volume (AC97LinkState *s, int index,
  385. audmixerctl_t mt, uint32_t val)
  386. {
  387. int mute = (val >> MUTE_SHIFT) & 1;
  388. uint8_t rvol = VOL_MASK - (val & VOL_MASK);
  389. uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
  390. rvol = 255 * rvol / VOL_MASK;
  391. lvol = 255 * lvol / VOL_MASK;
  392. #ifdef SOFT_VOLUME
  393. if (index == AC97_Master_Volume_Mute) {
  394. AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
  395. }
  396. else {
  397. AUD_set_volume (mt, &mute, &lvol, &rvol);
  398. }
  399. #else
  400. AUD_set_volume (mt, &mute, &lvol, &rvol);
  401. #endif
  402. rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
  403. lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
  404. mixer_store (s, index, val);
  405. }
  406. static audrecsource_t ac97_to_aud_record_source (uint8_t i)
  407. {
  408. switch (i) {
  409. case REC_MIC:
  410. return AUD_REC_MIC;
  411. case REC_CD:
  412. return AUD_REC_CD;
  413. case REC_VIDEO:
  414. return AUD_REC_VIDEO;
  415. case REC_AUX:
  416. return AUD_REC_AUX;
  417. case REC_LINE_IN:
  418. return AUD_REC_LINE_IN;
  419. case REC_PHONE:
  420. return AUD_REC_PHONE;
  421. default:
  422. dolog ("Unknown record source %d, using MIC\n", i);
  423. return AUD_REC_MIC;
  424. }
  425. }
  426. static uint8_t aud_to_ac97_record_source (audrecsource_t rs)
  427. {
  428. switch (rs) {
  429. case AUD_REC_MIC:
  430. return REC_MIC;
  431. case AUD_REC_CD:
  432. return REC_CD;
  433. case AUD_REC_VIDEO:
  434. return REC_VIDEO;
  435. case AUD_REC_AUX:
  436. return REC_AUX;
  437. case AUD_REC_LINE_IN:
  438. return REC_LINE_IN;
  439. case AUD_REC_PHONE:
  440. return REC_PHONE;
  441. default:
  442. dolog ("Unknown audio recording source %d using MIC\n", rs);
  443. return REC_MIC;
  444. }
  445. }
  446. static void record_select (AC97LinkState *s, uint32_t val)
  447. {
  448. uint8_t rs = val & REC_MASK;
  449. uint8_t ls = (val >> 8) & REC_MASK;
  450. audrecsource_t ars = ac97_to_aud_record_source (rs);
  451. audrecsource_t als = ac97_to_aud_record_source (ls);
  452. AUD_set_record_source (&als, &ars);
  453. rs = aud_to_ac97_record_source (ars);
  454. ls = aud_to_ac97_record_source (als);
  455. mixer_store (s, AC97_Record_Select, rs | (ls << 8));
  456. }
  457. #endif
  458. static void mixer_reset (AC97LinkState *s)
  459. {
  460. uint8_t active[LAST_INDEX];
  461. dolog ("mixer_reset\n");
  462. memset (s->mixer_data, 0, sizeof (s->mixer_data));
  463. memset (active, 0, sizeof (active));
  464. mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
  465. mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x8000);
  466. mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
  467. mixer_store (s, AC97_Phone_Volume_Mute , 0x8008);
  468. mixer_store (s, AC97_Mic_Volume_Mute , 0x8008);
  469. mixer_store (s, AC97_CD_Volume_Mute , 0x8808);
  470. mixer_store (s, AC97_Aux_Volume_Mute , 0x8808);
  471. mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x8000);
  472. mixer_store (s, AC97_General_Purpose , 0x0000);
  473. mixer_store (s, AC97_3D_Control , 0x0000);
  474. mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
  475. /*
  476. * Sigmatel 9700 (STAC9700)
  477. */
  478. mixer_store (s, AC97_Vendor_ID1 , 0x8384);
  479. mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
  480. mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
  481. mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
  482. mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
  483. mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
  484. mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
  485. mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
  486. mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
  487. #ifdef USE_MIXER
  488. record_select (s, 0);
  489. set_volume (s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME , 0x8000);
  490. set_volume (s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM , 0x8808);
  491. set_volume (s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
  492. #endif
  493. reset_voices (s, active);
  494. }
  495. /**
  496. * Native audio mixer
  497. * I/O Reads
  498. */
  499. static uint32_t nam_readb (void *opaque, uint32_t addr)
  500. {
  501. AC97LinkState *s = opaque;
  502. dolog ("U nam readb %#x\n", addr);
  503. s->cas = 0;
  504. return ~0U;
  505. }
  506. static uint32_t nam_readw (void *opaque, uint32_t addr)
  507. {
  508. AC97LinkState *s = opaque;
  509. uint32_t val = ~0U;
  510. uint32_t index = addr;
  511. s->cas = 0;
  512. val = mixer_load (s, index);
  513. return val;
  514. }
  515. static uint32_t nam_readl (void *opaque, uint32_t addr)
  516. {
  517. AC97LinkState *s = opaque;
  518. dolog ("U nam readl %#x\n", addr);
  519. s->cas = 0;
  520. return ~0U;
  521. }
  522. /**
  523. * Native audio mixer
  524. * I/O Writes
  525. */
  526. static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
  527. {
  528. AC97LinkState *s = opaque;
  529. dolog ("U nam writeb %#x <- %#x\n", addr, val);
  530. s->cas = 0;
  531. }
  532. static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
  533. {
  534. AC97LinkState *s = opaque;
  535. uint32_t index = addr;
  536. s->cas = 0;
  537. switch (index) {
  538. case AC97_Reset:
  539. mixer_reset (s);
  540. break;
  541. case AC97_Powerdown_Ctrl_Stat:
  542. val &= ~0xf;
  543. val |= mixer_load (s, index) & 0xf;
  544. mixer_store (s, index, val);
  545. break;
  546. #ifdef USE_MIXER
  547. case AC97_Master_Volume_Mute:
  548. set_volume (s, index, AUD_MIXER_VOLUME, val);
  549. break;
  550. case AC97_PCM_Out_Volume_Mute:
  551. set_volume (s, index, AUD_MIXER_PCM, val);
  552. break;
  553. case AC97_Line_In_Volume_Mute:
  554. set_volume (s, index, AUD_MIXER_LINE_IN, val);
  555. break;
  556. case AC97_Record_Select:
  557. record_select (s, val);
  558. break;
  559. #endif
  560. case AC97_Vendor_ID1:
  561. case AC97_Vendor_ID2:
  562. dolog ("Attempt to write vendor ID to %#x\n", val);
  563. break;
  564. case AC97_Extended_Audio_ID:
  565. dolog ("Attempt to write extended audio ID to %#x\n", val);
  566. break;
  567. case AC97_Extended_Audio_Ctrl_Stat:
  568. if (!(val & EACS_VRA)) {
  569. mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
  570. mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
  571. open_voice (s, PI_INDEX, 48000);
  572. open_voice (s, PO_INDEX, 48000);
  573. }
  574. if (!(val & EACS_VRM)) {
  575. mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
  576. open_voice (s, MC_INDEX, 48000);
  577. }
  578. dolog ("Setting extended audio control to %#x\n", val);
  579. mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
  580. break;
  581. case AC97_PCM_Front_DAC_Rate:
  582. if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
  583. mixer_store (s, index, val);
  584. dolog ("Set front DAC rate to %d\n", val);
  585. open_voice (s, PO_INDEX, val);
  586. }
  587. else {
  588. dolog ("Attempt to set front DAC rate to %d, "
  589. "but VRA is not set\n",
  590. val);
  591. }
  592. break;
  593. case AC97_MIC_ADC_Rate:
  594. if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
  595. mixer_store (s, index, val);
  596. dolog ("Set MIC ADC rate to %d\n", val);
  597. open_voice (s, MC_INDEX, val);
  598. }
  599. else {
  600. dolog ("Attempt to set MIC ADC rate to %d, "
  601. "but VRM is not set\n",
  602. val);
  603. }
  604. break;
  605. case AC97_PCM_LR_ADC_Rate:
  606. if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
  607. mixer_store (s, index, val);
  608. dolog ("Set front LR ADC rate to %d\n", val);
  609. open_voice (s, PI_INDEX, val);
  610. }
  611. else {
  612. dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
  613. val);
  614. }
  615. break;
  616. default:
  617. dolog ("U nam writew %#x <- %#x\n", addr, val);
  618. mixer_store (s, index, val);
  619. break;
  620. }
  621. }
  622. static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
  623. {
  624. AC97LinkState *s = opaque;
  625. dolog ("U nam writel %#x <- %#x\n", addr, val);
  626. s->cas = 0;
  627. }
  628. /**
  629. * Native audio bus master
  630. * I/O Reads
  631. */
  632. static uint32_t nabm_readb (void *opaque, uint32_t addr)
  633. {
  634. AC97LinkState *s = opaque;
  635. AC97BusMasterRegs *r = NULL;
  636. uint32_t index = addr;
  637. uint32_t val = ~0U;
  638. switch (index) {
  639. case CAS:
  640. dolog ("CAS %d\n", s->cas);
  641. val = s->cas;
  642. s->cas = 1;
  643. break;
  644. case PI_CIV:
  645. case PO_CIV:
  646. case MC_CIV:
  647. r = &s->bm_regs[GET_BM (index)];
  648. val = r->civ;
  649. dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
  650. break;
  651. case PI_LVI:
  652. case PO_LVI:
  653. case MC_LVI:
  654. r = &s->bm_regs[GET_BM (index)];
  655. val = r->lvi;
  656. dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
  657. break;
  658. case PI_PIV:
  659. case PO_PIV:
  660. case MC_PIV:
  661. r = &s->bm_regs[GET_BM (index)];
  662. val = r->piv;
  663. dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
  664. break;
  665. case PI_CR:
  666. case PO_CR:
  667. case MC_CR:
  668. r = &s->bm_regs[GET_BM (index)];
  669. val = r->cr;
  670. dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
  671. break;
  672. case PI_SR:
  673. case PO_SR:
  674. case MC_SR:
  675. r = &s->bm_regs[GET_BM (index)];
  676. val = r->sr & 0xff;
  677. dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
  678. break;
  679. default:
  680. dolog ("U nabm readb %#x -> %#x\n", addr, val);
  681. break;
  682. }
  683. return val;
  684. }
  685. static uint32_t nabm_readw (void *opaque, uint32_t addr)
  686. {
  687. AC97LinkState *s = opaque;
  688. AC97BusMasterRegs *r = NULL;
  689. uint32_t index = addr;
  690. uint32_t val = ~0U;
  691. switch (index) {
  692. case PI_SR:
  693. case PO_SR:
  694. case MC_SR:
  695. r = &s->bm_regs[GET_BM (index)];
  696. val = r->sr;
  697. dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
  698. break;
  699. case PI_PICB:
  700. case PO_PICB:
  701. case MC_PICB:
  702. r = &s->bm_regs[GET_BM (index)];
  703. val = r->picb;
  704. dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
  705. break;
  706. default:
  707. dolog ("U nabm readw %#x -> %#x\n", addr, val);
  708. break;
  709. }
  710. return val;
  711. }
  712. static uint32_t nabm_readl (void *opaque, uint32_t addr)
  713. {
  714. AC97LinkState *s = opaque;
  715. AC97BusMasterRegs *r = NULL;
  716. uint32_t index = addr;
  717. uint32_t val = ~0U;
  718. switch (index) {
  719. case PI_BDBAR:
  720. case PO_BDBAR:
  721. case MC_BDBAR:
  722. r = &s->bm_regs[GET_BM (index)];
  723. val = r->bdbar;
  724. dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
  725. break;
  726. case PI_CIV:
  727. case PO_CIV:
  728. case MC_CIV:
  729. r = &s->bm_regs[GET_BM (index)];
  730. val = r->civ | (r->lvi << 8) | (r->sr << 16);
  731. dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
  732. r->civ, r->lvi, r->sr);
  733. break;
  734. case PI_PICB:
  735. case PO_PICB:
  736. case MC_PICB:
  737. r = &s->bm_regs[GET_BM (index)];
  738. val = r->picb | (r->piv << 16) | (r->cr << 24);
  739. dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
  740. val, r->picb, r->piv, r->cr);
  741. break;
  742. case GLOB_CNT:
  743. val = s->glob_cnt;
  744. dolog ("glob_cnt -> %#x\n", val);
  745. break;
  746. case GLOB_STA:
  747. val = s->glob_sta | GS_S0CR;
  748. dolog ("glob_sta -> %#x\n", val);
  749. break;
  750. default:
  751. dolog ("U nabm readl %#x -> %#x\n", addr, val);
  752. break;
  753. }
  754. return val;
  755. }
  756. /**
  757. * Native audio bus master
  758. * I/O Writes
  759. */
  760. static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
  761. {
  762. AC97LinkState *s = opaque;
  763. AC97BusMasterRegs *r = NULL;
  764. uint32_t index = addr;
  765. switch (index) {
  766. case PI_LVI:
  767. case PO_LVI:
  768. case MC_LVI:
  769. r = &s->bm_regs[GET_BM (index)];
  770. if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
  771. r->sr &= ~(SR_DCH | SR_CELV);
  772. r->civ = r->piv;
  773. r->piv = (r->piv + 1) % 32;
  774. fetch_bd (s, r);
  775. }
  776. r->lvi = val % 32;
  777. dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
  778. break;
  779. case PI_CR:
  780. case PO_CR:
  781. case MC_CR:
  782. r = &s->bm_regs[GET_BM (index)];
  783. if (val & CR_RR) {
  784. reset_bm_regs (s, r);
  785. }
  786. else {
  787. r->cr = val & CR_VALID_MASK;
  788. if (!(r->cr & CR_RPBM)) {
  789. voice_set_active (s, r - s->bm_regs, 0);
  790. r->sr |= SR_DCH;
  791. }
  792. else {
  793. r->civ = r->piv;
  794. r->piv = (r->piv + 1) % 32;
  795. fetch_bd (s, r);
  796. r->sr &= ~SR_DCH;
  797. voice_set_active (s, r - s->bm_regs, 1);
  798. }
  799. }
  800. dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
  801. break;
  802. case PI_SR:
  803. case PO_SR:
  804. case MC_SR:
  805. r = &s->bm_regs[GET_BM (index)];
  806. r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
  807. update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
  808. dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
  809. break;
  810. default:
  811. dolog ("U nabm writeb %#x <- %#x\n", addr, val);
  812. break;
  813. }
  814. }
  815. static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
  816. {
  817. AC97LinkState *s = opaque;
  818. AC97BusMasterRegs *r = NULL;
  819. uint32_t index = addr;
  820. switch (index) {
  821. case PI_SR:
  822. case PO_SR:
  823. case MC_SR:
  824. r = &s->bm_regs[GET_BM (index)];
  825. r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
  826. update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
  827. dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
  828. break;
  829. default:
  830. dolog ("U nabm writew %#x <- %#x\n", addr, val);
  831. break;
  832. }
  833. }
  834. static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
  835. {
  836. AC97LinkState *s = opaque;
  837. AC97BusMasterRegs *r = NULL;
  838. uint32_t index = addr;
  839. switch (index) {
  840. case PI_BDBAR:
  841. case PO_BDBAR:
  842. case MC_BDBAR:
  843. r = &s->bm_regs[GET_BM (index)];
  844. r->bdbar = val & ~3;
  845. dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
  846. GET_BM (index), val, r->bdbar);
  847. break;
  848. case GLOB_CNT:
  849. if (val & GC_WR)
  850. warm_reset (s);
  851. if (val & GC_CR)
  852. cold_reset (s);
  853. if (!(val & (GC_WR | GC_CR)))
  854. s->glob_cnt = val & GC_VALID_MASK;
  855. dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
  856. break;
  857. case GLOB_STA:
  858. s->glob_sta &= ~(val & GS_WCLEAR_MASK);
  859. s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
  860. dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
  861. break;
  862. default:
  863. dolog ("U nabm writel %#x <- %#x\n", addr, val);
  864. break;
  865. }
  866. }
  867. static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
  868. int max, int *stop)
  869. {
  870. uint8_t tmpbuf[4096];
  871. uint32_t addr = r->bd.addr;
  872. uint32_t temp = r->picb << 1;
  873. uint32_t written = 0;
  874. int to_copy = 0;
  875. temp = audio_MIN (temp, max);
  876. if (!temp) {
  877. *stop = 1;
  878. return 0;
  879. }
  880. while (temp) {
  881. int copied;
  882. to_copy = audio_MIN (temp, sizeof (tmpbuf));
  883. pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
  884. copied = AUD_write (s->voice_po, tmpbuf, to_copy);
  885. dolog ("write_audio max=%x to_copy=%x copied=%x\n",
  886. max, to_copy, copied);
  887. if (!copied) {
  888. *stop = 1;
  889. break;
  890. }
  891. temp -= copied;
  892. addr += copied;
  893. written += copied;
  894. }
  895. if (!temp) {
  896. if (to_copy < 4) {
  897. dolog ("whoops\n");
  898. s->last_samp = 0;
  899. }
  900. else {
  901. s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
  902. }
  903. }
  904. r->bd.addr = addr;
  905. return written;
  906. }
  907. static void write_bup (AC97LinkState *s, int elapsed)
  908. {
  909. dolog ("write_bup\n");
  910. if (!(s->bup_flag & BUP_SET)) {
  911. if (s->bup_flag & BUP_LAST) {
  912. int i;
  913. uint8_t *p = s->silence;
  914. for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
  915. *(uint32_t *) p = s->last_samp;
  916. }
  917. }
  918. else {
  919. memset (s->silence, 0, sizeof (s->silence));
  920. }
  921. s->bup_flag |= BUP_SET;
  922. }
  923. while (elapsed) {
  924. int temp = audio_MIN (elapsed, sizeof (s->silence));
  925. while (temp) {
  926. int copied = AUD_write (s->voice_po, s->silence, temp);
  927. if (!copied)
  928. return;
  929. temp -= copied;
  930. elapsed -= copied;
  931. }
  932. }
  933. }
  934. static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
  935. int max, int *stop)
  936. {
  937. uint8_t tmpbuf[4096];
  938. uint32_t addr = r->bd.addr;
  939. uint32_t temp = r->picb << 1;
  940. uint32_t nread = 0;
  941. int to_copy = 0;
  942. SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
  943. temp = audio_MIN (temp, max);
  944. if (!temp) {
  945. *stop = 1;
  946. return 0;
  947. }
  948. while (temp) {
  949. int acquired;
  950. to_copy = audio_MIN (temp, sizeof (tmpbuf));
  951. acquired = AUD_read (voice, tmpbuf, to_copy);
  952. if (!acquired) {
  953. *stop = 1;
  954. break;
  955. }
  956. pci_dma_write (&s->dev, addr, tmpbuf, acquired);
  957. temp -= acquired;
  958. addr += acquired;
  959. nread += acquired;
  960. }
  961. r->bd.addr = addr;
  962. return nread;
  963. }
  964. static void transfer_audio (AC97LinkState *s, int index, int elapsed)
  965. {
  966. AC97BusMasterRegs *r = &s->bm_regs[index];
  967. int stop = 0;
  968. if (s->invalid_freq[index]) {
  969. AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
  970. index, s->invalid_freq[index]);
  971. return;
  972. }
  973. if (r->sr & SR_DCH) {
  974. if (r->cr & CR_RPBM) {
  975. switch (index) {
  976. case PO_INDEX:
  977. write_bup (s, elapsed);
  978. break;
  979. }
  980. }
  981. return;
  982. }
  983. while ((elapsed >> 1) && !stop) {
  984. int temp;
  985. if (!r->bd_valid) {
  986. dolog ("invalid bd\n");
  987. fetch_bd (s, r);
  988. }
  989. if (!r->picb) {
  990. dolog ("fresh bd %d is empty %#x %#x\n",
  991. r->civ, r->bd.addr, r->bd.ctl_len);
  992. if (r->civ == r->lvi) {
  993. r->sr |= SR_DCH; /* CELV? */
  994. s->bup_flag = 0;
  995. break;
  996. }
  997. r->sr &= ~SR_CELV;
  998. r->civ = r->piv;
  999. r->piv = (r->piv + 1) % 32;
  1000. fetch_bd (s, r);
  1001. return;
  1002. }
  1003. switch (index) {
  1004. case PO_INDEX:
  1005. temp = write_audio (s, r, elapsed, &stop);
  1006. elapsed -= temp;
  1007. r->picb -= (temp >> 1);
  1008. break;
  1009. case PI_INDEX:
  1010. case MC_INDEX:
  1011. temp = read_audio (s, r, elapsed, &stop);
  1012. elapsed -= temp;
  1013. r->picb -= (temp >> 1);
  1014. break;
  1015. }
  1016. if (!r->picb) {
  1017. uint32_t new_sr = r->sr & ~SR_CELV;
  1018. if (r->bd.ctl_len & BD_IOC) {
  1019. new_sr |= SR_BCIS;
  1020. }
  1021. if (r->civ == r->lvi) {
  1022. dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
  1023. new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
  1024. stop = 1;
  1025. s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
  1026. }
  1027. else {
  1028. r->civ = r->piv;
  1029. r->piv = (r->piv + 1) % 32;
  1030. fetch_bd (s, r);
  1031. }
  1032. update_sr (s, r, new_sr);
  1033. }
  1034. }
  1035. }
  1036. static void pi_callback (void *opaque, int avail)
  1037. {
  1038. transfer_audio (opaque, PI_INDEX, avail);
  1039. }
  1040. static void mc_callback (void *opaque, int avail)
  1041. {
  1042. transfer_audio (opaque, MC_INDEX, avail);
  1043. }
  1044. static void po_callback (void *opaque, int free)
  1045. {
  1046. transfer_audio (opaque, PO_INDEX, free);
  1047. }
  1048. static const VMStateDescription vmstate_ac97_bm_regs = {
  1049. .name = "ac97_bm_regs",
  1050. .version_id = 1,
  1051. .minimum_version_id = 1,
  1052. .minimum_version_id_old = 1,
  1053. .fields = (VMStateField []) {
  1054. VMSTATE_UINT32(bdbar, AC97BusMasterRegs),
  1055. VMSTATE_UINT8(civ, AC97BusMasterRegs),
  1056. VMSTATE_UINT8(lvi, AC97BusMasterRegs),
  1057. VMSTATE_UINT16(sr, AC97BusMasterRegs),
  1058. VMSTATE_UINT16(picb, AC97BusMasterRegs),
  1059. VMSTATE_UINT8(piv, AC97BusMasterRegs),
  1060. VMSTATE_UINT8(cr, AC97BusMasterRegs),
  1061. VMSTATE_UINT32(bd_valid, AC97BusMasterRegs),
  1062. VMSTATE_UINT32(bd.addr, AC97BusMasterRegs),
  1063. VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs),
  1064. VMSTATE_END_OF_LIST()
  1065. }
  1066. };
  1067. static int ac97_post_load (void *opaque, int version_id)
  1068. {
  1069. uint8_t active[LAST_INDEX];
  1070. AC97LinkState *s = opaque;
  1071. #ifdef USE_MIXER
  1072. record_select (s, mixer_load (s, AC97_Record_Select));
  1073. #define V_(a, b) set_volume (s, a, b, mixer_load (s, a))
  1074. V_ (AC97_Master_Volume_Mute, AUD_MIXER_VOLUME);
  1075. V_ (AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM);
  1076. V_ (AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN);
  1077. #undef V_
  1078. #endif
  1079. active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
  1080. active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
  1081. active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
  1082. reset_voices (s, active);
  1083. s->bup_flag = 0;
  1084. s->last_samp = 0;
  1085. return 0;
  1086. }
  1087. static bool is_version_2 (void *opaque, int version_id)
  1088. {
  1089. return version_id == 2;
  1090. }
  1091. static const VMStateDescription vmstate_ac97 = {
  1092. .name = "ac97",
  1093. .version_id = 3,
  1094. .minimum_version_id = 2,
  1095. .minimum_version_id_old = 2,
  1096. .post_load = ac97_post_load,
  1097. .fields = (VMStateField []) {
  1098. VMSTATE_PCI_DEVICE(dev, AC97LinkState),
  1099. VMSTATE_UINT32(glob_cnt, AC97LinkState),
  1100. VMSTATE_UINT32(glob_sta, AC97LinkState),
  1101. VMSTATE_UINT32(cas, AC97LinkState),
  1102. VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1,
  1103. vmstate_ac97_bm_regs, AC97BusMasterRegs),
  1104. VMSTATE_BUFFER(mixer_data, AC97LinkState),
  1105. VMSTATE_UNUSED_TEST(is_version_2, 3),
  1106. VMSTATE_END_OF_LIST()
  1107. }
  1108. };
  1109. static const MemoryRegionPortio nam_portio[] = {
  1110. { 0, 256 * 1, 1, .read = nam_readb, },
  1111. { 0, 256 * 2, 2, .read = nam_readw, },
  1112. { 0, 256 * 4, 4, .read = nam_readl, },
  1113. { 0, 256 * 1, 1, .write = nam_writeb, },
  1114. { 0, 256 * 2, 2, .write = nam_writew, },
  1115. { 0, 256 * 4, 4, .write = nam_writel, },
  1116. PORTIO_END_OF_LIST(),
  1117. };
  1118. static const MemoryRegionOps ac97_io_nam_ops = {
  1119. .old_portio = nam_portio,
  1120. };
  1121. static const MemoryRegionPortio nabm_portio[] = {
  1122. { 0, 64 * 1, 1, .read = nabm_readb, },
  1123. { 0, 64 * 2, 2, .read = nabm_readw, },
  1124. { 0, 64 * 4, 4, .read = nabm_readl, },
  1125. { 0, 64 * 1, 1, .write = nabm_writeb, },
  1126. { 0, 64 * 2, 2, .write = nabm_writew, },
  1127. { 0, 64 * 4, 4, .write = nabm_writel, },
  1128. PORTIO_END_OF_LIST()
  1129. };
  1130. static const MemoryRegionOps ac97_io_nabm_ops = {
  1131. .old_portio = nabm_portio,
  1132. };
  1133. static void ac97_on_reset (void *opaque)
  1134. {
  1135. AC97LinkState *s = opaque;
  1136. reset_bm_regs (s, &s->bm_regs[0]);
  1137. reset_bm_regs (s, &s->bm_regs[1]);
  1138. reset_bm_regs (s, &s->bm_regs[2]);
  1139. /*
  1140. * Reset the mixer too. The Windows XP driver seems to rely on
  1141. * this. At least it wants to read the vendor id before it resets
  1142. * the codec manually.
  1143. */
  1144. mixer_reset (s);
  1145. }
  1146. static int ac97_initfn (PCIDevice *dev)
  1147. {
  1148. AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
  1149. uint8_t *c = s->dev.config;
  1150. /* TODO: no need to override */
  1151. c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
  1152. c[PCI_COMMAND + 1] = 0x00;
  1153. /* TODO: */
  1154. c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
  1155. c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
  1156. c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
  1157. /* TODO set when bar is registered. no need to override. */
  1158. /* nabmar native audio mixer base address rw */
  1159. c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
  1160. c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
  1161. c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
  1162. c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
  1163. /* TODO set when bar is registered. no need to override. */
  1164. /* nabmbar native audio bus mastering base address rw */
  1165. c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
  1166. c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
  1167. c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
  1168. c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
  1169. if (s->use_broken_id) {
  1170. c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86;
  1171. c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
  1172. c[PCI_SUBSYSTEM_ID] = 0x00;
  1173. c[PCI_SUBSYSTEM_ID + 1] = 0x00;
  1174. }
  1175. c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
  1176. c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
  1177. memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
  1178. memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
  1179. pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
  1180. pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
  1181. qemu_register_reset (ac97_on_reset, s);
  1182. AUD_register_card ("ac97", &s->card);
  1183. ac97_on_reset (s);
  1184. return 0;
  1185. }
  1186. static int ac97_exitfn (PCIDevice *dev)
  1187. {
  1188. AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
  1189. memory_region_destroy (&s->io_nam);
  1190. memory_region_destroy (&s->io_nabm);
  1191. return 0;
  1192. }
  1193. int ac97_init (PCIBus *bus)
  1194. {
  1195. pci_create_simple (bus, -1, "AC97");
  1196. return 0;
  1197. }
  1198. static PCIDeviceInfo ac97_info = {
  1199. .qdev.name = "AC97",
  1200. .qdev.desc = "Intel 82801AA AC97 Audio",
  1201. .qdev.size = sizeof (AC97LinkState),
  1202. .qdev.vmsd = &vmstate_ac97,
  1203. .init = ac97_initfn,
  1204. .exit = ac97_exitfn,
  1205. .vendor_id = PCI_VENDOR_ID_INTEL,
  1206. .device_id = PCI_DEVICE_ID_INTEL_82801AA_5,
  1207. .revision = 0x01,
  1208. .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
  1209. .qdev.props = (Property[]) {
  1210. DEFINE_PROP_UINT32("use_broken_id", AC97LinkState, use_broken_id, 0),
  1211. DEFINE_PROP_END_OF_LIST(),
  1212. }
  1213. };
  1214. static void ac97_register (void)
  1215. {
  1216. pci_qdev_register (&ac97_info);
  1217. }
  1218. device_init (ac97_register);