tc58128.c 4.3 KB

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  1. #include "hw.h"
  2. #include "sh.h"
  3. #include "loader.h"
  4. #define CE1 0x0100
  5. #define CE2 0x0200
  6. #define RE 0x0400
  7. #define WE 0x0800
  8. #define ALE 0x1000
  9. #define CLE 0x2000
  10. #define RDY1 0x4000
  11. #define RDY2 0x8000
  12. #define RDY(n) ((n) == 0 ? RDY1 : RDY2)
  13. typedef enum { WAIT, READ1, READ2, READ3 } state_t;
  14. typedef struct {
  15. uint8_t *flash_contents;
  16. state_t state;
  17. uint32_t address;
  18. uint8_t address_cycle;
  19. } tc58128_dev;
  20. static tc58128_dev tc58128_devs[2];
  21. #define FLASH_SIZE (16*1024*1024)
  22. static void init_dev(tc58128_dev * dev, const char *filename)
  23. {
  24. int ret, blocks;
  25. dev->state = WAIT;
  26. dev->flash_contents = qemu_mallocz(FLASH_SIZE);
  27. memset(dev->flash_contents, 0xff, FLASH_SIZE);
  28. if (!dev->flash_contents) {
  29. fprintf(stderr, "could not alloc memory for flash\n");
  30. exit(1);
  31. }
  32. if (filename) {
  33. /* Load flash image skipping the first block */
  34. ret = load_image(filename, dev->flash_contents + 528 * 32);
  35. if (ret < 0) {
  36. fprintf(stderr, "ret=%d\n", ret);
  37. fprintf(stderr, "qemu: could not load flash image %s\n",
  38. filename);
  39. exit(1);
  40. } else {
  41. /* Build first block with number of blocks */
  42. blocks = (ret + 528 * 32 - 1) / (528 * 32);
  43. dev->flash_contents[0] = blocks & 0xff;
  44. dev->flash_contents[1] = (blocks >> 8) & 0xff;
  45. dev->flash_contents[2] = (blocks >> 16) & 0xff;
  46. dev->flash_contents[3] = (blocks >> 24) & 0xff;
  47. fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
  48. filename);
  49. }
  50. }
  51. }
  52. static void handle_command(tc58128_dev * dev, uint8_t command)
  53. {
  54. switch (command) {
  55. case 0xff:
  56. fprintf(stderr, "reset flash device\n");
  57. dev->state = WAIT;
  58. break;
  59. case 0x00:
  60. fprintf(stderr, "read mode 1\n");
  61. dev->state = READ1;
  62. dev->address_cycle = 0;
  63. break;
  64. case 0x01:
  65. fprintf(stderr, "read mode 2\n");
  66. dev->state = READ2;
  67. dev->address_cycle = 0;
  68. break;
  69. case 0x50:
  70. fprintf(stderr, "read mode 3\n");
  71. dev->state = READ3;
  72. dev->address_cycle = 0;
  73. break;
  74. default:
  75. fprintf(stderr, "unknown flash command 0x%02x\n", command);
  76. abort();
  77. }
  78. }
  79. static void handle_address(tc58128_dev * dev, uint8_t data)
  80. {
  81. switch (dev->state) {
  82. case READ1:
  83. case READ2:
  84. case READ3:
  85. switch (dev->address_cycle) {
  86. case 0:
  87. dev->address = data;
  88. if (dev->state == READ2)
  89. dev->address |= 0x100;
  90. else if (dev->state == READ3)
  91. dev->address |= 0x200;
  92. break;
  93. case 1:
  94. dev->address += data * 528 * 0x100;
  95. break;
  96. case 2:
  97. dev->address += data * 528;
  98. fprintf(stderr, "address pointer in flash: 0x%08x\n",
  99. dev->address);
  100. break;
  101. default:
  102. /* Invalid data */
  103. abort();
  104. }
  105. dev->address_cycle++;
  106. break;
  107. default:
  108. abort();
  109. }
  110. }
  111. static uint8_t handle_read(tc58128_dev * dev)
  112. {
  113. #if 0
  114. if (dev->address % 0x100000 == 0)
  115. fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
  116. #endif
  117. return dev->flash_contents[dev->address++];
  118. }
  119. /* We never mark the device as busy, so interrupts cannot be triggered
  120. XXXXX */
  121. static int tc58128_cb(uint16_t porta, uint16_t portb,
  122. uint16_t * periph_pdtra, uint16_t * periph_portadir,
  123. uint16_t * periph_pdtrb, uint16_t * periph_portbdir)
  124. {
  125. int dev;
  126. if ((porta & CE1) == 0)
  127. dev = 0;
  128. else if ((porta & CE2) == 0)
  129. dev = 1;
  130. else
  131. return 0; /* No device selected */
  132. if ((porta & RE) && (porta & WE)) {
  133. /* Nothing to do, assert ready and return to input state */
  134. *periph_portadir &= 0xff00;
  135. *periph_portadir |= RDY(dev);
  136. *periph_pdtra |= RDY(dev);
  137. return 1;
  138. }
  139. if (porta & CLE) {
  140. /* Command */
  141. assert((porta & WE) == 0);
  142. handle_command(&tc58128_devs[dev], porta & 0x00ff);
  143. } else if (porta & ALE) {
  144. assert((porta & WE) == 0);
  145. handle_address(&tc58128_devs[dev], porta & 0x00ff);
  146. } else if ((porta & RE) == 0) {
  147. *periph_portadir |= 0x00ff;
  148. *periph_pdtra &= 0xff00;
  149. *periph_pdtra |= handle_read(&tc58128_devs[dev]);
  150. } else {
  151. abort();
  152. }
  153. return 1;
  154. }
  155. static sh7750_io_device tc58128 = {
  156. RE | WE, /* Port A triggers */
  157. 0, /* Port B triggers */
  158. tc58128_cb /* Callback */
  159. };
  160. int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
  161. {
  162. init_dev(&tc58128_devs[0], zone1);
  163. init_dev(&tc58128_devs[1], zone2);
  164. return sh7750_register_io_device(s, &tc58128);
  165. }