syborg_interrupt.c 6.6 KB

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  1. /*
  2. * Syborg interrupt controller.
  3. *
  4. * Copyright (c) 2008 CodeSourcery
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "sysbus.h"
  25. #include "syborg.h"
  26. //#define DEBUG_SYBORG_INT
  27. #ifdef DEBUG_SYBORG_INT
  28. #define DPRINTF(fmt, ...) \
  29. do { printf("syborg_int: " fmt , ## __VA_ARGS__); } while (0)
  30. #define BADF(fmt, ...) \
  31. do { fprintf(stderr, "syborg_int: error: " fmt , ## __VA_ARGS__); \
  32. exit(1);} while (0)
  33. #else
  34. #define DPRINTF(fmt, ...) do {} while(0)
  35. #define BADF(fmt, ...) \
  36. do { fprintf(stderr, "syborg_int: error: " fmt , ## __VA_ARGS__);} while (0)
  37. #endif
  38. enum {
  39. INT_ID = 0,
  40. INT_STATUS = 1, /* number of pending interrupts */
  41. INT_CURRENT = 2, /* next interrupt to be serviced */
  42. INT_DISABLE_ALL = 3,
  43. INT_DISABLE = 4,
  44. INT_ENABLE = 5,
  45. INT_TOTAL = 6
  46. };
  47. typedef struct {
  48. unsigned level:1;
  49. unsigned enabled:1;
  50. } syborg_int_flags;
  51. typedef struct {
  52. SysBusDevice busdev;
  53. int pending_count;
  54. uint32_t num_irqs;
  55. syborg_int_flags *flags;
  56. qemu_irq parent_irq;
  57. } SyborgIntState;
  58. static void syborg_int_update(SyborgIntState *s)
  59. {
  60. DPRINTF("pending %d\n", s->pending_count);
  61. qemu_set_irq(s->parent_irq, s->pending_count > 0);
  62. }
  63. static void syborg_int_set_irq(void *opaque, int irq, int level)
  64. {
  65. SyborgIntState *s = (SyborgIntState *)opaque;
  66. if (s->flags[irq].level == level)
  67. return;
  68. s->flags[irq].level = level;
  69. if (s->flags[irq].enabled) {
  70. if (level)
  71. s->pending_count++;
  72. else
  73. s->pending_count--;
  74. syborg_int_update(s);
  75. }
  76. }
  77. static uint32_t syborg_int_read(void *opaque, target_phys_addr_t offset)
  78. {
  79. SyborgIntState *s = (SyborgIntState *)opaque;
  80. int i;
  81. offset &= 0xfff;
  82. switch (offset >> 2) {
  83. case INT_ID:
  84. return SYBORG_ID_INT;
  85. case INT_STATUS:
  86. DPRINTF("read status=%d\n", s->pending_count);
  87. return s->pending_count;
  88. case INT_CURRENT:
  89. for (i = 0; i < s->num_irqs; i++) {
  90. if (s->flags[i].level & s->flags[i].enabled) {
  91. DPRINTF("read current=%d\n", i);
  92. return i;
  93. }
  94. }
  95. DPRINTF("read current=none\n");
  96. return 0xffffffffu;
  97. default:
  98. cpu_abort(cpu_single_env, "syborg_int_read: Bad offset %x\n",
  99. (int)offset);
  100. return 0;
  101. }
  102. }
  103. static void syborg_int_write(void *opaque, target_phys_addr_t offset, uint32_t value)
  104. {
  105. SyborgIntState *s = (SyborgIntState *)opaque;
  106. int i;
  107. offset &= 0xfff;
  108. DPRINTF("syborg_int_write offset=%d val=%d\n", (int)offset, (int)value);
  109. switch (offset >> 2) {
  110. case INT_DISABLE_ALL:
  111. s->pending_count = 0;
  112. for (i = 0; i < s->num_irqs; i++)
  113. s->flags[i].enabled = 0;
  114. break;
  115. case INT_DISABLE:
  116. if (value >= s->num_irqs)
  117. break;
  118. if (s->flags[value].enabled) {
  119. if (s->flags[value].enabled)
  120. s->pending_count--;
  121. s->flags[value].enabled = 0;
  122. }
  123. break;
  124. case INT_ENABLE:
  125. if (value >= s->num_irqs)
  126. break;
  127. if (!(s->flags[value].enabled)) {
  128. if(s->flags[value].level)
  129. s->pending_count++;
  130. s->flags[value].enabled = 1;
  131. }
  132. break;
  133. default:
  134. cpu_abort(cpu_single_env, "syborg_int_write: Bad offset %x\n",
  135. (int)offset);
  136. return;
  137. }
  138. syborg_int_update(s);
  139. }
  140. static CPUReadMemoryFunc * const syborg_int_readfn[] = {
  141. syborg_int_read,
  142. syborg_int_read,
  143. syborg_int_read
  144. };
  145. static CPUWriteMemoryFunc * const syborg_int_writefn[] = {
  146. syborg_int_write,
  147. syborg_int_write,
  148. syborg_int_write
  149. };
  150. static void syborg_int_save(QEMUFile *f, void *opaque)
  151. {
  152. SyborgIntState *s = (SyborgIntState *)opaque;
  153. int i;
  154. qemu_put_be32(f, s->num_irqs);
  155. qemu_put_be32(f, s->pending_count);
  156. for (i = 0; i < s->num_irqs; i++) {
  157. qemu_put_be32(f, s->flags[i].enabled
  158. | ((unsigned)s->flags[i].level << 1));
  159. }
  160. }
  161. static int syborg_int_load(QEMUFile *f, void *opaque, int version_id)
  162. {
  163. SyborgIntState *s = (SyborgIntState *)opaque;
  164. uint32_t val;
  165. int i;
  166. if (version_id != 1)
  167. return -EINVAL;
  168. val = qemu_get_be32(f);
  169. if (val != s->num_irqs)
  170. return -EINVAL;
  171. s->pending_count = qemu_get_be32(f);
  172. for (i = 0; i < s->num_irqs; i++) {
  173. val = qemu_get_be32(f);
  174. s->flags[i].enabled = val & 1;
  175. s->flags[i].level = (val >> 1) & 1;
  176. }
  177. return 0;
  178. }
  179. static int syborg_int_init(SysBusDevice *dev)
  180. {
  181. SyborgIntState *s = FROM_SYSBUS(SyborgIntState, dev);
  182. int iomemtype;
  183. sysbus_init_irq(dev, &s->parent_irq);
  184. qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs);
  185. iomemtype = cpu_register_io_memory(syborg_int_readfn,
  186. syborg_int_writefn, s,
  187. DEVICE_NATIVE_ENDIAN);
  188. sysbus_init_mmio(dev, 0x1000, iomemtype);
  189. s->flags = qemu_mallocz(s->num_irqs * sizeof(syborg_int_flags));
  190. register_savevm(&dev->qdev, "syborg_int", -1, 1, syborg_int_save,
  191. syborg_int_load, s);
  192. return 0;
  193. }
  194. static SysBusDeviceInfo syborg_int_info = {
  195. .init = syborg_int_init,
  196. .qdev.name = "syborg,interrupt",
  197. .qdev.size = sizeof(SyborgIntState),
  198. .qdev.props = (Property[]) {
  199. DEFINE_PROP_UINT32("num-interrupts", SyborgIntState, num_irqs, 64),
  200. DEFINE_PROP_END_OF_LIST(),
  201. }
  202. };
  203. static void syborg_interrupt_register_devices(void)
  204. {
  205. sysbus_register_withprop(&syborg_int_info);
  206. }
  207. device_init(syborg_interrupt_register_devices)