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stellaris_enet.c 13 KB

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  1. /*
  2. * Luminary Micro Stellaris Ethernet Controller
  3. *
  4. * Copyright (c) 2007 CodeSourcery.
  5. * Written by Paul Brook
  6. *
  7. * This code is licensed under the GPL.
  8. */
  9. #include "sysbus.h"
  10. #include "net.h"
  11. #include <zlib.h>
  12. //#define DEBUG_STELLARIS_ENET 1
  13. #ifdef DEBUG_STELLARIS_ENET
  14. #define DPRINTF(fmt, ...) \
  15. do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
  16. #define BADF(fmt, ...) \
  17. do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  18. #else
  19. #define DPRINTF(fmt, ...) do {} while(0)
  20. #define BADF(fmt, ...) \
  21. do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
  22. #endif
  23. #define SE_INT_RX 0x01
  24. #define SE_INT_TXER 0x02
  25. #define SE_INT_TXEMP 0x04
  26. #define SE_INT_FOV 0x08
  27. #define SE_INT_RXER 0x10
  28. #define SE_INT_MD 0x20
  29. #define SE_INT_PHY 0x40
  30. #define SE_RCTL_RXEN 0x01
  31. #define SE_RCTL_AMUL 0x02
  32. #define SE_RCTL_PRMS 0x04
  33. #define SE_RCTL_BADCRC 0x08
  34. #define SE_RCTL_RSTFIFO 0x10
  35. #define SE_TCTL_TXEN 0x01
  36. #define SE_TCTL_PADEN 0x02
  37. #define SE_TCTL_CRC 0x04
  38. #define SE_TCTL_DUPLEX 0x08
  39. typedef struct {
  40. SysBusDevice busdev;
  41. uint32_t ris;
  42. uint32_t im;
  43. uint32_t rctl;
  44. uint32_t tctl;
  45. uint32_t thr;
  46. uint32_t mctl;
  47. uint32_t mdv;
  48. uint32_t mtxd;
  49. uint32_t mrxd;
  50. uint32_t np;
  51. int tx_frame_len;
  52. int tx_fifo_len;
  53. uint8_t tx_fifo[2048];
  54. /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
  55. We implement a full 31 packet fifo. */
  56. struct {
  57. uint8_t data[2048];
  58. int len;
  59. } rx[31];
  60. uint8_t *rx_fifo;
  61. int rx_fifo_len;
  62. int next_packet;
  63. NICState *nic;
  64. NICConf conf;
  65. qemu_irq irq;
  66. int mmio_index;
  67. } stellaris_enet_state;
  68. static void stellaris_enet_update(stellaris_enet_state *s)
  69. {
  70. qemu_set_irq(s->irq, (s->ris & s->im) != 0);
  71. }
  72. /* TODO: Implement MAC address filtering. */
  73. static ssize_t stellaris_enet_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
  74. {
  75. stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
  76. int n;
  77. uint8_t *p;
  78. uint32_t crc;
  79. if ((s->rctl & SE_RCTL_RXEN) == 0)
  80. return -1;
  81. if (s->np >= 31) {
  82. DPRINTF("Packet dropped\n");
  83. return -1;
  84. }
  85. DPRINTF("Received packet len=%d\n", size);
  86. n = s->next_packet + s->np;
  87. if (n >= 31)
  88. n -= 31;
  89. s->np++;
  90. s->rx[n].len = size + 6;
  91. p = s->rx[n].data;
  92. *(p++) = (size + 6);
  93. *(p++) = (size + 6) >> 8;
  94. memcpy (p, buf, size);
  95. p += size;
  96. crc = crc32(~0, buf, size);
  97. *(p++) = crc;
  98. *(p++) = crc >> 8;
  99. *(p++) = crc >> 16;
  100. *(p++) = crc >> 24;
  101. /* Clear the remaining bytes in the last word. */
  102. if ((size & 3) != 2) {
  103. memset(p, 0, (6 - size) & 3);
  104. }
  105. s->ris |= SE_INT_RX;
  106. stellaris_enet_update(s);
  107. return size;
  108. }
  109. static int stellaris_enet_can_receive(VLANClientState *nc)
  110. {
  111. stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
  112. if ((s->rctl & SE_RCTL_RXEN) == 0)
  113. return 1;
  114. return (s->np < 31);
  115. }
  116. static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
  117. {
  118. stellaris_enet_state *s = (stellaris_enet_state *)opaque;
  119. uint32_t val;
  120. switch (offset) {
  121. case 0x00: /* RIS */
  122. DPRINTF("IRQ status %02x\n", s->ris);
  123. return s->ris;
  124. case 0x04: /* IM */
  125. return s->im;
  126. case 0x08: /* RCTL */
  127. return s->rctl;
  128. case 0x0c: /* TCTL */
  129. return s->tctl;
  130. case 0x10: /* DATA */
  131. if (s->rx_fifo_len == 0) {
  132. if (s->np == 0) {
  133. BADF("RX underflow\n");
  134. return 0;
  135. }
  136. s->rx_fifo_len = s->rx[s->next_packet].len;
  137. s->rx_fifo = s->rx[s->next_packet].data;
  138. DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
  139. }
  140. val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
  141. | (s->rx_fifo[3] << 24);
  142. s->rx_fifo += 4;
  143. s->rx_fifo_len -= 4;
  144. if (s->rx_fifo_len <= 0) {
  145. s->rx_fifo_len = 0;
  146. s->next_packet++;
  147. if (s->next_packet >= 31)
  148. s->next_packet = 0;
  149. s->np--;
  150. DPRINTF("RX done np=%d\n", s->np);
  151. }
  152. return val;
  153. case 0x14: /* IA0 */
  154. return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
  155. | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
  156. case 0x18: /* IA1 */
  157. return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
  158. case 0x1c: /* THR */
  159. return s->thr;
  160. case 0x20: /* MCTL */
  161. return s->mctl;
  162. case 0x24: /* MDV */
  163. return s->mdv;
  164. case 0x28: /* MADD */
  165. return 0;
  166. case 0x2c: /* MTXD */
  167. return s->mtxd;
  168. case 0x30: /* MRXD */
  169. return s->mrxd;
  170. case 0x34: /* NP */
  171. return s->np;
  172. case 0x38: /* TR */
  173. return 0;
  174. case 0x3c: /* Undocuented: Timestamp? */
  175. return 0;
  176. default:
  177. hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
  178. return 0;
  179. }
  180. }
  181. static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
  182. uint32_t value)
  183. {
  184. stellaris_enet_state *s = (stellaris_enet_state *)opaque;
  185. switch (offset) {
  186. case 0x00: /* IACK */
  187. s->ris &= ~value;
  188. DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
  189. stellaris_enet_update(s);
  190. /* Clearing TXER also resets the TX fifo. */
  191. if (value & SE_INT_TXER)
  192. s->tx_frame_len = -1;
  193. break;
  194. case 0x04: /* IM */
  195. DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
  196. s->im = value;
  197. stellaris_enet_update(s);
  198. break;
  199. case 0x08: /* RCTL */
  200. s->rctl = value;
  201. if (value & SE_RCTL_RSTFIFO) {
  202. s->rx_fifo_len = 0;
  203. s->np = 0;
  204. stellaris_enet_update(s);
  205. }
  206. break;
  207. case 0x0c: /* TCTL */
  208. s->tctl = value;
  209. break;
  210. case 0x10: /* DATA */
  211. if (s->tx_frame_len == -1) {
  212. s->tx_frame_len = value & 0xffff;
  213. if (s->tx_frame_len > 2032) {
  214. DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
  215. s->tx_frame_len = 0;
  216. s->ris |= SE_INT_TXER;
  217. stellaris_enet_update(s);
  218. } else {
  219. DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
  220. /* The value written does not include the ethernet header. */
  221. s->tx_frame_len += 14;
  222. if ((s->tctl & SE_TCTL_CRC) == 0)
  223. s->tx_frame_len += 4;
  224. s->tx_fifo_len = 0;
  225. s->tx_fifo[s->tx_fifo_len++] = value >> 16;
  226. s->tx_fifo[s->tx_fifo_len++] = value >> 24;
  227. }
  228. } else {
  229. s->tx_fifo[s->tx_fifo_len++] = value;
  230. s->tx_fifo[s->tx_fifo_len++] = value >> 8;
  231. s->tx_fifo[s->tx_fifo_len++] = value >> 16;
  232. s->tx_fifo[s->tx_fifo_len++] = value >> 24;
  233. if (s->tx_fifo_len >= s->tx_frame_len) {
  234. /* We don't implement explicit CRC, so just chop it off. */
  235. if ((s->tctl & SE_TCTL_CRC) == 0)
  236. s->tx_frame_len -= 4;
  237. if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
  238. memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
  239. s->tx_fifo_len = 60;
  240. }
  241. qemu_send_packet(&s->nic->nc, s->tx_fifo, s->tx_frame_len);
  242. s->tx_frame_len = -1;
  243. s->ris |= SE_INT_TXEMP;
  244. stellaris_enet_update(s);
  245. DPRINTF("Done TX\n");
  246. }
  247. }
  248. break;
  249. case 0x14: /* IA0 */
  250. s->conf.macaddr.a[0] = value;
  251. s->conf.macaddr.a[1] = value >> 8;
  252. s->conf.macaddr.a[2] = value >> 16;
  253. s->conf.macaddr.a[3] = value >> 24;
  254. break;
  255. case 0x18: /* IA1 */
  256. s->conf.macaddr.a[4] = value;
  257. s->conf.macaddr.a[5] = value >> 8;
  258. break;
  259. case 0x1c: /* THR */
  260. s->thr = value;
  261. break;
  262. case 0x20: /* MCTL */
  263. s->mctl = value;
  264. break;
  265. case 0x24: /* MDV */
  266. s->mdv = value;
  267. break;
  268. case 0x28: /* MADD */
  269. /* ignored. */
  270. break;
  271. case 0x2c: /* MTXD */
  272. s->mtxd = value & 0xff;
  273. break;
  274. case 0x30: /* MRXD */
  275. case 0x34: /* NP */
  276. case 0x38: /* TR */
  277. /* Ignored. */
  278. case 0x3c: /* Undocuented: Timestamp? */
  279. /* Ignored. */
  280. break;
  281. default:
  282. hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
  283. }
  284. }
  285. static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
  286. stellaris_enet_read,
  287. stellaris_enet_read,
  288. stellaris_enet_read
  289. };
  290. static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
  291. stellaris_enet_write,
  292. stellaris_enet_write,
  293. stellaris_enet_write
  294. };
  295. static void stellaris_enet_reset(stellaris_enet_state *s)
  296. {
  297. s->mdv = 0x80;
  298. s->rctl = SE_RCTL_BADCRC;
  299. s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
  300. | SE_INT_TXER | SE_INT_RX;
  301. s->thr = 0x3f;
  302. s->tx_frame_len = -1;
  303. }
  304. static void stellaris_enet_save(QEMUFile *f, void *opaque)
  305. {
  306. stellaris_enet_state *s = (stellaris_enet_state *)opaque;
  307. int i;
  308. qemu_put_be32(f, s->ris);
  309. qemu_put_be32(f, s->im);
  310. qemu_put_be32(f, s->rctl);
  311. qemu_put_be32(f, s->tctl);
  312. qemu_put_be32(f, s->thr);
  313. qemu_put_be32(f, s->mctl);
  314. qemu_put_be32(f, s->mdv);
  315. qemu_put_be32(f, s->mtxd);
  316. qemu_put_be32(f, s->mrxd);
  317. qemu_put_be32(f, s->np);
  318. qemu_put_be32(f, s->tx_frame_len);
  319. qemu_put_be32(f, s->tx_fifo_len);
  320. qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
  321. for (i = 0; i < 31; i++) {
  322. qemu_put_be32(f, s->rx[i].len);
  323. qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
  324. }
  325. qemu_put_be32(f, s->next_packet);
  326. qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
  327. qemu_put_be32(f, s->rx_fifo_len);
  328. }
  329. static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
  330. {
  331. stellaris_enet_state *s = (stellaris_enet_state *)opaque;
  332. int i;
  333. if (version_id != 1)
  334. return -EINVAL;
  335. s->ris = qemu_get_be32(f);
  336. s->im = qemu_get_be32(f);
  337. s->rctl = qemu_get_be32(f);
  338. s->tctl = qemu_get_be32(f);
  339. s->thr = qemu_get_be32(f);
  340. s->mctl = qemu_get_be32(f);
  341. s->mdv = qemu_get_be32(f);
  342. s->mtxd = qemu_get_be32(f);
  343. s->mrxd = qemu_get_be32(f);
  344. s->np = qemu_get_be32(f);
  345. s->tx_frame_len = qemu_get_be32(f);
  346. s->tx_fifo_len = qemu_get_be32(f);
  347. qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
  348. for (i = 0; i < 31; i++) {
  349. s->rx[i].len = qemu_get_be32(f);
  350. qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
  351. }
  352. s->next_packet = qemu_get_be32(f);
  353. s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
  354. s->rx_fifo_len = qemu_get_be32(f);
  355. return 0;
  356. }
  357. static void stellaris_enet_cleanup(VLANClientState *nc)
  358. {
  359. stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
  360. unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
  361. cpu_unregister_io_memory(s->mmio_index);
  362. qemu_free(s);
  363. }
  364. static NetClientInfo net_stellaris_enet_info = {
  365. .type = NET_CLIENT_TYPE_NIC,
  366. .size = sizeof(NICState),
  367. .can_receive = stellaris_enet_can_receive,
  368. .receive = stellaris_enet_receive,
  369. .cleanup = stellaris_enet_cleanup,
  370. };
  371. static int stellaris_enet_init(SysBusDevice *dev)
  372. {
  373. stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
  374. s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
  375. stellaris_enet_writefn, s,
  376. DEVICE_NATIVE_ENDIAN);
  377. sysbus_init_mmio(dev, 0x1000, s->mmio_index);
  378. sysbus_init_irq(dev, &s->irq);
  379. qemu_macaddr_default_if_unset(&s->conf.macaddr);
  380. s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
  381. dev->qdev.info->name, dev->qdev.id, s);
  382. qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
  383. stellaris_enet_reset(s);
  384. register_savevm(&s->busdev.qdev, "stellaris_enet", -1, 1,
  385. stellaris_enet_save, stellaris_enet_load, s);
  386. return 0;
  387. }
  388. static SysBusDeviceInfo stellaris_enet_info = {
  389. .init = stellaris_enet_init,
  390. .qdev.name = "stellaris_enet",
  391. .qdev.size = sizeof(stellaris_enet_state),
  392. .qdev.props = (Property[]) {
  393. DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
  394. DEFINE_PROP_END_OF_LIST(),
  395. }
  396. };
  397. static void stellaris_enet_register_devices(void)
  398. {
  399. sysbus_register_withprop(&stellaris_enet_info);
  400. }
  401. device_init(stellaris_enet_register_devices)