spitz.c 32 KB

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  1. /*
  2. * PXA270-based Clamshell PDA platforms.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Written by Andrzej Zaborowski <balrog@zabor.org>
  6. *
  7. * This code is licensed under the GNU GPL v2.
  8. */
  9. #include "hw.h"
  10. #include "pxa.h"
  11. #include "arm-misc.h"
  12. #include "sysemu.h"
  13. #include "pcmcia.h"
  14. #include "i2c.h"
  15. #include "ssi.h"
  16. #include "flash.h"
  17. #include "qemu-timer.h"
  18. #include "devices.h"
  19. #include "sharpsl.h"
  20. #include "console.h"
  21. #include "block.h"
  22. #include "audio/audio.h"
  23. #include "boards.h"
  24. #include "blockdev.h"
  25. #include "sysbus.h"
  26. #undef REG_FMT
  27. #define REG_FMT "0x%02lx"
  28. /* Spitz Flash */
  29. #define FLASH_BASE 0x0c000000
  30. #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
  31. #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
  32. #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
  33. #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
  34. #define FLASH_ECCCLRR 0x10 /* Clear ECC */
  35. #define FLASH_FLASHIO 0x14 /* Flash I/O */
  36. #define FLASH_FLASHCTL 0x18 /* Flash Control */
  37. #define FLASHCTL_CE0 (1 << 0)
  38. #define FLASHCTL_CLE (1 << 1)
  39. #define FLASHCTL_ALE (1 << 2)
  40. #define FLASHCTL_WP (1 << 3)
  41. #define FLASHCTL_CE1 (1 << 4)
  42. #define FLASHCTL_RYBY (1 << 5)
  43. #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
  44. typedef struct {
  45. SysBusDevice busdev;
  46. NANDFlashState *nand;
  47. uint8_t ctl;
  48. uint8_t manf_id;
  49. uint8_t chip_id;
  50. ECCState ecc;
  51. } SLNANDState;
  52. static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
  53. {
  54. SLNANDState *s = (SLNANDState *) opaque;
  55. int ryby;
  56. switch (addr) {
  57. #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  58. case FLASH_ECCLPLB:
  59. return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  60. BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  61. #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  62. case FLASH_ECCLPUB:
  63. return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  64. BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  65. case FLASH_ECCCP:
  66. return s->ecc.cp;
  67. case FLASH_ECCCNTR:
  68. return s->ecc.count & 0xff;
  69. case FLASH_FLASHCTL:
  70. nand_getpins(s->nand, &ryby);
  71. if (ryby)
  72. return s->ctl | FLASHCTL_RYBY;
  73. else
  74. return s->ctl;
  75. case FLASH_FLASHIO:
  76. return ecc_digest(&s->ecc, nand_getio(s->nand));
  77. default:
  78. zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  79. }
  80. return 0;
  81. }
  82. static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
  83. {
  84. SLNANDState *s = (SLNANDState *) opaque;
  85. if (addr == FLASH_FLASHIO)
  86. return ecc_digest(&s->ecc, nand_getio(s->nand)) |
  87. (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
  88. return sl_readb(opaque, addr);
  89. }
  90. static void sl_writeb(void *opaque, target_phys_addr_t addr,
  91. uint32_t value)
  92. {
  93. SLNANDState *s = (SLNANDState *) opaque;
  94. switch (addr) {
  95. case FLASH_ECCCLRR:
  96. /* Value is ignored. */
  97. ecc_reset(&s->ecc);
  98. break;
  99. case FLASH_FLASHCTL:
  100. s->ctl = value & 0xff & ~FLASHCTL_RYBY;
  101. nand_setpins(s->nand,
  102. s->ctl & FLASHCTL_CLE,
  103. s->ctl & FLASHCTL_ALE,
  104. s->ctl & FLASHCTL_NCE,
  105. s->ctl & FLASHCTL_WP,
  106. 0);
  107. break;
  108. case FLASH_FLASHIO:
  109. nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
  110. break;
  111. default:
  112. zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  113. }
  114. }
  115. enum {
  116. FLASH_128M,
  117. FLASH_1024M,
  118. };
  119. static CPUReadMemoryFunc * const sl_readfn[] = {
  120. sl_readb,
  121. sl_readb,
  122. sl_readl,
  123. };
  124. static CPUWriteMemoryFunc * const sl_writefn[] = {
  125. sl_writeb,
  126. sl_writeb,
  127. sl_writeb,
  128. };
  129. static void sl_flash_register(PXA2xxState *cpu, int size)
  130. {
  131. DeviceState *dev;
  132. dev = qdev_create(NULL, "sl-nand");
  133. qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
  134. if (size == FLASH_128M)
  135. qdev_prop_set_uint8(dev, "chip_id", 0x73);
  136. else if (size == FLASH_1024M)
  137. qdev_prop_set_uint8(dev, "chip_id", 0xf1);
  138. qdev_init_nofail(dev);
  139. sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE);
  140. }
  141. static int sl_nand_init(SysBusDevice *dev) {
  142. int iomemtype;
  143. SLNANDState *s;
  144. s = FROM_SYSBUS(SLNANDState, dev);
  145. s->ctl = 0;
  146. s->nand = nand_init(s->manf_id, s->chip_id);
  147. iomemtype = cpu_register_io_memory(sl_readfn,
  148. sl_writefn, s, DEVICE_NATIVE_ENDIAN);
  149. sysbus_init_mmio(dev, 0x40, iomemtype);
  150. return 0;
  151. }
  152. /* Spitz Keyboard */
  153. #define SPITZ_KEY_STROBE_NUM 11
  154. #define SPITZ_KEY_SENSE_NUM 7
  155. static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
  156. 12, 17, 91, 34, 36, 38, 39
  157. };
  158. static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
  159. 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
  160. };
  161. /* Eighth additional row maps the special keys */
  162. static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
  163. { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
  164. { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
  165. { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
  166. { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
  167. { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
  168. { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
  169. { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
  170. { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
  171. };
  172. #define SPITZ_GPIO_AK_INT 13 /* Remote control */
  173. #define SPITZ_GPIO_SYNC 16 /* Sync button */
  174. #define SPITZ_GPIO_ON_KEY 95 /* Power button */
  175. #define SPITZ_GPIO_SWA 97 /* Lid */
  176. #define SPITZ_GPIO_SWB 96 /* Tablet mode */
  177. /* The special buttons are mapped to unused keys */
  178. static const int spitz_gpiomap[5] = {
  179. SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
  180. SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
  181. };
  182. typedef struct {
  183. SysBusDevice busdev;
  184. qemu_irq sense[SPITZ_KEY_SENSE_NUM];
  185. qemu_irq gpiomap[5];
  186. int keymap[0x80];
  187. uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
  188. uint16_t strobe_state;
  189. uint16_t sense_state;
  190. uint16_t pre_map[0x100];
  191. uint16_t modifiers;
  192. uint16_t imodifiers;
  193. uint8_t fifo[16];
  194. int fifopos, fifolen;
  195. QEMUTimer *kbdtimer;
  196. } SpitzKeyboardState;
  197. static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
  198. {
  199. int i;
  200. uint16_t strobe, sense = 0;
  201. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
  202. strobe = s->keyrow[i] & s->strobe_state;
  203. if (strobe) {
  204. sense |= 1 << i;
  205. if (!(s->sense_state & (1 << i)))
  206. qemu_irq_raise(s->sense[i]);
  207. } else if (s->sense_state & (1 << i))
  208. qemu_irq_lower(s->sense[i]);
  209. }
  210. s->sense_state = sense;
  211. }
  212. static void spitz_keyboard_strobe(void *opaque, int line, int level)
  213. {
  214. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  215. if (level)
  216. s->strobe_state |= 1 << line;
  217. else
  218. s->strobe_state &= ~(1 << line);
  219. spitz_keyboard_sense_update(s);
  220. }
  221. static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
  222. {
  223. int spitz_keycode = s->keymap[keycode & 0x7f];
  224. if (spitz_keycode == -1)
  225. return;
  226. /* Handle the additional keys */
  227. if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
  228. qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
  229. return;
  230. }
  231. if (keycode & 0x80)
  232. s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
  233. else
  234. s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
  235. spitz_keyboard_sense_update(s);
  236. }
  237. #define SHIFT (1 << 7)
  238. #define CTRL (1 << 8)
  239. #define FN (1 << 9)
  240. #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  241. static void spitz_keyboard_handler(void *opaque, int keycode)
  242. {
  243. SpitzKeyboardState *s = opaque;
  244. uint16_t code;
  245. int mapcode;
  246. switch (keycode) {
  247. case 0x2a: /* Left Shift */
  248. s->modifiers |= 1;
  249. break;
  250. case 0xaa:
  251. s->modifiers &= ~1;
  252. break;
  253. case 0x36: /* Right Shift */
  254. s->modifiers |= 2;
  255. break;
  256. case 0xb6:
  257. s->modifiers &= ~2;
  258. break;
  259. case 0x1d: /* Control */
  260. s->modifiers |= 4;
  261. break;
  262. case 0x9d:
  263. s->modifiers &= ~4;
  264. break;
  265. case 0x38: /* Alt */
  266. s->modifiers |= 8;
  267. break;
  268. case 0xb8:
  269. s->modifiers &= ~8;
  270. break;
  271. }
  272. code = s->pre_map[mapcode = ((s->modifiers & 3) ?
  273. (keycode | SHIFT) :
  274. (keycode & ~SHIFT))];
  275. if (code != mapcode) {
  276. #if 0
  277. if ((code & SHIFT) && !(s->modifiers & 1))
  278. QUEUE_KEY(0x2a | (keycode & 0x80));
  279. if ((code & CTRL ) && !(s->modifiers & 4))
  280. QUEUE_KEY(0x1d | (keycode & 0x80));
  281. if ((code & FN ) && !(s->modifiers & 8))
  282. QUEUE_KEY(0x38 | (keycode & 0x80));
  283. if ((code & FN ) && (s->modifiers & 1))
  284. QUEUE_KEY(0x2a | (~keycode & 0x80));
  285. if ((code & FN ) && (s->modifiers & 2))
  286. QUEUE_KEY(0x36 | (~keycode & 0x80));
  287. #else
  288. if (keycode & 0x80) {
  289. if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
  290. QUEUE_KEY(0x2a | 0x80);
  291. if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
  292. QUEUE_KEY(0x1d | 0x80);
  293. if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
  294. QUEUE_KEY(0x38 | 0x80);
  295. if ((s->imodifiers & 0x10) && (s->modifiers & 1))
  296. QUEUE_KEY(0x2a);
  297. if ((s->imodifiers & 0x20) && (s->modifiers & 2))
  298. QUEUE_KEY(0x36);
  299. s->imodifiers = 0;
  300. } else {
  301. if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
  302. QUEUE_KEY(0x2a);
  303. s->imodifiers |= 1;
  304. }
  305. if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
  306. QUEUE_KEY(0x1d);
  307. s->imodifiers |= 4;
  308. }
  309. if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
  310. QUEUE_KEY(0x38);
  311. s->imodifiers |= 8;
  312. }
  313. if ((code & FN ) && (s->modifiers & 1) &&
  314. !(s->imodifiers & 0x10)) {
  315. QUEUE_KEY(0x2a | 0x80);
  316. s->imodifiers |= 0x10;
  317. }
  318. if ((code & FN ) && (s->modifiers & 2) &&
  319. !(s->imodifiers & 0x20)) {
  320. QUEUE_KEY(0x36 | 0x80);
  321. s->imodifiers |= 0x20;
  322. }
  323. }
  324. #endif
  325. }
  326. QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
  327. }
  328. static void spitz_keyboard_tick(void *opaque)
  329. {
  330. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  331. if (s->fifolen) {
  332. spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
  333. s->fifolen --;
  334. if (s->fifopos >= 16)
  335. s->fifopos = 0;
  336. }
  337. qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
  338. get_ticks_per_sec() / 32);
  339. }
  340. static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
  341. {
  342. int i;
  343. for (i = 0; i < 0x100; i ++)
  344. s->pre_map[i] = i;
  345. s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
  346. s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
  347. s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
  348. s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
  349. s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
  350. s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
  351. s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
  352. s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
  353. s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
  354. s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
  355. s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
  356. s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
  357. s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
  358. s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
  359. s->pre_map[0x0d ] = 0x12 | FN; /* equal */
  360. s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
  361. s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
  362. s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
  363. s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
  364. s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
  365. s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
  366. s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
  367. s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
  368. s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
  369. s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
  370. s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
  371. s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
  372. s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
  373. s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
  374. s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
  375. s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
  376. s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
  377. s->modifiers = 0;
  378. s->imodifiers = 0;
  379. s->fifopos = 0;
  380. s->fifolen = 0;
  381. }
  382. #undef SHIFT
  383. #undef CTRL
  384. #undef FN
  385. static int spitz_keyboard_post_load(void *opaque, int version_id)
  386. {
  387. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  388. /* Release all pressed keys */
  389. memset(s->keyrow, 0, sizeof(s->keyrow));
  390. spitz_keyboard_sense_update(s);
  391. s->modifiers = 0;
  392. s->imodifiers = 0;
  393. s->fifopos = 0;
  394. s->fifolen = 0;
  395. return 0;
  396. }
  397. static void spitz_keyboard_register(PXA2xxState *cpu)
  398. {
  399. int i;
  400. DeviceState *dev;
  401. SpitzKeyboardState *s;
  402. dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
  403. s = FROM_SYSBUS(SpitzKeyboardState, sysbus_from_qdev(dev));
  404. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
  405. qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
  406. for (i = 0; i < 5; i ++)
  407. s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
  408. if (!graphic_rotate)
  409. s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
  410. for (i = 0; i < 5; i++)
  411. qemu_set_irq(s->gpiomap[i], 0);
  412. for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
  413. qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
  414. qdev_get_gpio_in(dev, i));
  415. qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
  416. qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
  417. }
  418. static int spitz_keyboard_init(SysBusDevice *dev)
  419. {
  420. SpitzKeyboardState *s;
  421. int i, j;
  422. s = FROM_SYSBUS(SpitzKeyboardState, dev);
  423. for (i = 0; i < 0x80; i ++)
  424. s->keymap[i] = -1;
  425. for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
  426. for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
  427. if (spitz_keymap[i][j] != -1)
  428. s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
  429. spitz_keyboard_pre_map(s);
  430. s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
  431. qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
  432. qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
  433. return 0;
  434. }
  435. /* LCD backlight controller */
  436. #define LCDTG_RESCTL 0x00
  437. #define LCDTG_PHACTRL 0x01
  438. #define LCDTG_DUTYCTRL 0x02
  439. #define LCDTG_POWERREG0 0x03
  440. #define LCDTG_POWERREG1 0x04
  441. #define LCDTG_GPOR3 0x05
  442. #define LCDTG_PICTRL 0x06
  443. #define LCDTG_POLCTRL 0x07
  444. typedef struct {
  445. SSISlave ssidev;
  446. uint32_t bl_intensity;
  447. uint32_t bl_power;
  448. } SpitzLCDTG;
  449. static void spitz_bl_update(SpitzLCDTG *s)
  450. {
  451. if (s->bl_power && s->bl_intensity)
  452. zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
  453. else
  454. zaurus_printf("LCD Backlight now off\n");
  455. }
  456. /* FIXME: Implement GPIO properly and remove this hack. */
  457. static SpitzLCDTG *spitz_lcdtg;
  458. static inline void spitz_bl_bit5(void *opaque, int line, int level)
  459. {
  460. SpitzLCDTG *s = spitz_lcdtg;
  461. int prev = s->bl_intensity;
  462. if (level)
  463. s->bl_intensity &= ~0x20;
  464. else
  465. s->bl_intensity |= 0x20;
  466. if (s->bl_power && prev != s->bl_intensity)
  467. spitz_bl_update(s);
  468. }
  469. static inline void spitz_bl_power(void *opaque, int line, int level)
  470. {
  471. SpitzLCDTG *s = spitz_lcdtg;
  472. s->bl_power = !!level;
  473. spitz_bl_update(s);
  474. }
  475. static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
  476. {
  477. SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
  478. int addr;
  479. addr = value >> 5;
  480. value &= 0x1f;
  481. switch (addr) {
  482. case LCDTG_RESCTL:
  483. if (value)
  484. zaurus_printf("LCD in QVGA mode\n");
  485. else
  486. zaurus_printf("LCD in VGA mode\n");
  487. break;
  488. case LCDTG_DUTYCTRL:
  489. s->bl_intensity &= ~0x1f;
  490. s->bl_intensity |= value;
  491. if (s->bl_power)
  492. spitz_bl_update(s);
  493. break;
  494. case LCDTG_POWERREG0:
  495. /* Set common voltage to M62332FP */
  496. break;
  497. }
  498. return 0;
  499. }
  500. static int spitz_lcdtg_init(SSISlave *dev)
  501. {
  502. SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
  503. spitz_lcdtg = s;
  504. s->bl_power = 0;
  505. s->bl_intensity = 0x20;
  506. return 0;
  507. }
  508. /* SSP devices */
  509. #define CORGI_SSP_PORT 2
  510. #define SPITZ_GPIO_LCDCON_CS 53
  511. #define SPITZ_GPIO_ADS7846_CS 14
  512. #define SPITZ_GPIO_MAX1111_CS 20
  513. #define SPITZ_GPIO_TP_INT 11
  514. static DeviceState *max1111;
  515. /* "Demux" the signal based on current chipselect */
  516. typedef struct {
  517. SSISlave ssidev;
  518. SSIBus *bus[3];
  519. uint32_t enable[3];
  520. } CorgiSSPState;
  521. static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
  522. {
  523. CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
  524. int i;
  525. for (i = 0; i < 3; i++) {
  526. if (s->enable[i]) {
  527. return ssi_transfer(s->bus[i], value);
  528. }
  529. }
  530. return 0;
  531. }
  532. static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  533. {
  534. CorgiSSPState *s = (CorgiSSPState *)opaque;
  535. assert(line >= 0 && line < 3);
  536. s->enable[line] = !level;
  537. }
  538. #define MAX1111_BATT_VOLT 1
  539. #define MAX1111_BATT_TEMP 2
  540. #define MAX1111_ACIN_VOLT 3
  541. #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
  542. #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
  543. #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
  544. static void spitz_adc_temp_on(void *opaque, int line, int level)
  545. {
  546. if (!max1111)
  547. return;
  548. if (level)
  549. max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
  550. else
  551. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  552. }
  553. static int corgi_ssp_init(SSISlave *dev)
  554. {
  555. CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
  556. qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
  557. s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
  558. s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
  559. s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
  560. return 0;
  561. }
  562. static void spitz_ssp_attach(PXA2xxState *cpu)
  563. {
  564. DeviceState *mux;
  565. DeviceState *dev;
  566. void *bus;
  567. mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
  568. bus = qdev_get_child_bus(mux, "ssi0");
  569. ssi_create_slave(bus, "spitz-lcdtg");
  570. bus = qdev_get_child_bus(mux, "ssi1");
  571. dev = ssi_create_slave(bus, "ads7846");
  572. qdev_connect_gpio_out(dev, 0,
  573. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
  574. bus = qdev_get_child_bus(mux, "ssi2");
  575. max1111 = ssi_create_slave(bus, "max1111");
  576. max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
  577. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  578. max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
  579. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
  580. qdev_get_gpio_in(mux, 0));
  581. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
  582. qdev_get_gpio_in(mux, 1));
  583. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
  584. qdev_get_gpio_in(mux, 2));
  585. }
  586. /* CF Microdrive */
  587. static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
  588. {
  589. PCMCIACardState *md;
  590. BlockDriverState *bs;
  591. DriveInfo *dinfo;
  592. dinfo = drive_get(IF_IDE, 0, 0);
  593. if (!dinfo)
  594. return;
  595. bs = dinfo->bdrv;
  596. if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
  597. md = dscm1xxxx_init(dinfo);
  598. pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
  599. }
  600. }
  601. /* Wm8750 and Max7310 on I2C */
  602. #define AKITA_MAX_ADDR 0x18
  603. #define SPITZ_WM_ADDRL 0x1b
  604. #define SPITZ_WM_ADDRH 0x1a
  605. #define SPITZ_GPIO_WM 5
  606. static void spitz_wm8750_addr(void *opaque, int line, int level)
  607. {
  608. i2c_slave *wm = (i2c_slave *) opaque;
  609. if (level)
  610. i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
  611. else
  612. i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
  613. }
  614. static void spitz_i2c_setup(PXA2xxState *cpu)
  615. {
  616. /* Attach the CPU on one end of our I2C bus. */
  617. i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
  618. DeviceState *wm;
  619. /* Attach a WM8750 to the bus */
  620. wm = i2c_create_slave(bus, "wm8750", 0);
  621. spitz_wm8750_addr(wm, 0, 0);
  622. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
  623. qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
  624. /* .. and to the sound interface. */
  625. cpu->i2s->opaque = wm;
  626. cpu->i2s->codec_out = wm8750_dac_dat;
  627. cpu->i2s->codec_in = wm8750_adc_dat;
  628. wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
  629. }
  630. static void spitz_akita_i2c_setup(PXA2xxState *cpu)
  631. {
  632. /* Attach a Max7310 to Akita I2C bus. */
  633. i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
  634. AKITA_MAX_ADDR);
  635. }
  636. /* Other peripherals */
  637. static void spitz_out_switch(void *opaque, int line, int level)
  638. {
  639. switch (line) {
  640. case 0:
  641. zaurus_printf("Charging %s.\n", level ? "off" : "on");
  642. break;
  643. case 1:
  644. zaurus_printf("Discharging %s.\n", level ? "on" : "off");
  645. break;
  646. case 2:
  647. zaurus_printf("Green LED %s.\n", level ? "on" : "off");
  648. break;
  649. case 3:
  650. zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
  651. break;
  652. case 4:
  653. spitz_bl_bit5(opaque, line, level);
  654. break;
  655. case 5:
  656. spitz_bl_power(opaque, line, level);
  657. break;
  658. case 6:
  659. spitz_adc_temp_on(opaque, line, level);
  660. break;
  661. }
  662. }
  663. #define SPITZ_SCP_LED_GREEN 1
  664. #define SPITZ_SCP_JK_B 2
  665. #define SPITZ_SCP_CHRG_ON 3
  666. #define SPITZ_SCP_MUTE_L 4
  667. #define SPITZ_SCP_MUTE_R 5
  668. #define SPITZ_SCP_CF_POWER 6
  669. #define SPITZ_SCP_LED_ORANGE 7
  670. #define SPITZ_SCP_JK_A 8
  671. #define SPITZ_SCP_ADC_TEMP_ON 9
  672. #define SPITZ_SCP2_IR_ON 1
  673. #define SPITZ_SCP2_AKIN_PULLUP 2
  674. #define SPITZ_SCP2_BACKLIGHT_CONT 7
  675. #define SPITZ_SCP2_BACKLIGHT_ON 8
  676. #define SPITZ_SCP2_MIC_BIAS 9
  677. static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
  678. DeviceState *scp0, DeviceState *scp1)
  679. {
  680. qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
  681. qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
  682. qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
  683. qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
  684. qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
  685. if (scp1) {
  686. qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
  687. qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
  688. }
  689. qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  690. }
  691. #define SPITZ_GPIO_HSYNC 22
  692. #define SPITZ_GPIO_SD_DETECT 9
  693. #define SPITZ_GPIO_SD_WP 81
  694. #define SPITZ_GPIO_ON_RESET 89
  695. #define SPITZ_GPIO_BAT_COVER 90
  696. #define SPITZ_GPIO_CF1_IRQ 105
  697. #define SPITZ_GPIO_CF1_CD 94
  698. #define SPITZ_GPIO_CF2_IRQ 106
  699. #define SPITZ_GPIO_CF2_CD 93
  700. static int spitz_hsync;
  701. static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
  702. {
  703. PXA2xxState *cpu = (PXA2xxState *) opaque;
  704. qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
  705. spitz_hsync ^= 1;
  706. }
  707. static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  708. {
  709. qemu_irq lcd_hsync;
  710. /*
  711. * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
  712. * read to satisfy broken guests that poll-wait for hsync.
  713. * Simulating a real hsync event would be less practical and
  714. * wouldn't guarantee that a guest ever exits the loop.
  715. */
  716. spitz_hsync = 0;
  717. lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
  718. pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
  719. pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
  720. /* MMC/SD host */
  721. pxa2xx_mmci_handlers(cpu->mmc,
  722. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
  723. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
  724. /* Battery lock always closed */
  725. qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
  726. /* Handle reset */
  727. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
  728. /* PCMCIA signals: card's IRQ and Card-Detect */
  729. if (slots >= 1)
  730. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
  731. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
  732. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
  733. if (slots >= 2)
  734. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
  735. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
  736. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
  737. }
  738. /* Board init. */
  739. enum spitz_model_e { spitz, akita, borzoi, terrier };
  740. #define SPITZ_RAM 0x04000000
  741. #define SPITZ_ROM 0x00800000
  742. static struct arm_boot_info spitz_binfo = {
  743. .loader_start = PXA2XX_SDRAM_BASE,
  744. .ram_size = 0x04000000,
  745. };
  746. static void spitz_common_init(ram_addr_t ram_size,
  747. const char *kernel_filename,
  748. const char *kernel_cmdline, const char *initrd_filename,
  749. const char *cpu_model, enum spitz_model_e model, int arm_id)
  750. {
  751. PXA2xxState *cpu;
  752. DeviceState *scp0, *scp1 = NULL;
  753. if (!cpu_model)
  754. cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
  755. /* Setup CPU & memory */
  756. cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
  757. sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
  758. cpu_register_physical_memory(0, SPITZ_ROM,
  759. qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM);
  760. /* Setup peripherals */
  761. spitz_keyboard_register(cpu);
  762. spitz_ssp_attach(cpu);
  763. scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
  764. if (model != akita) {
  765. scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
  766. }
  767. spitz_scoop_gpio_setup(cpu, scp0, scp1);
  768. spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
  769. spitz_i2c_setup(cpu);
  770. if (model == akita)
  771. spitz_akita_i2c_setup(cpu);
  772. if (model == terrier)
  773. /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
  774. spitz_microdrive_attach(cpu, 1);
  775. else if (model != akita)
  776. /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
  777. spitz_microdrive_attach(cpu, 0);
  778. spitz_binfo.kernel_filename = kernel_filename;
  779. spitz_binfo.kernel_cmdline = kernel_cmdline;
  780. spitz_binfo.initrd_filename = initrd_filename;
  781. spitz_binfo.board_id = arm_id;
  782. arm_load_kernel(cpu->env, &spitz_binfo);
  783. sl_bootparam_write(SL_PXA_PARAM_BASE);
  784. }
  785. static void spitz_init(ram_addr_t ram_size,
  786. const char *boot_device,
  787. const char *kernel_filename, const char *kernel_cmdline,
  788. const char *initrd_filename, const char *cpu_model)
  789. {
  790. spitz_common_init(ram_size, kernel_filename,
  791. kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
  792. }
  793. static void borzoi_init(ram_addr_t ram_size,
  794. const char *boot_device,
  795. const char *kernel_filename, const char *kernel_cmdline,
  796. const char *initrd_filename, const char *cpu_model)
  797. {
  798. spitz_common_init(ram_size, kernel_filename,
  799. kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
  800. }
  801. static void akita_init(ram_addr_t ram_size,
  802. const char *boot_device,
  803. const char *kernel_filename, const char *kernel_cmdline,
  804. const char *initrd_filename, const char *cpu_model)
  805. {
  806. spitz_common_init(ram_size, kernel_filename,
  807. kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
  808. }
  809. static void terrier_init(ram_addr_t ram_size,
  810. const char *boot_device,
  811. const char *kernel_filename, const char *kernel_cmdline,
  812. const char *initrd_filename, const char *cpu_model)
  813. {
  814. spitz_common_init(ram_size, kernel_filename,
  815. kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
  816. }
  817. static QEMUMachine akitapda_machine = {
  818. .name = "akita",
  819. .desc = "Akita PDA (PXA270)",
  820. .init = akita_init,
  821. };
  822. static QEMUMachine spitzpda_machine = {
  823. .name = "spitz",
  824. .desc = "Spitz PDA (PXA270)",
  825. .init = spitz_init,
  826. };
  827. static QEMUMachine borzoipda_machine = {
  828. .name = "borzoi",
  829. .desc = "Borzoi PDA (PXA270)",
  830. .init = borzoi_init,
  831. };
  832. static QEMUMachine terrierpda_machine = {
  833. .name = "terrier",
  834. .desc = "Terrier PDA (PXA270)",
  835. .init = terrier_init,
  836. };
  837. static void spitz_machine_init(void)
  838. {
  839. qemu_register_machine(&akitapda_machine);
  840. qemu_register_machine(&spitzpda_machine);
  841. qemu_register_machine(&borzoipda_machine);
  842. qemu_register_machine(&terrierpda_machine);
  843. }
  844. machine_init(spitz_machine_init);
  845. static bool is_version_0(void *opaque, int version_id)
  846. {
  847. return version_id == 0;
  848. }
  849. static VMStateDescription vmstate_sl_nand_info = {
  850. .name = "sl-nand",
  851. .version_id = 0,
  852. .minimum_version_id = 0,
  853. .minimum_version_id_old = 0,
  854. .fields = (VMStateField []) {
  855. VMSTATE_UINT8(ctl, SLNANDState),
  856. VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
  857. VMSTATE_END_OF_LIST(),
  858. },
  859. };
  860. static SysBusDeviceInfo sl_nand_info = {
  861. .init = sl_nand_init,
  862. .qdev.name = "sl-nand",
  863. .qdev.size = sizeof(SLNANDState),
  864. .qdev.vmsd = &vmstate_sl_nand_info,
  865. .qdev.props = (Property []) {
  866. DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
  867. DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
  868. DEFINE_PROP_END_OF_LIST(),
  869. },
  870. };
  871. static VMStateDescription vmstate_spitz_kbd = {
  872. .name = "spitz-keyboard",
  873. .version_id = 1,
  874. .minimum_version_id = 0,
  875. .minimum_version_id_old = 0,
  876. .post_load = spitz_keyboard_post_load,
  877. .fields = (VMStateField []) {
  878. VMSTATE_UINT16(sense_state, SpitzKeyboardState),
  879. VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
  880. VMSTATE_UNUSED_TEST(is_version_0, 5),
  881. VMSTATE_END_OF_LIST(),
  882. },
  883. };
  884. static SysBusDeviceInfo spitz_keyboard_info = {
  885. .init = spitz_keyboard_init,
  886. .qdev.name = "spitz-keyboard",
  887. .qdev.size = sizeof(SpitzKeyboardState),
  888. .qdev.vmsd = &vmstate_spitz_kbd,
  889. .qdev.props = (Property []) {
  890. DEFINE_PROP_END_OF_LIST(),
  891. },
  892. };
  893. static const VMStateDescription vmstate_corgi_ssp_regs = {
  894. .name = "corgi-ssp",
  895. .version_id = 1,
  896. .minimum_version_id = 1,
  897. .minimum_version_id_old = 1,
  898. .fields = (VMStateField []) {
  899. VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
  900. VMSTATE_END_OF_LIST(),
  901. }
  902. };
  903. static SSISlaveInfo corgi_ssp_info = {
  904. .qdev.name = "corgi-ssp",
  905. .qdev.size = sizeof(CorgiSSPState),
  906. .qdev.vmsd = &vmstate_corgi_ssp_regs,
  907. .init = corgi_ssp_init,
  908. .transfer = corgi_ssp_transfer
  909. };
  910. static const VMStateDescription vmstate_spitz_lcdtg_regs = {
  911. .name = "spitz-lcdtg",
  912. .version_id = 1,
  913. .minimum_version_id = 1,
  914. .minimum_version_id_old = 1,
  915. .fields = (VMStateField []) {
  916. VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
  917. VMSTATE_UINT32(bl_power, SpitzLCDTG),
  918. VMSTATE_END_OF_LIST(),
  919. }
  920. };
  921. static SSISlaveInfo spitz_lcdtg_info = {
  922. .qdev.name = "spitz-lcdtg",
  923. .qdev.size = sizeof(SpitzLCDTG),
  924. .qdev.vmsd = &vmstate_spitz_lcdtg_regs,
  925. .init = spitz_lcdtg_init,
  926. .transfer = spitz_lcdtg_transfer
  927. };
  928. static void spitz_register_devices(void)
  929. {
  930. ssi_register_slave(&corgi_ssp_info);
  931. ssi_register_slave(&spitz_lcdtg_info);
  932. sysbus_register_withprop(&spitz_keyboard_info);
  933. sysbus_register_withprop(&sl_nand_info);
  934. }
  935. device_init(spitz_register_devices)