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sh_intc.c 12 KB

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  1. /*
  2. * SuperH interrupt controller module
  3. *
  4. * Copyright (c) 2007 Magnus Damm
  5. * Based on sh_timer.c and arm_timer.c by Paul Brook
  6. * Copyright (c) 2005-2006 CodeSourcery.
  7. *
  8. * This code is licensed under the GPL.
  9. */
  10. #include "sh_intc.h"
  11. #include "hw.h"
  12. #include "sh.h"
  13. //#define DEBUG_INTC
  14. //#define DEBUG_INTC_SOURCES
  15. #define INTC_A7(x) ((x) & 0x1fffffff)
  16. void sh_intc_toggle_source(struct intc_source *source,
  17. int enable_adj, int assert_adj)
  18. {
  19. int enable_changed = 0;
  20. int pending_changed = 0;
  21. int old_pending;
  22. if ((source->enable_count == source->enable_max) && (enable_adj == -1))
  23. enable_changed = -1;
  24. source->enable_count += enable_adj;
  25. if (source->enable_count == source->enable_max)
  26. enable_changed = 1;
  27. source->asserted += assert_adj;
  28. old_pending = source->pending;
  29. source->pending = source->asserted &&
  30. (source->enable_count == source->enable_max);
  31. if (old_pending != source->pending)
  32. pending_changed = 1;
  33. if (pending_changed) {
  34. if (source->pending) {
  35. source->parent->pending++;
  36. if (source->parent->pending == 1)
  37. cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
  38. }
  39. else {
  40. source->parent->pending--;
  41. if (source->parent->pending == 0)
  42. cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
  43. }
  44. }
  45. if (enable_changed || assert_adj || pending_changed) {
  46. #ifdef DEBUG_INTC_SOURCES
  47. printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
  48. source->parent->pending,
  49. source->asserted,
  50. source->enable_count,
  51. source->enable_max,
  52. source->vect,
  53. source->asserted ? "asserted " :
  54. assert_adj ? "deasserted" : "",
  55. enable_changed == 1 ? "enabled " :
  56. enable_changed == -1 ? "disabled " : "",
  57. source->pending ? "pending" : "");
  58. #endif
  59. }
  60. }
  61. static void sh_intc_set_irq (void *opaque, int n, int level)
  62. {
  63. struct intc_desc *desc = opaque;
  64. struct intc_source *source = &(desc->sources[n]);
  65. if (level && !source->asserted)
  66. sh_intc_toggle_source(source, 0, 1);
  67. else if (!level && source->asserted)
  68. sh_intc_toggle_source(source, 0, -1);
  69. }
  70. int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
  71. {
  72. unsigned int i;
  73. /* slow: use a linked lists of pending sources instead */
  74. /* wrong: take interrupt priority into account (one list per priority) */
  75. if (imask == 0x0f) {
  76. return -1; /* FIXME, update code to include priority per source */
  77. }
  78. for (i = 0; i < desc->nr_sources; i++) {
  79. struct intc_source *source = desc->sources + i;
  80. if (source->pending) {
  81. #ifdef DEBUG_INTC_SOURCES
  82. printf("sh_intc: (%d) returning interrupt source 0x%x\n",
  83. desc->pending, source->vect);
  84. #endif
  85. return source->vect;
  86. }
  87. }
  88. abort();
  89. }
  90. #define INTC_MODE_NONE 0
  91. #define INTC_MODE_DUAL_SET 1
  92. #define INTC_MODE_DUAL_CLR 2
  93. #define INTC_MODE_ENABLE_REG 3
  94. #define INTC_MODE_MASK_REG 4
  95. #define INTC_MODE_IS_PRIO 8
  96. static unsigned int sh_intc_mode(unsigned long address,
  97. unsigned long set_reg, unsigned long clr_reg)
  98. {
  99. if ((address != INTC_A7(set_reg)) &&
  100. (address != INTC_A7(clr_reg)))
  101. return INTC_MODE_NONE;
  102. if (set_reg && clr_reg) {
  103. if (address == INTC_A7(set_reg))
  104. return INTC_MODE_DUAL_SET;
  105. else
  106. return INTC_MODE_DUAL_CLR;
  107. }
  108. if (set_reg)
  109. return INTC_MODE_ENABLE_REG;
  110. else
  111. return INTC_MODE_MASK_REG;
  112. }
  113. static void sh_intc_locate(struct intc_desc *desc,
  114. unsigned long address,
  115. unsigned long **datap,
  116. intc_enum **enums,
  117. unsigned int *first,
  118. unsigned int *width,
  119. unsigned int *modep)
  120. {
  121. unsigned int i, mode;
  122. /* this is slow but works for now */
  123. if (desc->mask_regs) {
  124. for (i = 0; i < desc->nr_mask_regs; i++) {
  125. struct intc_mask_reg *mr = desc->mask_regs + i;
  126. mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
  127. if (mode == INTC_MODE_NONE)
  128. continue;
  129. *modep = mode;
  130. *datap = &mr->value;
  131. *enums = mr->enum_ids;
  132. *first = mr->reg_width - 1;
  133. *width = 1;
  134. return;
  135. }
  136. }
  137. if (desc->prio_regs) {
  138. for (i = 0; i < desc->nr_prio_regs; i++) {
  139. struct intc_prio_reg *pr = desc->prio_regs + i;
  140. mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
  141. if (mode == INTC_MODE_NONE)
  142. continue;
  143. *modep = mode | INTC_MODE_IS_PRIO;
  144. *datap = &pr->value;
  145. *enums = pr->enum_ids;
  146. *first = (pr->reg_width / pr->field_width) - 1;
  147. *width = pr->field_width;
  148. return;
  149. }
  150. }
  151. abort();
  152. }
  153. static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
  154. int enable, int is_group)
  155. {
  156. struct intc_source *source = desc->sources + id;
  157. if (!id)
  158. return;
  159. if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
  160. #ifdef DEBUG_INTC_SOURCES
  161. printf("sh_intc: reserved interrupt source %d modified\n", id);
  162. #endif
  163. return;
  164. }
  165. if (source->vect)
  166. sh_intc_toggle_source(source, enable ? 1 : -1, 0);
  167. #ifdef DEBUG_INTC
  168. else {
  169. printf("setting interrupt group %d to %d\n", id, !!enable);
  170. }
  171. #endif
  172. if ((is_group || !source->vect) && source->next_enum_id) {
  173. sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
  174. }
  175. #ifdef DEBUG_INTC
  176. if (!source->vect) {
  177. printf("setting interrupt group %d to %d - done\n", id, !!enable);
  178. }
  179. #endif
  180. }
  181. static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
  182. {
  183. struct intc_desc *desc = opaque;
  184. intc_enum *enum_ids = NULL;
  185. unsigned int first = 0;
  186. unsigned int width = 0;
  187. unsigned int mode = 0;
  188. unsigned long *valuep;
  189. #ifdef DEBUG_INTC
  190. printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
  191. #endif
  192. sh_intc_locate(desc, (unsigned long)offset, &valuep,
  193. &enum_ids, &first, &width, &mode);
  194. return *valuep;
  195. }
  196. static void sh_intc_write(void *opaque, target_phys_addr_t offset,
  197. uint32_t value)
  198. {
  199. struct intc_desc *desc = opaque;
  200. intc_enum *enum_ids = NULL;
  201. unsigned int first = 0;
  202. unsigned int width = 0;
  203. unsigned int mode = 0;
  204. unsigned int k;
  205. unsigned long *valuep;
  206. unsigned long mask;
  207. #ifdef DEBUG_INTC
  208. printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
  209. #endif
  210. sh_intc_locate(desc, (unsigned long)offset, &valuep,
  211. &enum_ids, &first, &width, &mode);
  212. switch (mode) {
  213. case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
  214. case INTC_MODE_DUAL_SET: value |= *valuep; break;
  215. case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
  216. default: abort();
  217. }
  218. for (k = 0; k <= first; k++) {
  219. mask = ((1 << width) - 1) << ((first - k) * width);
  220. if ((*valuep & mask) == (value & mask))
  221. continue;
  222. #if 0
  223. printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
  224. k, first, enum_ids[k], (unsigned int)mask);
  225. #endif
  226. sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
  227. }
  228. *valuep = value;
  229. #ifdef DEBUG_INTC
  230. printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
  231. #endif
  232. }
  233. static CPUReadMemoryFunc * const sh_intc_readfn[] = {
  234. sh_intc_read,
  235. sh_intc_read,
  236. sh_intc_read
  237. };
  238. static CPUWriteMemoryFunc * const sh_intc_writefn[] = {
  239. sh_intc_write,
  240. sh_intc_write,
  241. sh_intc_write
  242. };
  243. struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
  244. {
  245. if (id)
  246. return desc->sources + id;
  247. return NULL;
  248. }
  249. static void sh_intc_register(struct intc_desc *desc,
  250. unsigned long address)
  251. {
  252. if (address) {
  253. cpu_register_physical_memory_offset(P4ADDR(address), 4,
  254. desc->iomemtype, INTC_A7(address));
  255. cpu_register_physical_memory_offset(A7ADDR(address), 4,
  256. desc->iomemtype, INTC_A7(address));
  257. }
  258. }
  259. static void sh_intc_register_source(struct intc_desc *desc,
  260. intc_enum source,
  261. struct intc_group *groups,
  262. int nr_groups)
  263. {
  264. unsigned int i, k;
  265. struct intc_source *s;
  266. if (desc->mask_regs) {
  267. for (i = 0; i < desc->nr_mask_regs; i++) {
  268. struct intc_mask_reg *mr = desc->mask_regs + i;
  269. for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
  270. if (mr->enum_ids[k] != source)
  271. continue;
  272. s = sh_intc_source(desc, mr->enum_ids[k]);
  273. if (s)
  274. s->enable_max++;
  275. }
  276. }
  277. }
  278. if (desc->prio_regs) {
  279. for (i = 0; i < desc->nr_prio_regs; i++) {
  280. struct intc_prio_reg *pr = desc->prio_regs + i;
  281. for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
  282. if (pr->enum_ids[k] != source)
  283. continue;
  284. s = sh_intc_source(desc, pr->enum_ids[k]);
  285. if (s)
  286. s->enable_max++;
  287. }
  288. }
  289. }
  290. if (groups) {
  291. for (i = 0; i < nr_groups; i++) {
  292. struct intc_group *gr = groups + i;
  293. for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
  294. if (gr->enum_ids[k] != source)
  295. continue;
  296. s = sh_intc_source(desc, gr->enum_ids[k]);
  297. if (s)
  298. s->enable_max++;
  299. }
  300. }
  301. }
  302. }
  303. void sh_intc_register_sources(struct intc_desc *desc,
  304. struct intc_vect *vectors,
  305. int nr_vectors,
  306. struct intc_group *groups,
  307. int nr_groups)
  308. {
  309. unsigned int i, k;
  310. struct intc_source *s;
  311. for (i = 0; i < nr_vectors; i++) {
  312. struct intc_vect *vect = vectors + i;
  313. sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
  314. s = sh_intc_source(desc, vect->enum_id);
  315. if (s)
  316. s->vect = vect->vect;
  317. #ifdef DEBUG_INTC_SOURCES
  318. printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
  319. vect->enum_id, s->vect, s->enable_count, s->enable_max);
  320. #endif
  321. }
  322. if (groups) {
  323. for (i = 0; i < nr_groups; i++) {
  324. struct intc_group *gr = groups + i;
  325. s = sh_intc_source(desc, gr->enum_id);
  326. s->next_enum_id = gr->enum_ids[0];
  327. for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
  328. if (!gr->enum_ids[k])
  329. continue;
  330. s = sh_intc_source(desc, gr->enum_ids[k - 1]);
  331. s->next_enum_id = gr->enum_ids[k];
  332. }
  333. #ifdef DEBUG_INTC_SOURCES
  334. printf("sh_intc: registered group %d (%d/%d)\n",
  335. gr->enum_id, s->enable_count, s->enable_max);
  336. #endif
  337. }
  338. }
  339. }
  340. int sh_intc_init(struct intc_desc *desc,
  341. int nr_sources,
  342. struct intc_mask_reg *mask_regs,
  343. int nr_mask_regs,
  344. struct intc_prio_reg *prio_regs,
  345. int nr_prio_regs)
  346. {
  347. unsigned int i;
  348. desc->pending = 0;
  349. desc->nr_sources = nr_sources;
  350. desc->mask_regs = mask_regs;
  351. desc->nr_mask_regs = nr_mask_regs;
  352. desc->prio_regs = prio_regs;
  353. desc->nr_prio_regs = nr_prio_regs;
  354. i = sizeof(struct intc_source) * nr_sources;
  355. desc->sources = qemu_mallocz(i);
  356. for (i = 0; i < desc->nr_sources; i++) {
  357. struct intc_source *source = desc->sources + i;
  358. source->parent = desc;
  359. }
  360. desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
  361. desc->iomemtype = cpu_register_io_memory(sh_intc_readfn,
  362. sh_intc_writefn, desc,
  363. DEVICE_NATIVE_ENDIAN);
  364. if (desc->mask_regs) {
  365. for (i = 0; i < desc->nr_mask_regs; i++) {
  366. struct intc_mask_reg *mr = desc->mask_regs + i;
  367. sh_intc_register(desc, mr->set_reg);
  368. sh_intc_register(desc, mr->clr_reg);
  369. }
  370. }
  371. if (desc->prio_regs) {
  372. for (i = 0; i < desc->nr_prio_regs; i++) {
  373. struct intc_prio_reg *pr = desc->prio_regs + i;
  374. sh_intc_register(desc, pr->set_reg);
  375. sh_intc_register(desc, pr->clr_reg);
  376. }
  377. }
  378. return 0;
  379. }
  380. /* Assert level <n> IRL interrupt.
  381. 0:deassert. 1:lowest priority,... 15:highest priority. */
  382. void sh_intc_set_irl(void *opaque, int n, int level)
  383. {
  384. struct intc_source *s = opaque;
  385. int i, irl = level ^ 15;
  386. for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
  387. if (i == irl)
  388. sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
  389. else
  390. if (s->asserted)
  391. sh_intc_toggle_source(s, 0, -1);
  392. }
  393. }