omap_lcdc.c 12 KB

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  1. /*
  2. * OMAP LCD controller.
  3. *
  4. * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "hw.h"
  20. #include "console.h"
  21. #include "omap.h"
  22. #include "framebuffer.h"
  23. struct omap_lcd_panel_s {
  24. qemu_irq irq;
  25. DisplayState *state;
  26. ram_addr_t imif_base;
  27. ram_addr_t emiff_base;
  28. int plm;
  29. int tft;
  30. int mono;
  31. int enable;
  32. int width;
  33. int height;
  34. int interrupts;
  35. uint32_t timing[3];
  36. uint32_t subpanel;
  37. uint32_t ctrl;
  38. struct omap_dma_lcd_channel_s *dma;
  39. uint16_t palette[256];
  40. int palette_done;
  41. int frame_done;
  42. int invalidate;
  43. int sync_error;
  44. };
  45. static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
  46. {
  47. if (s->frame_done && (s->interrupts & 1)) {
  48. qemu_irq_raise(s->irq);
  49. return;
  50. }
  51. if (s->palette_done && (s->interrupts & 2)) {
  52. qemu_irq_raise(s->irq);
  53. return;
  54. }
  55. if (s->sync_error) {
  56. qemu_irq_raise(s->irq);
  57. return;
  58. }
  59. qemu_irq_lower(s->irq);
  60. }
  61. #include "pixel_ops.h"
  62. #define draw_line_func drawfn
  63. #define DEPTH 8
  64. #include "omap_lcd_template.h"
  65. #define DEPTH 15
  66. #include "omap_lcd_template.h"
  67. #define DEPTH 16
  68. #include "omap_lcd_template.h"
  69. #define DEPTH 32
  70. #include "omap_lcd_template.h"
  71. static draw_line_func draw_line_table2[33] = {
  72. [0 ... 32] = NULL,
  73. [8] = draw_line2_8,
  74. [15] = draw_line2_15,
  75. [16] = draw_line2_16,
  76. [32] = draw_line2_32,
  77. }, draw_line_table4[33] = {
  78. [0 ... 32] = NULL,
  79. [8] = draw_line4_8,
  80. [15] = draw_line4_15,
  81. [16] = draw_line4_16,
  82. [32] = draw_line4_32,
  83. }, draw_line_table8[33] = {
  84. [0 ... 32] = NULL,
  85. [8] = draw_line8_8,
  86. [15] = draw_line8_15,
  87. [16] = draw_line8_16,
  88. [32] = draw_line8_32,
  89. }, draw_line_table12[33] = {
  90. [0 ... 32] = NULL,
  91. [8] = draw_line12_8,
  92. [15] = draw_line12_15,
  93. [16] = draw_line12_16,
  94. [32] = draw_line12_32,
  95. }, draw_line_table16[33] = {
  96. [0 ... 32] = NULL,
  97. [8] = draw_line16_8,
  98. [15] = draw_line16_15,
  99. [16] = draw_line16_16,
  100. [32] = draw_line16_32,
  101. };
  102. static void omap_update_display(void *opaque)
  103. {
  104. struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
  105. draw_line_func draw_line;
  106. int size, height, first, last;
  107. int width, linesize, step, bpp, frame_offset;
  108. target_phys_addr_t frame_base;
  109. if (!omap_lcd || omap_lcd->plm == 1 ||
  110. !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
  111. return;
  112. frame_offset = 0;
  113. if (omap_lcd->plm != 2) {
  114. cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[
  115. omap_lcd->dma->current_frame],
  116. (void *)omap_lcd->palette, 0x200);
  117. switch (omap_lcd->palette[0] >> 12 & 7) {
  118. case 3 ... 7:
  119. frame_offset += 0x200;
  120. break;
  121. default:
  122. frame_offset += 0x20;
  123. }
  124. }
  125. /* Colour depth */
  126. switch ((omap_lcd->palette[0] >> 12) & 7) {
  127. case 1:
  128. draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)];
  129. bpp = 2;
  130. break;
  131. case 2:
  132. draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)];
  133. bpp = 4;
  134. break;
  135. case 3:
  136. draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)];
  137. bpp = 8;
  138. break;
  139. case 4 ... 7:
  140. if (!omap_lcd->tft)
  141. draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)];
  142. else
  143. draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)];
  144. bpp = 16;
  145. break;
  146. default:
  147. /* Unsupported at the moment. */
  148. return;
  149. }
  150. /* Resolution */
  151. width = omap_lcd->width;
  152. if (width != ds_get_width(omap_lcd->state) ||
  153. omap_lcd->height != ds_get_height(omap_lcd->state)) {
  154. qemu_console_resize(omap_lcd->state,
  155. omap_lcd->width, omap_lcd->height);
  156. omap_lcd->invalidate = 1;
  157. }
  158. if (omap_lcd->dma->current_frame == 0)
  159. size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
  160. else
  161. size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
  162. if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
  163. omap_lcd->sync_error = 1;
  164. omap_lcd_interrupts(omap_lcd);
  165. omap_lcd->enable = 0;
  166. return;
  167. }
  168. /* Content */
  169. frame_base = omap_lcd->dma->phys_framebuffer[
  170. omap_lcd->dma->current_frame] + frame_offset;
  171. omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
  172. if (omap_lcd->dma->interrupts & 1)
  173. qemu_irq_raise(omap_lcd->dma->irq);
  174. if (omap_lcd->dma->dual)
  175. omap_lcd->dma->current_frame ^= 1;
  176. if (!ds_get_bits_per_pixel(omap_lcd->state))
  177. return;
  178. first = 0;
  179. height = omap_lcd->height;
  180. if (omap_lcd->subpanel & (1 << 31)) {
  181. if (omap_lcd->subpanel & (1 << 29))
  182. first = (omap_lcd->subpanel >> 16) & 0x3ff;
  183. else
  184. height = (omap_lcd->subpanel >> 16) & 0x3ff;
  185. /* TODO: fill the rest of the panel with DPD */
  186. }
  187. step = width * bpp >> 3;
  188. linesize = ds_get_linesize(omap_lcd->state);
  189. framebuffer_update_display(omap_lcd->state,
  190. frame_base, width, height,
  191. step, linesize, 0,
  192. omap_lcd->invalidate,
  193. draw_line, omap_lcd->palette,
  194. &first, &last);
  195. if (first >= 0) {
  196. dpy_update(omap_lcd->state, 0, first, width, last - first + 1);
  197. }
  198. omap_lcd->invalidate = 0;
  199. }
  200. static int ppm_save(const char *filename, uint8_t *data,
  201. int w, int h, int linesize)
  202. {
  203. FILE *f;
  204. uint8_t *d, *d1;
  205. unsigned int v;
  206. int y, x, bpp;
  207. f = fopen(filename, "wb");
  208. if (!f)
  209. return -1;
  210. fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
  211. d1 = data;
  212. bpp = linesize / w;
  213. for (y = 0; y < h; y ++) {
  214. d = d1;
  215. for (x = 0; x < w; x ++) {
  216. v = *(uint32_t *) d;
  217. switch (bpp) {
  218. case 2:
  219. fputc((v >> 8) & 0xf8, f);
  220. fputc((v >> 3) & 0xfc, f);
  221. fputc((v << 3) & 0xf8, f);
  222. break;
  223. case 3:
  224. case 4:
  225. default:
  226. fputc((v >> 16) & 0xff, f);
  227. fputc((v >> 8) & 0xff, f);
  228. fputc((v) & 0xff, f);
  229. break;
  230. }
  231. d += bpp;
  232. }
  233. d1 += linesize;
  234. }
  235. fclose(f);
  236. return 0;
  237. }
  238. static void omap_screen_dump(void *opaque, const char *filename) {
  239. struct omap_lcd_panel_s *omap_lcd = opaque;
  240. omap_update_display(opaque);
  241. if (omap_lcd && ds_get_data(omap_lcd->state))
  242. ppm_save(filename, ds_get_data(omap_lcd->state),
  243. omap_lcd->width, omap_lcd->height,
  244. ds_get_linesize(omap_lcd->state));
  245. }
  246. static void omap_invalidate_display(void *opaque) {
  247. struct omap_lcd_panel_s *omap_lcd = opaque;
  248. omap_lcd->invalidate = 1;
  249. }
  250. static void omap_lcd_update(struct omap_lcd_panel_s *s) {
  251. if (!s->enable) {
  252. s->dma->current_frame = -1;
  253. s->sync_error = 0;
  254. if (s->plm != 1)
  255. s->frame_done = 1;
  256. omap_lcd_interrupts(s);
  257. return;
  258. }
  259. if (s->dma->current_frame == -1) {
  260. s->frame_done = 0;
  261. s->palette_done = 0;
  262. s->dma->current_frame = 0;
  263. }
  264. if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
  265. s->dma->src_f1_top) ||
  266. !s->dma->mpu->port[
  267. s->dma->src].addr_valid(s->dma->mpu,
  268. s->dma->src_f1_bottom) ||
  269. (s->dma->dual &&
  270. (!s->dma->mpu->port[
  271. s->dma->src].addr_valid(s->dma->mpu,
  272. s->dma->src_f2_top) ||
  273. !s->dma->mpu->port[
  274. s->dma->src].addr_valid(s->dma->mpu,
  275. s->dma->src_f2_bottom)))) {
  276. s->dma->condition |= 1 << 2;
  277. if (s->dma->interrupts & (1 << 1))
  278. qemu_irq_raise(s->dma->irq);
  279. s->enable = 0;
  280. return;
  281. }
  282. s->dma->phys_framebuffer[0] = s->dma->src_f1_top;
  283. s->dma->phys_framebuffer[1] = s->dma->src_f2_top;
  284. if (s->plm != 2 && !s->palette_done) {
  285. cpu_physical_memory_read(
  286. s->dma->phys_framebuffer[s->dma->current_frame],
  287. (void *)s->palette, 0x200);
  288. s->palette_done = 1;
  289. omap_lcd_interrupts(s);
  290. }
  291. }
  292. static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
  293. {
  294. struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
  295. switch (addr) {
  296. case 0x00: /* LCD_CONTROL */
  297. return (s->tft << 23) | (s->plm << 20) |
  298. (s->tft << 7) | (s->interrupts << 3) |
  299. (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
  300. case 0x04: /* LCD_TIMING0 */
  301. return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
  302. case 0x08: /* LCD_TIMING1 */
  303. return (s->timing[1] << 10) | (s->height - 1);
  304. case 0x0c: /* LCD_TIMING2 */
  305. return s->timing[2] | 0xfc000000;
  306. case 0x10: /* LCD_STATUS */
  307. return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
  308. case 0x14: /* LCD_SUBPANEL */
  309. return s->subpanel;
  310. default:
  311. break;
  312. }
  313. OMAP_BAD_REG(addr);
  314. return 0;
  315. }
  316. static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
  317. uint32_t value)
  318. {
  319. struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
  320. switch (addr) {
  321. case 0x00: /* LCD_CONTROL */
  322. s->plm = (value >> 20) & 3;
  323. s->tft = (value >> 7) & 1;
  324. s->interrupts = (value >> 3) & 3;
  325. s->mono = (value >> 1) & 1;
  326. s->ctrl = value & 0x01cff300;
  327. if (s->enable != (value & 1)) {
  328. s->enable = value & 1;
  329. omap_lcd_update(s);
  330. }
  331. break;
  332. case 0x04: /* LCD_TIMING0 */
  333. s->timing[0] = value >> 10;
  334. s->width = (value & 0x3ff) + 1;
  335. break;
  336. case 0x08: /* LCD_TIMING1 */
  337. s->timing[1] = value >> 10;
  338. s->height = (value & 0x3ff) + 1;
  339. break;
  340. case 0x0c: /* LCD_TIMING2 */
  341. s->timing[2] = value;
  342. break;
  343. case 0x10: /* LCD_STATUS */
  344. break;
  345. case 0x14: /* LCD_SUBPANEL */
  346. s->subpanel = value & 0xa1ffffff;
  347. break;
  348. default:
  349. OMAP_BAD_REG(addr);
  350. }
  351. }
  352. static CPUReadMemoryFunc * const omap_lcdc_readfn[] = {
  353. omap_lcdc_read,
  354. omap_lcdc_read,
  355. omap_lcdc_read,
  356. };
  357. static CPUWriteMemoryFunc * const omap_lcdc_writefn[] = {
  358. omap_lcdc_write,
  359. omap_lcdc_write,
  360. omap_lcdc_write,
  361. };
  362. void omap_lcdc_reset(struct omap_lcd_panel_s *s)
  363. {
  364. s->dma->current_frame = -1;
  365. s->plm = 0;
  366. s->tft = 0;
  367. s->mono = 0;
  368. s->enable = 0;
  369. s->width = 0;
  370. s->height = 0;
  371. s->interrupts = 0;
  372. s->timing[0] = 0;
  373. s->timing[1] = 0;
  374. s->timing[2] = 0;
  375. s->subpanel = 0;
  376. s->palette_done = 0;
  377. s->frame_done = 0;
  378. s->sync_error = 0;
  379. s->invalidate = 1;
  380. s->subpanel = 0;
  381. s->ctrl = 0;
  382. }
  383. struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
  384. struct omap_dma_lcd_channel_s *dma,
  385. ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
  386. {
  387. int iomemtype;
  388. struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
  389. qemu_mallocz(sizeof(struct omap_lcd_panel_s));
  390. s->irq = irq;
  391. s->dma = dma;
  392. s->imif_base = imif_base;
  393. s->emiff_base = emiff_base;
  394. omap_lcdc_reset(s);
  395. iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
  396. omap_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
  397. cpu_register_physical_memory(base, 0x100, iomemtype);
  398. s->state = graphic_console_init(omap_update_display,
  399. omap_invalidate_display,
  400. omap_screen_dump, NULL, s);
  401. return s;
  402. }