omap_dma.c 59 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082
  1. /*
  2. * TI OMAP DMA gigacell.
  3. *
  4. * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
  5. * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include "qemu-common.h"
  21. #include "qemu-timer.h"
  22. #include "omap.h"
  23. #include "irq.h"
  24. #include "soc_dma.h"
  25. struct omap_dma_channel_s {
  26. /* transfer data */
  27. int burst[2];
  28. int pack[2];
  29. int endian[2];
  30. int endian_lock[2];
  31. int translate[2];
  32. enum omap_dma_port port[2];
  33. target_phys_addr_t addr[2];
  34. omap_dma_addressing_t mode[2];
  35. uint32_t elements;
  36. uint16_t frames;
  37. int32_t frame_index[2];
  38. int16_t element_index[2];
  39. int data_type;
  40. /* transfer type */
  41. int transparent_copy;
  42. int constant_fill;
  43. uint32_t color;
  44. int prefetch;
  45. /* auto init and linked channel data */
  46. int end_prog;
  47. int repeat;
  48. int auto_init;
  49. int link_enabled;
  50. int link_next_ch;
  51. /* interruption data */
  52. int interrupts;
  53. int status;
  54. int cstatus;
  55. /* state data */
  56. int active;
  57. int enable;
  58. int sync;
  59. int src_sync;
  60. int pending_request;
  61. int waiting_end_prog;
  62. uint16_t cpc;
  63. int set_update;
  64. /* sync type */
  65. int fs;
  66. int bs;
  67. /* compatibility */
  68. int omap_3_1_compatible_disable;
  69. qemu_irq irq;
  70. struct omap_dma_channel_s *sibling;
  71. struct omap_dma_reg_set_s {
  72. target_phys_addr_t src, dest;
  73. int frame;
  74. int element;
  75. int pck_element;
  76. int frame_delta[2];
  77. int elem_delta[2];
  78. int frames;
  79. int elements;
  80. int pck_elements;
  81. } active_set;
  82. struct soc_dma_ch_s *dma;
  83. /* unused parameters */
  84. int write_mode;
  85. int priority;
  86. int interleave_disabled;
  87. int type;
  88. int suspend;
  89. int buf_disable;
  90. };
  91. struct omap_dma_s {
  92. struct soc_dma_s *dma;
  93. struct omap_mpu_state_s *mpu;
  94. omap_clk clk;
  95. qemu_irq irq[4];
  96. void (*intr_update)(struct omap_dma_s *s);
  97. enum omap_dma_model model;
  98. int omap_3_1_mapping_disabled;
  99. uint32_t gcr;
  100. uint32_t ocp;
  101. uint32_t caps[5];
  102. uint32_t irqen[4];
  103. uint32_t irqstat[4];
  104. int chans;
  105. struct omap_dma_channel_s ch[32];
  106. struct omap_dma_lcd_channel_s lcd_ch;
  107. };
  108. /* Interrupts */
  109. #define TIMEOUT_INTR (1 << 0)
  110. #define EVENT_DROP_INTR (1 << 1)
  111. #define HALF_FRAME_INTR (1 << 2)
  112. #define END_FRAME_INTR (1 << 3)
  113. #define LAST_FRAME_INTR (1 << 4)
  114. #define END_BLOCK_INTR (1 << 5)
  115. #define SYNC (1 << 6)
  116. #define END_PKT_INTR (1 << 7)
  117. #define TRANS_ERR_INTR (1 << 8)
  118. #define MISALIGN_INTR (1 << 11)
  119. static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
  120. {
  121. return s->intr_update(s);
  122. }
  123. static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
  124. {
  125. struct omap_dma_reg_set_s *a = &ch->active_set;
  126. int i, normal;
  127. int omap_3_1 = !ch->omap_3_1_compatible_disable;
  128. /*
  129. * TODO: verify address ranges and alignment
  130. * TODO: port endianness
  131. */
  132. a->src = ch->addr[0];
  133. a->dest = ch->addr[1];
  134. a->frames = ch->frames;
  135. a->elements = ch->elements;
  136. a->pck_elements = ch->frame_index[!ch->src_sync];
  137. a->frame = 0;
  138. a->element = 0;
  139. a->pck_element = 0;
  140. if (unlikely(!ch->elements || !ch->frames)) {
  141. printf("%s: bad DMA request\n", __FUNCTION__);
  142. return;
  143. }
  144. for (i = 0; i < 2; i ++)
  145. switch (ch->mode[i]) {
  146. case constant:
  147. a->elem_delta[i] = 0;
  148. a->frame_delta[i] = 0;
  149. break;
  150. case post_incremented:
  151. a->elem_delta[i] = ch->data_type;
  152. a->frame_delta[i] = 0;
  153. break;
  154. case single_index:
  155. a->elem_delta[i] = ch->data_type +
  156. ch->element_index[omap_3_1 ? 0 : i] - 1;
  157. a->frame_delta[i] = 0;
  158. break;
  159. case double_index:
  160. a->elem_delta[i] = ch->data_type +
  161. ch->element_index[omap_3_1 ? 0 : i] - 1;
  162. a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
  163. ch->element_index[omap_3_1 ? 0 : i];
  164. break;
  165. default:
  166. break;
  167. }
  168. normal = !ch->transparent_copy && !ch->constant_fill &&
  169. /* FIFO is big-endian so either (ch->endian[n] == 1) OR
  170. * (ch->endian_lock[n] == 1) mean no endianism conversion. */
  171. (ch->endian[0] | ch->endian_lock[0]) ==
  172. (ch->endian[1] | ch->endian_lock[1]);
  173. for (i = 0; i < 2; i ++) {
  174. /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
  175. * limit min_elems in omap_dma_transfer_setup to the nearest frame
  176. * end. */
  177. if (!a->elem_delta[i] && normal &&
  178. (a->frames == 1 || !a->frame_delta[i]))
  179. ch->dma->type[i] = soc_dma_access_const;
  180. else if (a->elem_delta[i] == ch->data_type && normal &&
  181. (a->frames == 1 || !a->frame_delta[i]))
  182. ch->dma->type[i] = soc_dma_access_linear;
  183. else
  184. ch->dma->type[i] = soc_dma_access_other;
  185. ch->dma->vaddr[i] = ch->addr[i];
  186. }
  187. soc_dma_ch_update(ch->dma);
  188. }
  189. static void omap_dma_activate_channel(struct omap_dma_s *s,
  190. struct omap_dma_channel_s *ch)
  191. {
  192. if (!ch->active) {
  193. if (ch->set_update) {
  194. /* It's not clear when the active set is supposed to be
  195. * loaded from registers. We're already loading it when the
  196. * channel is enabled, and for some guests this is not enough
  197. * but that may be also because of a race condition (no
  198. * delays in qemu) in the guest code, which we're just
  199. * working around here. */
  200. omap_dma_channel_load(ch);
  201. ch->set_update = 0;
  202. }
  203. ch->active = 1;
  204. soc_dma_set_request(ch->dma, 1);
  205. if (ch->sync)
  206. ch->status |= SYNC;
  207. }
  208. }
  209. static void omap_dma_deactivate_channel(struct omap_dma_s *s,
  210. struct omap_dma_channel_s *ch)
  211. {
  212. /* Update cpc */
  213. ch->cpc = ch->active_set.dest & 0xffff;
  214. if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
  215. /* Don't deactivate the channel */
  216. ch->pending_request = 0;
  217. return;
  218. }
  219. /* Don't deactive the channel if it is synchronized and the DMA request is
  220. active */
  221. if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
  222. return;
  223. if (ch->active) {
  224. ch->active = 0;
  225. ch->status &= ~SYNC;
  226. soc_dma_set_request(ch->dma, 0);
  227. }
  228. }
  229. static void omap_dma_enable_channel(struct omap_dma_s *s,
  230. struct omap_dma_channel_s *ch)
  231. {
  232. if (!ch->enable) {
  233. ch->enable = 1;
  234. ch->waiting_end_prog = 0;
  235. omap_dma_channel_load(ch);
  236. /* TODO: theoretically if ch->sync && ch->prefetch &&
  237. * !s->dma->drqbmp[ch->sync], we should also activate and fetch
  238. * from source and then stall until signalled. */
  239. if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
  240. omap_dma_activate_channel(s, ch);
  241. }
  242. }
  243. static void omap_dma_disable_channel(struct omap_dma_s *s,
  244. struct omap_dma_channel_s *ch)
  245. {
  246. if (ch->enable) {
  247. ch->enable = 0;
  248. /* Discard any pending request */
  249. ch->pending_request = 0;
  250. omap_dma_deactivate_channel(s, ch);
  251. }
  252. }
  253. static void omap_dma_channel_end_prog(struct omap_dma_s *s,
  254. struct omap_dma_channel_s *ch)
  255. {
  256. if (ch->waiting_end_prog) {
  257. ch->waiting_end_prog = 0;
  258. if (!ch->sync || ch->pending_request) {
  259. ch->pending_request = 0;
  260. omap_dma_activate_channel(s, ch);
  261. }
  262. }
  263. }
  264. static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
  265. {
  266. struct omap_dma_channel_s *ch = s->ch;
  267. /* First three interrupts are shared between two channels each. */
  268. if (ch[0].status | ch[6].status)
  269. qemu_irq_raise(ch[0].irq);
  270. if (ch[1].status | ch[7].status)
  271. qemu_irq_raise(ch[1].irq);
  272. if (ch[2].status | ch[8].status)
  273. qemu_irq_raise(ch[2].irq);
  274. if (ch[3].status)
  275. qemu_irq_raise(ch[3].irq);
  276. if (ch[4].status)
  277. qemu_irq_raise(ch[4].irq);
  278. if (ch[5].status)
  279. qemu_irq_raise(ch[5].irq);
  280. }
  281. static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
  282. {
  283. struct omap_dma_channel_s *ch = s->ch;
  284. int i;
  285. for (i = s->chans; i; ch ++, i --)
  286. if (ch->status)
  287. qemu_irq_raise(ch->irq);
  288. }
  289. static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
  290. {
  291. s->omap_3_1_mapping_disabled = 0;
  292. s->chans = 9;
  293. s->intr_update = omap_dma_interrupts_3_1_update;
  294. }
  295. static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
  296. {
  297. s->omap_3_1_mapping_disabled = 1;
  298. s->chans = 16;
  299. s->intr_update = omap_dma_interrupts_3_2_update;
  300. }
  301. static void omap_dma_process_request(struct omap_dma_s *s, int request)
  302. {
  303. int channel;
  304. int drop_event = 0;
  305. struct omap_dma_channel_s *ch = s->ch;
  306. for (channel = 0; channel < s->chans; channel ++, ch ++) {
  307. if (ch->enable && ch->sync == request) {
  308. if (!ch->active)
  309. omap_dma_activate_channel(s, ch);
  310. else if (!ch->pending_request)
  311. ch->pending_request = 1;
  312. else {
  313. /* Request collision */
  314. /* Second request received while processing other request */
  315. ch->status |= EVENT_DROP_INTR;
  316. drop_event = 1;
  317. }
  318. }
  319. }
  320. if (drop_event)
  321. omap_dma_interrupts_update(s);
  322. }
  323. static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
  324. {
  325. uint8_t value[4];
  326. struct omap_dma_channel_s *ch = dma->opaque;
  327. struct omap_dma_reg_set_s *a = &ch->active_set;
  328. int bytes = dma->bytes;
  329. #ifdef MULTI_REQ
  330. uint16_t status = ch->status;
  331. #endif
  332. do {
  333. /* Transfer a single element */
  334. /* FIXME: check the endianness */
  335. if (!ch->constant_fill)
  336. cpu_physical_memory_read(a->src, value, ch->data_type);
  337. else
  338. *(uint32_t *) value = ch->color;
  339. if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
  340. cpu_physical_memory_write(a->dest, value, ch->data_type);
  341. a->src += a->elem_delta[0];
  342. a->dest += a->elem_delta[1];
  343. a->element ++;
  344. #ifndef MULTI_REQ
  345. if (a->element == a->elements) {
  346. /* End of Frame */
  347. a->element = 0;
  348. a->src += a->frame_delta[0];
  349. a->dest += a->frame_delta[1];
  350. a->frame ++;
  351. /* If the channel is async, update cpc */
  352. if (!ch->sync)
  353. ch->cpc = a->dest & 0xffff;
  354. }
  355. } while ((bytes -= ch->data_type));
  356. #else
  357. /* If the channel is element synchronized, deactivate it */
  358. if (ch->sync && !ch->fs && !ch->bs)
  359. omap_dma_deactivate_channel(s, ch);
  360. /* If it is the last frame, set the LAST_FRAME interrupt */
  361. if (a->element == 1 && a->frame == a->frames - 1)
  362. if (ch->interrupts & LAST_FRAME_INTR)
  363. ch->status |= LAST_FRAME_INTR;
  364. /* If the half of the frame was reached, set the HALF_FRAME
  365. interrupt */
  366. if (a->element == (a->elements >> 1))
  367. if (ch->interrupts & HALF_FRAME_INTR)
  368. ch->status |= HALF_FRAME_INTR;
  369. if (ch->fs && ch->bs) {
  370. a->pck_element ++;
  371. /* Check if a full packet has beed transferred. */
  372. if (a->pck_element == a->pck_elements) {
  373. a->pck_element = 0;
  374. /* Set the END_PKT interrupt */
  375. if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
  376. ch->status |= END_PKT_INTR;
  377. /* If the channel is packet-synchronized, deactivate it */
  378. if (ch->sync)
  379. omap_dma_deactivate_channel(s, ch);
  380. }
  381. }
  382. if (a->element == a->elements) {
  383. /* End of Frame */
  384. a->element = 0;
  385. a->src += a->frame_delta[0];
  386. a->dest += a->frame_delta[1];
  387. a->frame ++;
  388. /* If the channel is frame synchronized, deactivate it */
  389. if (ch->sync && ch->fs && !ch->bs)
  390. omap_dma_deactivate_channel(s, ch);
  391. /* If the channel is async, update cpc */
  392. if (!ch->sync)
  393. ch->cpc = a->dest & 0xffff;
  394. /* Set the END_FRAME interrupt */
  395. if (ch->interrupts & END_FRAME_INTR)
  396. ch->status |= END_FRAME_INTR;
  397. if (a->frame == a->frames) {
  398. /* End of Block */
  399. /* Disable the channel */
  400. if (ch->omap_3_1_compatible_disable) {
  401. omap_dma_disable_channel(s, ch);
  402. if (ch->link_enabled)
  403. omap_dma_enable_channel(s,
  404. &s->ch[ch->link_next_ch]);
  405. } else {
  406. if (!ch->auto_init)
  407. omap_dma_disable_channel(s, ch);
  408. else if (ch->repeat || ch->end_prog)
  409. omap_dma_channel_load(ch);
  410. else {
  411. ch->waiting_end_prog = 1;
  412. omap_dma_deactivate_channel(s, ch);
  413. }
  414. }
  415. if (ch->interrupts & END_BLOCK_INTR)
  416. ch->status |= END_BLOCK_INTR;
  417. }
  418. }
  419. } while (status == ch->status && ch->active);
  420. omap_dma_interrupts_update(s);
  421. #endif
  422. }
  423. enum {
  424. omap_dma_intr_element_sync,
  425. omap_dma_intr_last_frame,
  426. omap_dma_intr_half_frame,
  427. omap_dma_intr_frame,
  428. omap_dma_intr_frame_sync,
  429. omap_dma_intr_packet,
  430. omap_dma_intr_packet_sync,
  431. omap_dma_intr_block,
  432. __omap_dma_intr_last,
  433. };
  434. static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
  435. {
  436. struct omap_dma_port_if_s *src_p, *dest_p;
  437. struct omap_dma_reg_set_s *a;
  438. struct omap_dma_channel_s *ch = dma->opaque;
  439. struct omap_dma_s *s = dma->dma->opaque;
  440. int frames, min_elems, elements[__omap_dma_intr_last];
  441. a = &ch->active_set;
  442. src_p = &s->mpu->port[ch->port[0]];
  443. dest_p = &s->mpu->port[ch->port[1]];
  444. if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
  445. (!dest_p->addr_valid(s->mpu, a->dest))) {
  446. #if 0
  447. /* Bus time-out */
  448. if (ch->interrupts & TIMEOUT_INTR)
  449. ch->status |= TIMEOUT_INTR;
  450. omap_dma_deactivate_channel(s, ch);
  451. continue;
  452. #endif
  453. printf("%s: Bus time-out in DMA%i operation\n",
  454. __FUNCTION__, dma->num);
  455. }
  456. min_elems = INT_MAX;
  457. /* Check all the conditions that terminate the transfer starting
  458. * with those that can occur the soonest. */
  459. #define INTR_CHECK(cond, id, nelements) \
  460. if (cond) { \
  461. elements[id] = nelements; \
  462. if (elements[id] < min_elems) \
  463. min_elems = elements[id]; \
  464. } else \
  465. elements[id] = INT_MAX;
  466. /* Elements */
  467. INTR_CHECK(
  468. ch->sync && !ch->fs && !ch->bs,
  469. omap_dma_intr_element_sync,
  470. 1)
  471. /* Frames */
  472. /* TODO: for transfers where entire frames can be read and written
  473. * using memcpy() but a->frame_delta is non-zero, try to still do
  474. * transfers using soc_dma but limit min_elems to a->elements - ...
  475. * See also the TODO in omap_dma_channel_load. */
  476. INTR_CHECK(
  477. (ch->interrupts & LAST_FRAME_INTR) &&
  478. ((a->frame < a->frames - 1) || !a->element),
  479. omap_dma_intr_last_frame,
  480. (a->frames - a->frame - 2) * a->elements +
  481. (a->elements - a->element + 1))
  482. INTR_CHECK(
  483. ch->interrupts & HALF_FRAME_INTR,
  484. omap_dma_intr_half_frame,
  485. (a->elements >> 1) +
  486. (a->element >= (a->elements >> 1) ? a->elements : 0) -
  487. a->element)
  488. INTR_CHECK(
  489. ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
  490. omap_dma_intr_frame,
  491. a->elements - a->element)
  492. INTR_CHECK(
  493. ch->sync && ch->fs && !ch->bs,
  494. omap_dma_intr_frame_sync,
  495. a->elements - a->element)
  496. /* Packets */
  497. INTR_CHECK(
  498. ch->fs && ch->bs &&
  499. (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
  500. omap_dma_intr_packet,
  501. a->pck_elements - a->pck_element)
  502. INTR_CHECK(
  503. ch->fs && ch->bs && ch->sync,
  504. omap_dma_intr_packet_sync,
  505. a->pck_elements - a->pck_element)
  506. /* Blocks */
  507. INTR_CHECK(
  508. 1,
  509. omap_dma_intr_block,
  510. (a->frames - a->frame - 1) * a->elements +
  511. (a->elements - a->element))
  512. dma->bytes = min_elems * ch->data_type;
  513. /* Set appropriate interrupts and/or deactivate channels */
  514. #ifdef MULTI_REQ
  515. /* TODO: should all of this only be done if dma->update, and otherwise
  516. * inside omap_dma_transfer_generic below - check what's faster. */
  517. if (dma->update) {
  518. #endif
  519. /* If the channel is element synchronized, deactivate it */
  520. if (min_elems == elements[omap_dma_intr_element_sync])
  521. omap_dma_deactivate_channel(s, ch);
  522. /* If it is the last frame, set the LAST_FRAME interrupt */
  523. if (min_elems == elements[omap_dma_intr_last_frame])
  524. ch->status |= LAST_FRAME_INTR;
  525. /* If exactly half of the frame was reached, set the HALF_FRAME
  526. interrupt */
  527. if (min_elems == elements[omap_dma_intr_half_frame])
  528. ch->status |= HALF_FRAME_INTR;
  529. /* If a full packet has been transferred, set the END_PKT interrupt */
  530. if (min_elems == elements[omap_dma_intr_packet])
  531. ch->status |= END_PKT_INTR;
  532. /* If the channel is packet-synchronized, deactivate it */
  533. if (min_elems == elements[omap_dma_intr_packet_sync])
  534. omap_dma_deactivate_channel(s, ch);
  535. /* If the channel is frame synchronized, deactivate it */
  536. if (min_elems == elements[omap_dma_intr_frame_sync])
  537. omap_dma_deactivate_channel(s, ch);
  538. /* Set the END_FRAME interrupt */
  539. if (min_elems == elements[omap_dma_intr_frame])
  540. ch->status |= END_FRAME_INTR;
  541. if (min_elems == elements[omap_dma_intr_block]) {
  542. /* End of Block */
  543. /* Disable the channel */
  544. if (ch->omap_3_1_compatible_disable) {
  545. omap_dma_disable_channel(s, ch);
  546. if (ch->link_enabled)
  547. omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
  548. } else {
  549. if (!ch->auto_init)
  550. omap_dma_disable_channel(s, ch);
  551. else if (ch->repeat || ch->end_prog)
  552. omap_dma_channel_load(ch);
  553. else {
  554. ch->waiting_end_prog = 1;
  555. omap_dma_deactivate_channel(s, ch);
  556. }
  557. }
  558. if (ch->interrupts & END_BLOCK_INTR)
  559. ch->status |= END_BLOCK_INTR;
  560. }
  561. /* Update packet number */
  562. if (ch->fs && ch->bs) {
  563. a->pck_element += min_elems;
  564. a->pck_element %= a->pck_elements;
  565. }
  566. /* TODO: check if we really need to update anything here or perhaps we
  567. * can skip part of this. */
  568. #ifndef MULTI_REQ
  569. if (dma->update) {
  570. #endif
  571. a->element += min_elems;
  572. frames = a->element / a->elements;
  573. a->element = a->element % a->elements;
  574. a->frame += frames;
  575. a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
  576. a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
  577. /* If the channel is async, update cpc */
  578. if (!ch->sync && frames)
  579. ch->cpc = a->dest & 0xffff;
  580. /* TODO: if the destination port is IMIF or EMIFF, set the dirty
  581. * bits on it. */
  582. #ifndef MULTI_REQ
  583. }
  584. #else
  585. }
  586. #endif
  587. omap_dma_interrupts_update(s);
  588. }
  589. void omap_dma_reset(struct soc_dma_s *dma)
  590. {
  591. int i;
  592. struct omap_dma_s *s = dma->opaque;
  593. soc_dma_reset(s->dma);
  594. if (s->model < omap_dma_4)
  595. s->gcr = 0x0004;
  596. else
  597. s->gcr = 0x00010010;
  598. s->ocp = 0x00000000;
  599. memset(&s->irqstat, 0, sizeof(s->irqstat));
  600. memset(&s->irqen, 0, sizeof(s->irqen));
  601. s->lcd_ch.src = emiff;
  602. s->lcd_ch.condition = 0;
  603. s->lcd_ch.interrupts = 0;
  604. s->lcd_ch.dual = 0;
  605. if (s->model < omap_dma_4)
  606. omap_dma_enable_3_1_mapping(s);
  607. for (i = 0; i < s->chans; i ++) {
  608. s->ch[i].suspend = 0;
  609. s->ch[i].prefetch = 0;
  610. s->ch[i].buf_disable = 0;
  611. s->ch[i].src_sync = 0;
  612. memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
  613. memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
  614. memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
  615. memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
  616. memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
  617. memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
  618. memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
  619. memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
  620. s->ch[i].write_mode = 0;
  621. s->ch[i].data_type = 0;
  622. s->ch[i].transparent_copy = 0;
  623. s->ch[i].constant_fill = 0;
  624. s->ch[i].color = 0x00000000;
  625. s->ch[i].end_prog = 0;
  626. s->ch[i].repeat = 0;
  627. s->ch[i].auto_init = 0;
  628. s->ch[i].link_enabled = 0;
  629. if (s->model < omap_dma_4)
  630. s->ch[i].interrupts = 0x0003;
  631. else
  632. s->ch[i].interrupts = 0x0000;
  633. s->ch[i].status = 0;
  634. s->ch[i].cstatus = 0;
  635. s->ch[i].active = 0;
  636. s->ch[i].enable = 0;
  637. s->ch[i].sync = 0;
  638. s->ch[i].pending_request = 0;
  639. s->ch[i].waiting_end_prog = 0;
  640. s->ch[i].cpc = 0x0000;
  641. s->ch[i].fs = 0;
  642. s->ch[i].bs = 0;
  643. s->ch[i].omap_3_1_compatible_disable = 0;
  644. memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
  645. s->ch[i].priority = 0;
  646. s->ch[i].interleave_disabled = 0;
  647. s->ch[i].type = 0;
  648. }
  649. }
  650. static int omap_dma_ch_reg_read(struct omap_dma_s *s,
  651. struct omap_dma_channel_s *ch, int reg, uint16_t *value)
  652. {
  653. switch (reg) {
  654. case 0x00: /* SYS_DMA_CSDP_CH0 */
  655. *value = (ch->burst[1] << 14) |
  656. (ch->pack[1] << 13) |
  657. (ch->port[1] << 9) |
  658. (ch->burst[0] << 7) |
  659. (ch->pack[0] << 6) |
  660. (ch->port[0] << 2) |
  661. (ch->data_type >> 1);
  662. break;
  663. case 0x02: /* SYS_DMA_CCR_CH0 */
  664. if (s->model <= omap_dma_3_1)
  665. *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
  666. else
  667. *value = ch->omap_3_1_compatible_disable << 10;
  668. *value |= (ch->mode[1] << 14) |
  669. (ch->mode[0] << 12) |
  670. (ch->end_prog << 11) |
  671. (ch->repeat << 9) |
  672. (ch->auto_init << 8) |
  673. (ch->enable << 7) |
  674. (ch->priority << 6) |
  675. (ch->fs << 5) | ch->sync;
  676. break;
  677. case 0x04: /* SYS_DMA_CICR_CH0 */
  678. *value = ch->interrupts;
  679. break;
  680. case 0x06: /* SYS_DMA_CSR_CH0 */
  681. *value = ch->status;
  682. ch->status &= SYNC;
  683. if (!ch->omap_3_1_compatible_disable && ch->sibling) {
  684. *value |= (ch->sibling->status & 0x3f) << 6;
  685. ch->sibling->status &= SYNC;
  686. }
  687. qemu_irq_lower(ch->irq);
  688. break;
  689. case 0x08: /* SYS_DMA_CSSA_L_CH0 */
  690. *value = ch->addr[0] & 0x0000ffff;
  691. break;
  692. case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
  693. *value = ch->addr[0] >> 16;
  694. break;
  695. case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
  696. *value = ch->addr[1] & 0x0000ffff;
  697. break;
  698. case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
  699. *value = ch->addr[1] >> 16;
  700. break;
  701. case 0x10: /* SYS_DMA_CEN_CH0 */
  702. *value = ch->elements;
  703. break;
  704. case 0x12: /* SYS_DMA_CFN_CH0 */
  705. *value = ch->frames;
  706. break;
  707. case 0x14: /* SYS_DMA_CFI_CH0 */
  708. *value = ch->frame_index[0];
  709. break;
  710. case 0x16: /* SYS_DMA_CEI_CH0 */
  711. *value = ch->element_index[0];
  712. break;
  713. case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
  714. if (ch->omap_3_1_compatible_disable)
  715. *value = ch->active_set.src & 0xffff; /* CSAC */
  716. else
  717. *value = ch->cpc;
  718. break;
  719. case 0x1a: /* DMA_CDAC */
  720. *value = ch->active_set.dest & 0xffff; /* CDAC */
  721. break;
  722. case 0x1c: /* DMA_CDEI */
  723. *value = ch->element_index[1];
  724. break;
  725. case 0x1e: /* DMA_CDFI */
  726. *value = ch->frame_index[1];
  727. break;
  728. case 0x20: /* DMA_COLOR_L */
  729. *value = ch->color & 0xffff;
  730. break;
  731. case 0x22: /* DMA_COLOR_U */
  732. *value = ch->color >> 16;
  733. break;
  734. case 0x24: /* DMA_CCR2 */
  735. *value = (ch->bs << 2) |
  736. (ch->transparent_copy << 1) |
  737. ch->constant_fill;
  738. break;
  739. case 0x28: /* DMA_CLNK_CTRL */
  740. *value = (ch->link_enabled << 15) |
  741. (ch->link_next_ch & 0xf);
  742. break;
  743. case 0x2a: /* DMA_LCH_CTRL */
  744. *value = (ch->interleave_disabled << 15) |
  745. ch->type;
  746. break;
  747. default:
  748. return 1;
  749. }
  750. return 0;
  751. }
  752. static int omap_dma_ch_reg_write(struct omap_dma_s *s,
  753. struct omap_dma_channel_s *ch, int reg, uint16_t value)
  754. {
  755. switch (reg) {
  756. case 0x00: /* SYS_DMA_CSDP_CH0 */
  757. ch->burst[1] = (value & 0xc000) >> 14;
  758. ch->pack[1] = (value & 0x2000) >> 13;
  759. ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
  760. ch->burst[0] = (value & 0x0180) >> 7;
  761. ch->pack[0] = (value & 0x0040) >> 6;
  762. ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
  763. ch->data_type = 1 << (value & 3);
  764. if (ch->port[0] >= __omap_dma_port_last)
  765. printf("%s: invalid DMA port %i\n", __FUNCTION__,
  766. ch->port[0]);
  767. if (ch->port[1] >= __omap_dma_port_last)
  768. printf("%s: invalid DMA port %i\n", __FUNCTION__,
  769. ch->port[1]);
  770. if ((value & 3) == 3)
  771. printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
  772. break;
  773. case 0x02: /* SYS_DMA_CCR_CH0 */
  774. ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
  775. ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
  776. ch->end_prog = (value & 0x0800) >> 11;
  777. if (s->model >= omap_dma_3_2)
  778. ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
  779. ch->repeat = (value & 0x0200) >> 9;
  780. ch->auto_init = (value & 0x0100) >> 8;
  781. ch->priority = (value & 0x0040) >> 6;
  782. ch->fs = (value & 0x0020) >> 5;
  783. ch->sync = value & 0x001f;
  784. if (value & 0x0080)
  785. omap_dma_enable_channel(s, ch);
  786. else
  787. omap_dma_disable_channel(s, ch);
  788. if (ch->end_prog)
  789. omap_dma_channel_end_prog(s, ch);
  790. break;
  791. case 0x04: /* SYS_DMA_CICR_CH0 */
  792. ch->interrupts = value & 0x3f;
  793. break;
  794. case 0x06: /* SYS_DMA_CSR_CH0 */
  795. OMAP_RO_REG((target_phys_addr_t) reg);
  796. break;
  797. case 0x08: /* SYS_DMA_CSSA_L_CH0 */
  798. ch->addr[0] &= 0xffff0000;
  799. ch->addr[0] |= value;
  800. break;
  801. case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
  802. ch->addr[0] &= 0x0000ffff;
  803. ch->addr[0] |= (uint32_t) value << 16;
  804. break;
  805. case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
  806. ch->addr[1] &= 0xffff0000;
  807. ch->addr[1] |= value;
  808. break;
  809. case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
  810. ch->addr[1] &= 0x0000ffff;
  811. ch->addr[1] |= (uint32_t) value << 16;
  812. break;
  813. case 0x10: /* SYS_DMA_CEN_CH0 */
  814. ch->elements = value;
  815. break;
  816. case 0x12: /* SYS_DMA_CFN_CH0 */
  817. ch->frames = value;
  818. break;
  819. case 0x14: /* SYS_DMA_CFI_CH0 */
  820. ch->frame_index[0] = (int16_t) value;
  821. break;
  822. case 0x16: /* SYS_DMA_CEI_CH0 */
  823. ch->element_index[0] = (int16_t) value;
  824. break;
  825. case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
  826. OMAP_RO_REG((target_phys_addr_t) reg);
  827. break;
  828. case 0x1c: /* DMA_CDEI */
  829. ch->element_index[1] = (int16_t) value;
  830. break;
  831. case 0x1e: /* DMA_CDFI */
  832. ch->frame_index[1] = (int16_t) value;
  833. break;
  834. case 0x20: /* DMA_COLOR_L */
  835. ch->color &= 0xffff0000;
  836. ch->color |= value;
  837. break;
  838. case 0x22: /* DMA_COLOR_U */
  839. ch->color &= 0xffff;
  840. ch->color |= value << 16;
  841. break;
  842. case 0x24: /* DMA_CCR2 */
  843. ch->bs = (value >> 2) & 0x1;
  844. ch->transparent_copy = (value >> 1) & 0x1;
  845. ch->constant_fill = value & 0x1;
  846. break;
  847. case 0x28: /* DMA_CLNK_CTRL */
  848. ch->link_enabled = (value >> 15) & 0x1;
  849. if (value & (1 << 14)) { /* Stop_Lnk */
  850. ch->link_enabled = 0;
  851. omap_dma_disable_channel(s, ch);
  852. }
  853. ch->link_next_ch = value & 0x1f;
  854. break;
  855. case 0x2a: /* DMA_LCH_CTRL */
  856. ch->interleave_disabled = (value >> 15) & 0x1;
  857. ch->type = value & 0xf;
  858. break;
  859. default:
  860. return 1;
  861. }
  862. return 0;
  863. }
  864. static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
  865. uint16_t value)
  866. {
  867. switch (offset) {
  868. case 0xbc0: /* DMA_LCD_CSDP */
  869. s->brust_f2 = (value >> 14) & 0x3;
  870. s->pack_f2 = (value >> 13) & 0x1;
  871. s->data_type_f2 = (1 << ((value >> 11) & 0x3));
  872. s->brust_f1 = (value >> 7) & 0x3;
  873. s->pack_f1 = (value >> 6) & 0x1;
  874. s->data_type_f1 = (1 << ((value >> 0) & 0x3));
  875. break;
  876. case 0xbc2: /* DMA_LCD_CCR */
  877. s->mode_f2 = (value >> 14) & 0x3;
  878. s->mode_f1 = (value >> 12) & 0x3;
  879. s->end_prog = (value >> 11) & 0x1;
  880. s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
  881. s->repeat = (value >> 9) & 0x1;
  882. s->auto_init = (value >> 8) & 0x1;
  883. s->running = (value >> 7) & 0x1;
  884. s->priority = (value >> 6) & 0x1;
  885. s->bs = (value >> 4) & 0x1;
  886. break;
  887. case 0xbc4: /* DMA_LCD_CTRL */
  888. s->dst = (value >> 8) & 0x1;
  889. s->src = ((value >> 6) & 0x3) << 1;
  890. s->condition = 0;
  891. /* Assume no bus errors and thus no BUS_ERROR irq bits. */
  892. s->interrupts = (value >> 1) & 1;
  893. s->dual = value & 1;
  894. break;
  895. case 0xbc8: /* TOP_B1_L */
  896. s->src_f1_top &= 0xffff0000;
  897. s->src_f1_top |= 0x0000ffff & value;
  898. break;
  899. case 0xbca: /* TOP_B1_U */
  900. s->src_f1_top &= 0x0000ffff;
  901. s->src_f1_top |= value << 16;
  902. break;
  903. case 0xbcc: /* BOT_B1_L */
  904. s->src_f1_bottom &= 0xffff0000;
  905. s->src_f1_bottom |= 0x0000ffff & value;
  906. break;
  907. case 0xbce: /* BOT_B1_U */
  908. s->src_f1_bottom &= 0x0000ffff;
  909. s->src_f1_bottom |= (uint32_t) value << 16;
  910. break;
  911. case 0xbd0: /* TOP_B2_L */
  912. s->src_f2_top &= 0xffff0000;
  913. s->src_f2_top |= 0x0000ffff & value;
  914. break;
  915. case 0xbd2: /* TOP_B2_U */
  916. s->src_f2_top &= 0x0000ffff;
  917. s->src_f2_top |= (uint32_t) value << 16;
  918. break;
  919. case 0xbd4: /* BOT_B2_L */
  920. s->src_f2_bottom &= 0xffff0000;
  921. s->src_f2_bottom |= 0x0000ffff & value;
  922. break;
  923. case 0xbd6: /* BOT_B2_U */
  924. s->src_f2_bottom &= 0x0000ffff;
  925. s->src_f2_bottom |= (uint32_t) value << 16;
  926. break;
  927. case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
  928. s->element_index_f1 = value;
  929. break;
  930. case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
  931. s->frame_index_f1 &= 0xffff0000;
  932. s->frame_index_f1 |= 0x0000ffff & value;
  933. break;
  934. case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
  935. s->frame_index_f1 &= 0x0000ffff;
  936. s->frame_index_f1 |= (uint32_t) value << 16;
  937. break;
  938. case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
  939. s->element_index_f2 = value;
  940. break;
  941. case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
  942. s->frame_index_f2 &= 0xffff0000;
  943. s->frame_index_f2 |= 0x0000ffff & value;
  944. break;
  945. case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
  946. s->frame_index_f2 &= 0x0000ffff;
  947. s->frame_index_f2 |= (uint32_t) value << 16;
  948. break;
  949. case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
  950. s->elements_f1 = value;
  951. break;
  952. case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
  953. s->frames_f1 = value;
  954. break;
  955. case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
  956. s->elements_f2 = value;
  957. break;
  958. case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
  959. s->frames_f2 = value;
  960. break;
  961. case 0xbea: /* DMA_LCD_LCH_CTRL */
  962. s->lch_type = value & 0xf;
  963. break;
  964. default:
  965. return 1;
  966. }
  967. return 0;
  968. }
  969. static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
  970. uint16_t *ret)
  971. {
  972. switch (offset) {
  973. case 0xbc0: /* DMA_LCD_CSDP */
  974. *ret = (s->brust_f2 << 14) |
  975. (s->pack_f2 << 13) |
  976. ((s->data_type_f2 >> 1) << 11) |
  977. (s->brust_f1 << 7) |
  978. (s->pack_f1 << 6) |
  979. ((s->data_type_f1 >> 1) << 0);
  980. break;
  981. case 0xbc2: /* DMA_LCD_CCR */
  982. *ret = (s->mode_f2 << 14) |
  983. (s->mode_f1 << 12) |
  984. (s->end_prog << 11) |
  985. (s->omap_3_1_compatible_disable << 10) |
  986. (s->repeat << 9) |
  987. (s->auto_init << 8) |
  988. (s->running << 7) |
  989. (s->priority << 6) |
  990. (s->bs << 4);
  991. break;
  992. case 0xbc4: /* DMA_LCD_CTRL */
  993. qemu_irq_lower(s->irq);
  994. *ret = (s->dst << 8) |
  995. ((s->src & 0x6) << 5) |
  996. (s->condition << 3) |
  997. (s->interrupts << 1) |
  998. s->dual;
  999. break;
  1000. case 0xbc8: /* TOP_B1_L */
  1001. *ret = s->src_f1_top & 0xffff;
  1002. break;
  1003. case 0xbca: /* TOP_B1_U */
  1004. *ret = s->src_f1_top >> 16;
  1005. break;
  1006. case 0xbcc: /* BOT_B1_L */
  1007. *ret = s->src_f1_bottom & 0xffff;
  1008. break;
  1009. case 0xbce: /* BOT_B1_U */
  1010. *ret = s->src_f1_bottom >> 16;
  1011. break;
  1012. case 0xbd0: /* TOP_B2_L */
  1013. *ret = s->src_f2_top & 0xffff;
  1014. break;
  1015. case 0xbd2: /* TOP_B2_U */
  1016. *ret = s->src_f2_top >> 16;
  1017. break;
  1018. case 0xbd4: /* BOT_B2_L */
  1019. *ret = s->src_f2_bottom & 0xffff;
  1020. break;
  1021. case 0xbd6: /* BOT_B2_U */
  1022. *ret = s->src_f2_bottom >> 16;
  1023. break;
  1024. case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
  1025. *ret = s->element_index_f1;
  1026. break;
  1027. case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
  1028. *ret = s->frame_index_f1 & 0xffff;
  1029. break;
  1030. case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
  1031. *ret = s->frame_index_f1 >> 16;
  1032. break;
  1033. case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
  1034. *ret = s->element_index_f2;
  1035. break;
  1036. case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
  1037. *ret = s->frame_index_f2 & 0xffff;
  1038. break;
  1039. case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
  1040. *ret = s->frame_index_f2 >> 16;
  1041. break;
  1042. case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
  1043. *ret = s->elements_f1;
  1044. break;
  1045. case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
  1046. *ret = s->frames_f1;
  1047. break;
  1048. case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
  1049. *ret = s->elements_f2;
  1050. break;
  1051. case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
  1052. *ret = s->frames_f2;
  1053. break;
  1054. case 0xbea: /* DMA_LCD_LCH_CTRL */
  1055. *ret = s->lch_type;
  1056. break;
  1057. default:
  1058. return 1;
  1059. }
  1060. return 0;
  1061. }
  1062. static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
  1063. uint16_t value)
  1064. {
  1065. switch (offset) {
  1066. case 0x300: /* SYS_DMA_LCD_CTRL */
  1067. s->src = (value & 0x40) ? imif : emiff;
  1068. s->condition = 0;
  1069. /* Assume no bus errors and thus no BUS_ERROR irq bits. */
  1070. s->interrupts = (value >> 1) & 1;
  1071. s->dual = value & 1;
  1072. break;
  1073. case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
  1074. s->src_f1_top &= 0xffff0000;
  1075. s->src_f1_top |= 0x0000ffff & value;
  1076. break;
  1077. case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
  1078. s->src_f1_top &= 0x0000ffff;
  1079. s->src_f1_top |= value << 16;
  1080. break;
  1081. case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
  1082. s->src_f1_bottom &= 0xffff0000;
  1083. s->src_f1_bottom |= 0x0000ffff & value;
  1084. break;
  1085. case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
  1086. s->src_f1_bottom &= 0x0000ffff;
  1087. s->src_f1_bottom |= value << 16;
  1088. break;
  1089. case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
  1090. s->src_f2_top &= 0xffff0000;
  1091. s->src_f2_top |= 0x0000ffff & value;
  1092. break;
  1093. case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
  1094. s->src_f2_top &= 0x0000ffff;
  1095. s->src_f2_top |= value << 16;
  1096. break;
  1097. case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
  1098. s->src_f2_bottom &= 0xffff0000;
  1099. s->src_f2_bottom |= 0x0000ffff & value;
  1100. break;
  1101. case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
  1102. s->src_f2_bottom &= 0x0000ffff;
  1103. s->src_f2_bottom |= value << 16;
  1104. break;
  1105. default:
  1106. return 1;
  1107. }
  1108. return 0;
  1109. }
  1110. static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
  1111. uint16_t *ret)
  1112. {
  1113. int i;
  1114. switch (offset) {
  1115. case 0x300: /* SYS_DMA_LCD_CTRL */
  1116. i = s->condition;
  1117. s->condition = 0;
  1118. qemu_irq_lower(s->irq);
  1119. *ret = ((s->src == imif) << 6) | (i << 3) |
  1120. (s->interrupts << 1) | s->dual;
  1121. break;
  1122. case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
  1123. *ret = s->src_f1_top & 0xffff;
  1124. break;
  1125. case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
  1126. *ret = s->src_f1_top >> 16;
  1127. break;
  1128. case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
  1129. *ret = s->src_f1_bottom & 0xffff;
  1130. break;
  1131. case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
  1132. *ret = s->src_f1_bottom >> 16;
  1133. break;
  1134. case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
  1135. *ret = s->src_f2_top & 0xffff;
  1136. break;
  1137. case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
  1138. *ret = s->src_f2_top >> 16;
  1139. break;
  1140. case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
  1141. *ret = s->src_f2_bottom & 0xffff;
  1142. break;
  1143. case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
  1144. *ret = s->src_f2_bottom >> 16;
  1145. break;
  1146. default:
  1147. return 1;
  1148. }
  1149. return 0;
  1150. }
  1151. static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
  1152. {
  1153. switch (offset) {
  1154. case 0x400: /* SYS_DMA_GCR */
  1155. s->gcr = value;
  1156. break;
  1157. case 0x404: /* DMA_GSCR */
  1158. if (value & 0x8)
  1159. omap_dma_disable_3_1_mapping(s);
  1160. else
  1161. omap_dma_enable_3_1_mapping(s);
  1162. break;
  1163. case 0x408: /* DMA_GRST */
  1164. if (value & 0x1)
  1165. omap_dma_reset(s->dma);
  1166. break;
  1167. default:
  1168. return 1;
  1169. }
  1170. return 0;
  1171. }
  1172. static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
  1173. uint16_t *ret)
  1174. {
  1175. switch (offset) {
  1176. case 0x400: /* SYS_DMA_GCR */
  1177. *ret = s->gcr;
  1178. break;
  1179. case 0x404: /* DMA_GSCR */
  1180. *ret = s->omap_3_1_mapping_disabled << 3;
  1181. break;
  1182. case 0x408: /* DMA_GRST */
  1183. *ret = 0;
  1184. break;
  1185. case 0x442: /* DMA_HW_ID */
  1186. case 0x444: /* DMA_PCh2_ID */
  1187. case 0x446: /* DMA_PCh0_ID */
  1188. case 0x448: /* DMA_PCh1_ID */
  1189. case 0x44a: /* DMA_PChG_ID */
  1190. case 0x44c: /* DMA_PChD_ID */
  1191. *ret = 1;
  1192. break;
  1193. case 0x44e: /* DMA_CAPS_0_U */
  1194. *ret = (s->caps[0] >> 16) & 0xffff;
  1195. break;
  1196. case 0x450: /* DMA_CAPS_0_L */
  1197. *ret = (s->caps[0] >> 0) & 0xffff;
  1198. break;
  1199. case 0x452: /* DMA_CAPS_1_U */
  1200. *ret = (s->caps[1] >> 16) & 0xffff;
  1201. break;
  1202. case 0x454: /* DMA_CAPS_1_L */
  1203. *ret = (s->caps[1] >> 0) & 0xffff;
  1204. break;
  1205. case 0x456: /* DMA_CAPS_2 */
  1206. *ret = s->caps[2];
  1207. break;
  1208. case 0x458: /* DMA_CAPS_3 */
  1209. *ret = s->caps[3];
  1210. break;
  1211. case 0x45a: /* DMA_CAPS_4 */
  1212. *ret = s->caps[4];
  1213. break;
  1214. case 0x460: /* DMA_PCh2_SR */
  1215. case 0x480: /* DMA_PCh0_SR */
  1216. case 0x482: /* DMA_PCh1_SR */
  1217. case 0x4c0: /* DMA_PChD_SR_0 */
  1218. printf("%s: Physical Channel Status Registers not implemented.\n",
  1219. __FUNCTION__);
  1220. *ret = 0xff;
  1221. break;
  1222. default:
  1223. return 1;
  1224. }
  1225. return 0;
  1226. }
  1227. static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
  1228. {
  1229. struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  1230. int reg, ch;
  1231. uint16_t ret;
  1232. switch (addr) {
  1233. case 0x300 ... 0x3fe:
  1234. if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
  1235. if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
  1236. break;
  1237. return ret;
  1238. }
  1239. /* Fall through. */
  1240. case 0x000 ... 0x2fe:
  1241. reg = addr & 0x3f;
  1242. ch = (addr >> 6) & 0x0f;
  1243. if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
  1244. break;
  1245. return ret;
  1246. case 0x404 ... 0x4fe:
  1247. if (s->model <= omap_dma_3_1)
  1248. break;
  1249. /* Fall through. */
  1250. case 0x400:
  1251. if (omap_dma_sys_read(s, addr, &ret))
  1252. break;
  1253. return ret;
  1254. case 0xb00 ... 0xbfe:
  1255. if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
  1256. if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
  1257. break;
  1258. return ret;
  1259. }
  1260. break;
  1261. }
  1262. OMAP_BAD_REG(addr);
  1263. return 0;
  1264. }
  1265. static void omap_dma_write(void *opaque, target_phys_addr_t addr,
  1266. uint32_t value)
  1267. {
  1268. struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  1269. int reg, ch;
  1270. switch (addr) {
  1271. case 0x300 ... 0x3fe:
  1272. if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
  1273. if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
  1274. break;
  1275. return;
  1276. }
  1277. /* Fall through. */
  1278. case 0x000 ... 0x2fe:
  1279. reg = addr & 0x3f;
  1280. ch = (addr >> 6) & 0x0f;
  1281. if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
  1282. break;
  1283. return;
  1284. case 0x404 ... 0x4fe:
  1285. if (s->model <= omap_dma_3_1)
  1286. break;
  1287. case 0x400:
  1288. /* Fall through. */
  1289. if (omap_dma_sys_write(s, addr, value))
  1290. break;
  1291. return;
  1292. case 0xb00 ... 0xbfe:
  1293. if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
  1294. if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
  1295. break;
  1296. return;
  1297. }
  1298. break;
  1299. }
  1300. OMAP_BAD_REG(addr);
  1301. }
  1302. static CPUReadMemoryFunc * const omap_dma_readfn[] = {
  1303. omap_badwidth_read16,
  1304. omap_dma_read,
  1305. omap_badwidth_read16,
  1306. };
  1307. static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
  1308. omap_badwidth_write16,
  1309. omap_dma_write,
  1310. omap_badwidth_write16,
  1311. };
  1312. static void omap_dma_request(void *opaque, int drq, int req)
  1313. {
  1314. struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  1315. /* The request pins are level triggered in QEMU. */
  1316. if (req) {
  1317. if (~s->dma->drqbmp & (1 << drq)) {
  1318. s->dma->drqbmp |= 1 << drq;
  1319. omap_dma_process_request(s, drq);
  1320. }
  1321. } else
  1322. s->dma->drqbmp &= ~(1 << drq);
  1323. }
  1324. /* XXX: this won't be needed once soc_dma knows about clocks. */
  1325. static void omap_dma_clk_update(void *opaque, int line, int on)
  1326. {
  1327. struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  1328. int i;
  1329. s->dma->freq = omap_clk_getrate(s->clk);
  1330. for (i = 0; i < s->chans; i ++)
  1331. if (s->ch[i].active)
  1332. soc_dma_set_request(s->ch[i].dma, on);
  1333. }
  1334. static void omap_dma_setcaps(struct omap_dma_s *s)
  1335. {
  1336. switch (s->model) {
  1337. default:
  1338. case omap_dma_3_1:
  1339. break;
  1340. case omap_dma_3_2:
  1341. case omap_dma_4:
  1342. /* XXX Only available for sDMA */
  1343. s->caps[0] =
  1344. (1 << 19) | /* Constant Fill Capability */
  1345. (1 << 18); /* Transparent BLT Capability */
  1346. s->caps[1] =
  1347. (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
  1348. s->caps[2] =
  1349. (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
  1350. (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
  1351. (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
  1352. (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
  1353. (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
  1354. (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
  1355. (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
  1356. (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
  1357. (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
  1358. s->caps[3] =
  1359. (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
  1360. (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
  1361. (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
  1362. (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
  1363. (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
  1364. (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
  1365. (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
  1366. (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
  1367. s->caps[4] =
  1368. (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
  1369. (1 << 6) | /* SYNC_STATUS_CPBLTY */
  1370. (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
  1371. (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
  1372. (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
  1373. (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
  1374. (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
  1375. (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
  1376. break;
  1377. }
  1378. }
  1379. struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
  1380. qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
  1381. enum omap_dma_model model)
  1382. {
  1383. int iomemtype, num_irqs, memsize, i;
  1384. struct omap_dma_s *s = (struct omap_dma_s *)
  1385. qemu_mallocz(sizeof(struct omap_dma_s));
  1386. if (model <= omap_dma_3_1) {
  1387. num_irqs = 6;
  1388. memsize = 0x800;
  1389. } else {
  1390. num_irqs = 16;
  1391. memsize = 0xc00;
  1392. }
  1393. s->model = model;
  1394. s->mpu = mpu;
  1395. s->clk = clk;
  1396. s->lcd_ch.irq = lcd_irq;
  1397. s->lcd_ch.mpu = mpu;
  1398. s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
  1399. s->dma->freq = omap_clk_getrate(clk);
  1400. s->dma->transfer_fn = omap_dma_transfer_generic;
  1401. s->dma->setup_fn = omap_dma_transfer_setup;
  1402. s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
  1403. s->dma->opaque = s;
  1404. while (num_irqs --)
  1405. s->ch[num_irqs].irq = irqs[num_irqs];
  1406. for (i = 0; i < 3; i ++) {
  1407. s->ch[i].sibling = &s->ch[i + 6];
  1408. s->ch[i + 6].sibling = &s->ch[i];
  1409. }
  1410. for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
  1411. s->ch[i].dma = &s->dma->ch[i];
  1412. s->dma->ch[i].opaque = &s->ch[i];
  1413. }
  1414. omap_dma_setcaps(s);
  1415. omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
  1416. omap_dma_reset(s->dma);
  1417. omap_dma_clk_update(s, 0, 1);
  1418. iomemtype = cpu_register_io_memory(omap_dma_readfn,
  1419. omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
  1420. cpu_register_physical_memory(base, memsize, iomemtype);
  1421. mpu->drq = s->dma->drq;
  1422. return s->dma;
  1423. }
  1424. static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
  1425. {
  1426. struct omap_dma_channel_s *ch = s->ch;
  1427. uint32_t bmp, bit;
  1428. for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
  1429. if (ch->status) {
  1430. bmp |= bit;
  1431. ch->cstatus |= ch->status;
  1432. ch->status = 0;
  1433. }
  1434. if ((s->irqstat[0] |= s->irqen[0] & bmp))
  1435. qemu_irq_raise(s->irq[0]);
  1436. if ((s->irqstat[1] |= s->irqen[1] & bmp))
  1437. qemu_irq_raise(s->irq[1]);
  1438. if ((s->irqstat[2] |= s->irqen[2] & bmp))
  1439. qemu_irq_raise(s->irq[2]);
  1440. if ((s->irqstat[3] |= s->irqen[3] & bmp))
  1441. qemu_irq_raise(s->irq[3]);
  1442. }
  1443. static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
  1444. {
  1445. struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  1446. int irqn = 0, chnum;
  1447. struct omap_dma_channel_s *ch;
  1448. switch (addr) {
  1449. case 0x00: /* DMA4_REVISION */
  1450. return 0x40;
  1451. case 0x14: /* DMA4_IRQSTATUS_L3 */
  1452. irqn ++;
  1453. case 0x10: /* DMA4_IRQSTATUS_L2 */
  1454. irqn ++;
  1455. case 0x0c: /* DMA4_IRQSTATUS_L1 */
  1456. irqn ++;
  1457. case 0x08: /* DMA4_IRQSTATUS_L0 */
  1458. return s->irqstat[irqn];
  1459. case 0x24: /* DMA4_IRQENABLE_L3 */
  1460. irqn ++;
  1461. case 0x20: /* DMA4_IRQENABLE_L2 */
  1462. irqn ++;
  1463. case 0x1c: /* DMA4_IRQENABLE_L1 */
  1464. irqn ++;
  1465. case 0x18: /* DMA4_IRQENABLE_L0 */
  1466. return s->irqen[irqn];
  1467. case 0x28: /* DMA4_SYSSTATUS */
  1468. return 1; /* RESETDONE */
  1469. case 0x2c: /* DMA4_OCP_SYSCONFIG */
  1470. return s->ocp;
  1471. case 0x64: /* DMA4_CAPS_0 */
  1472. return s->caps[0];
  1473. case 0x6c: /* DMA4_CAPS_2 */
  1474. return s->caps[2];
  1475. case 0x70: /* DMA4_CAPS_3 */
  1476. return s->caps[3];
  1477. case 0x74: /* DMA4_CAPS_4 */
  1478. return s->caps[4];
  1479. case 0x78: /* DMA4_GCR */
  1480. return s->gcr;
  1481. case 0x80 ... 0xfff:
  1482. addr -= 0x80;
  1483. chnum = addr / 0x60;
  1484. ch = s->ch + chnum;
  1485. addr -= chnum * 0x60;
  1486. break;
  1487. default:
  1488. OMAP_BAD_REG(addr);
  1489. return 0;
  1490. }
  1491. /* Per-channel registers */
  1492. switch (addr) {
  1493. case 0x00: /* DMA4_CCR */
  1494. return (ch->buf_disable << 25) |
  1495. (ch->src_sync << 24) |
  1496. (ch->prefetch << 23) |
  1497. ((ch->sync & 0x60) << 14) |
  1498. (ch->bs << 18) |
  1499. (ch->transparent_copy << 17) |
  1500. (ch->constant_fill << 16) |
  1501. (ch->mode[1] << 14) |
  1502. (ch->mode[0] << 12) |
  1503. (0 << 10) | (0 << 9) |
  1504. (ch->suspend << 8) |
  1505. (ch->enable << 7) |
  1506. (ch->priority << 6) |
  1507. (ch->fs << 5) | (ch->sync & 0x1f);
  1508. case 0x04: /* DMA4_CLNK_CTRL */
  1509. return (ch->link_enabled << 15) | ch->link_next_ch;
  1510. case 0x08: /* DMA4_CICR */
  1511. return ch->interrupts;
  1512. case 0x0c: /* DMA4_CSR */
  1513. return ch->cstatus;
  1514. case 0x10: /* DMA4_CSDP */
  1515. return (ch->endian[0] << 21) |
  1516. (ch->endian_lock[0] << 20) |
  1517. (ch->endian[1] << 19) |
  1518. (ch->endian_lock[1] << 18) |
  1519. (ch->write_mode << 16) |
  1520. (ch->burst[1] << 14) |
  1521. (ch->pack[1] << 13) |
  1522. (ch->translate[1] << 9) |
  1523. (ch->burst[0] << 7) |
  1524. (ch->pack[0] << 6) |
  1525. (ch->translate[0] << 2) |
  1526. (ch->data_type >> 1);
  1527. case 0x14: /* DMA4_CEN */
  1528. return ch->elements;
  1529. case 0x18: /* DMA4_CFN */
  1530. return ch->frames;
  1531. case 0x1c: /* DMA4_CSSA */
  1532. return ch->addr[0];
  1533. case 0x20: /* DMA4_CDSA */
  1534. return ch->addr[1];
  1535. case 0x24: /* DMA4_CSEI */
  1536. return ch->element_index[0];
  1537. case 0x28: /* DMA4_CSFI */
  1538. return ch->frame_index[0];
  1539. case 0x2c: /* DMA4_CDEI */
  1540. return ch->element_index[1];
  1541. case 0x30: /* DMA4_CDFI */
  1542. return ch->frame_index[1];
  1543. case 0x34: /* DMA4_CSAC */
  1544. return ch->active_set.src & 0xffff;
  1545. case 0x38: /* DMA4_CDAC */
  1546. return ch->active_set.dest & 0xffff;
  1547. case 0x3c: /* DMA4_CCEN */
  1548. return ch->active_set.element;
  1549. case 0x40: /* DMA4_CCFN */
  1550. return ch->active_set.frame;
  1551. case 0x44: /* DMA4_COLOR */
  1552. /* XXX only in sDMA */
  1553. return ch->color;
  1554. default:
  1555. OMAP_BAD_REG(addr);
  1556. return 0;
  1557. }
  1558. }
  1559. static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
  1560. uint32_t value)
  1561. {
  1562. struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  1563. int chnum, irqn = 0;
  1564. struct omap_dma_channel_s *ch;
  1565. switch (addr) {
  1566. case 0x14: /* DMA4_IRQSTATUS_L3 */
  1567. irqn ++;
  1568. case 0x10: /* DMA4_IRQSTATUS_L2 */
  1569. irqn ++;
  1570. case 0x0c: /* DMA4_IRQSTATUS_L1 */
  1571. irqn ++;
  1572. case 0x08: /* DMA4_IRQSTATUS_L0 */
  1573. s->irqstat[irqn] &= ~value;
  1574. if (!s->irqstat[irqn])
  1575. qemu_irq_lower(s->irq[irqn]);
  1576. return;
  1577. case 0x24: /* DMA4_IRQENABLE_L3 */
  1578. irqn ++;
  1579. case 0x20: /* DMA4_IRQENABLE_L2 */
  1580. irqn ++;
  1581. case 0x1c: /* DMA4_IRQENABLE_L1 */
  1582. irqn ++;
  1583. case 0x18: /* DMA4_IRQENABLE_L0 */
  1584. s->irqen[irqn] = value;
  1585. return;
  1586. case 0x2c: /* DMA4_OCP_SYSCONFIG */
  1587. if (value & 2) /* SOFTRESET */
  1588. omap_dma_reset(s->dma);
  1589. s->ocp = value & 0x3321;
  1590. if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
  1591. fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
  1592. return;
  1593. case 0x78: /* DMA4_GCR */
  1594. s->gcr = value & 0x00ff00ff;
  1595. if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
  1596. fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
  1597. return;
  1598. case 0x80 ... 0xfff:
  1599. addr -= 0x80;
  1600. chnum = addr / 0x60;
  1601. ch = s->ch + chnum;
  1602. addr -= chnum * 0x60;
  1603. break;
  1604. case 0x00: /* DMA4_REVISION */
  1605. case 0x28: /* DMA4_SYSSTATUS */
  1606. case 0x64: /* DMA4_CAPS_0 */
  1607. case 0x6c: /* DMA4_CAPS_2 */
  1608. case 0x70: /* DMA4_CAPS_3 */
  1609. case 0x74: /* DMA4_CAPS_4 */
  1610. OMAP_RO_REG(addr);
  1611. return;
  1612. default:
  1613. OMAP_BAD_REG(addr);
  1614. return;
  1615. }
  1616. /* Per-channel registers */
  1617. switch (addr) {
  1618. case 0x00: /* DMA4_CCR */
  1619. ch->buf_disable = (value >> 25) & 1;
  1620. ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
  1621. if (ch->buf_disable && !ch->src_sync)
  1622. fprintf(stderr, "%s: Buffering disable is not allowed in "
  1623. "destination synchronised mode\n", __FUNCTION__);
  1624. ch->prefetch = (value >> 23) & 1;
  1625. ch->bs = (value >> 18) & 1;
  1626. ch->transparent_copy = (value >> 17) & 1;
  1627. ch->constant_fill = (value >> 16) & 1;
  1628. ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
  1629. ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
  1630. ch->suspend = (value & 0x0100) >> 8;
  1631. ch->priority = (value & 0x0040) >> 6;
  1632. ch->fs = (value & 0x0020) >> 5;
  1633. if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
  1634. fprintf(stderr, "%s: For a packet transfer at least one port "
  1635. "must be constant-addressed\n", __FUNCTION__);
  1636. ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
  1637. /* XXX must be 0x01 for CamDMA */
  1638. if (value & 0x0080)
  1639. omap_dma_enable_channel(s, ch);
  1640. else
  1641. omap_dma_disable_channel(s, ch);
  1642. break;
  1643. case 0x04: /* DMA4_CLNK_CTRL */
  1644. ch->link_enabled = (value >> 15) & 0x1;
  1645. ch->link_next_ch = value & 0x1f;
  1646. break;
  1647. case 0x08: /* DMA4_CICR */
  1648. ch->interrupts = value & 0x09be;
  1649. break;
  1650. case 0x0c: /* DMA4_CSR */
  1651. ch->cstatus &= ~value;
  1652. break;
  1653. case 0x10: /* DMA4_CSDP */
  1654. ch->endian[0] =(value >> 21) & 1;
  1655. ch->endian_lock[0] =(value >> 20) & 1;
  1656. ch->endian[1] =(value >> 19) & 1;
  1657. ch->endian_lock[1] =(value >> 18) & 1;
  1658. if (ch->endian[0] != ch->endian[1])
  1659. fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
  1660. __FUNCTION__);
  1661. ch->write_mode = (value >> 16) & 3;
  1662. ch->burst[1] = (value & 0xc000) >> 14;
  1663. ch->pack[1] = (value & 0x2000) >> 13;
  1664. ch->translate[1] = (value & 0x1e00) >> 9;
  1665. ch->burst[0] = (value & 0x0180) >> 7;
  1666. ch->pack[0] = (value & 0x0040) >> 6;
  1667. ch->translate[0] = (value & 0x003c) >> 2;
  1668. if (ch->translate[0] | ch->translate[1])
  1669. fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
  1670. __FUNCTION__);
  1671. ch->data_type = 1 << (value & 3);
  1672. if ((value & 3) == 3)
  1673. printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
  1674. break;
  1675. case 0x14: /* DMA4_CEN */
  1676. ch->set_update = 1;
  1677. ch->elements = value & 0xffffff;
  1678. break;
  1679. case 0x18: /* DMA4_CFN */
  1680. ch->frames = value & 0xffff;
  1681. ch->set_update = 1;
  1682. break;
  1683. case 0x1c: /* DMA4_CSSA */
  1684. ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
  1685. ch->set_update = 1;
  1686. break;
  1687. case 0x20: /* DMA4_CDSA */
  1688. ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
  1689. ch->set_update = 1;
  1690. break;
  1691. case 0x24: /* DMA4_CSEI */
  1692. ch->element_index[0] = (int16_t) value;
  1693. ch->set_update = 1;
  1694. break;
  1695. case 0x28: /* DMA4_CSFI */
  1696. ch->frame_index[0] = (int32_t) value;
  1697. ch->set_update = 1;
  1698. break;
  1699. case 0x2c: /* DMA4_CDEI */
  1700. ch->element_index[1] = (int16_t) value;
  1701. ch->set_update = 1;
  1702. break;
  1703. case 0x30: /* DMA4_CDFI */
  1704. ch->frame_index[1] = (int32_t) value;
  1705. ch->set_update = 1;
  1706. break;
  1707. case 0x44: /* DMA4_COLOR */
  1708. /* XXX only in sDMA */
  1709. ch->color = value;
  1710. break;
  1711. case 0x34: /* DMA4_CSAC */
  1712. case 0x38: /* DMA4_CDAC */
  1713. case 0x3c: /* DMA4_CCEN */
  1714. case 0x40: /* DMA4_CCFN */
  1715. OMAP_RO_REG(addr);
  1716. break;
  1717. default:
  1718. OMAP_BAD_REG(addr);
  1719. }
  1720. }
  1721. static CPUReadMemoryFunc * const omap_dma4_readfn[] = {
  1722. omap_badwidth_read16,
  1723. omap_dma4_read,
  1724. omap_dma4_read,
  1725. };
  1726. static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
  1727. omap_badwidth_write16,
  1728. omap_dma4_write,
  1729. omap_dma4_write,
  1730. };
  1731. struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
  1732. struct omap_mpu_state_s *mpu, int fifo,
  1733. int chans, omap_clk iclk, omap_clk fclk)
  1734. {
  1735. int iomemtype, i;
  1736. struct omap_dma_s *s = (struct omap_dma_s *)
  1737. qemu_mallocz(sizeof(struct omap_dma_s));
  1738. s->model = omap_dma_4;
  1739. s->chans = chans;
  1740. s->mpu = mpu;
  1741. s->clk = fclk;
  1742. s->dma = soc_dma_init(s->chans);
  1743. s->dma->freq = omap_clk_getrate(fclk);
  1744. s->dma->transfer_fn = omap_dma_transfer_generic;
  1745. s->dma->setup_fn = omap_dma_transfer_setup;
  1746. s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
  1747. s->dma->opaque = s;
  1748. for (i = 0; i < s->chans; i ++) {
  1749. s->ch[i].dma = &s->dma->ch[i];
  1750. s->dma->ch[i].opaque = &s->ch[i];
  1751. }
  1752. memcpy(&s->irq, irqs, sizeof(s->irq));
  1753. s->intr_update = omap_dma_interrupts_4_update;
  1754. omap_dma_setcaps(s);
  1755. omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
  1756. omap_dma_reset(s->dma);
  1757. omap_dma_clk_update(s, 0, !!s->dma->freq);
  1758. iomemtype = cpu_register_io_memory(omap_dma4_readfn,
  1759. omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN);
  1760. cpu_register_physical_memory(base, 0x1000, iomemtype);
  1761. mpu->drq = s->dma->drq;
  1762. return s->dma;
  1763. }
  1764. struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
  1765. {
  1766. struct omap_dma_s *s = dma->opaque;
  1767. return &s->lcd_ch;
  1768. }