omap2.c 82 KB

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  1. /*
  2. * TI OMAP processors emulation.
  3. *
  4. * Copyright (C) 2007-2008 Nokia Corporation
  5. * Written by Andrzej Zaborowski <andrew@openedhand.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 or
  10. * (at your option) version 3 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include "blockdev.h"
  21. #include "hw.h"
  22. #include "arm-misc.h"
  23. #include "omap.h"
  24. #include "sysemu.h"
  25. #include "qemu-timer.h"
  26. #include "qemu-char.h"
  27. #include "flash.h"
  28. #include "soc_dma.h"
  29. #include "audio/audio.h"
  30. /* Enhanced Audio Controller (CODEC only) */
  31. struct omap_eac_s {
  32. qemu_irq irq;
  33. uint16_t sysconfig;
  34. uint8_t config[4];
  35. uint8_t control;
  36. uint8_t address;
  37. uint16_t data;
  38. uint8_t vtol;
  39. uint8_t vtsl;
  40. uint16_t mixer;
  41. uint16_t gain[4];
  42. uint8_t att;
  43. uint16_t max[7];
  44. struct {
  45. qemu_irq txdrq;
  46. qemu_irq rxdrq;
  47. uint32_t (*txrx)(void *opaque, uint32_t, int);
  48. void *opaque;
  49. #define EAC_BUF_LEN 1024
  50. uint32_t rxbuf[EAC_BUF_LEN];
  51. int rxoff;
  52. int rxlen;
  53. int rxavail;
  54. uint32_t txbuf[EAC_BUF_LEN];
  55. int txlen;
  56. int txavail;
  57. int enable;
  58. int rate;
  59. uint16_t config[4];
  60. /* These need to be moved to the actual codec */
  61. QEMUSoundCard card;
  62. SWVoiceIn *in_voice;
  63. SWVoiceOut *out_voice;
  64. int hw_enable;
  65. } codec;
  66. struct {
  67. uint8_t control;
  68. uint16_t config;
  69. } modem, bt;
  70. };
  71. static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
  72. {
  73. qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
  74. }
  75. static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
  76. {
  77. qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
  78. ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
  79. }
  80. static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
  81. {
  82. qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
  83. ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
  84. }
  85. static inline void omap_eac_in_refill(struct omap_eac_s *s)
  86. {
  87. int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
  88. int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
  89. int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
  90. int recv = 1;
  91. uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
  92. left -= leftwrap;
  93. start = 0;
  94. while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
  95. leftwrap)) > 0) { /* Be defensive */
  96. start += recv;
  97. leftwrap -= recv;
  98. }
  99. if (recv <= 0)
  100. s->codec.rxavail = 0;
  101. else
  102. s->codec.rxavail -= start >> 2;
  103. s->codec.rxlen += start >> 2;
  104. if (recv > 0 && left > 0) {
  105. start = 0;
  106. while (left && (recv = AUD_read(s->codec.in_voice,
  107. (uint8_t *) s->codec.rxbuf + start,
  108. left)) > 0) { /* Be defensive */
  109. start += recv;
  110. left -= recv;
  111. }
  112. if (recv <= 0)
  113. s->codec.rxavail = 0;
  114. else
  115. s->codec.rxavail -= start >> 2;
  116. s->codec.rxlen += start >> 2;
  117. }
  118. }
  119. static inline void omap_eac_out_empty(struct omap_eac_s *s)
  120. {
  121. int left = s->codec.txlen << 2;
  122. int start = 0;
  123. int sent = 1;
  124. while (left && (sent = AUD_write(s->codec.out_voice,
  125. (uint8_t *) s->codec.txbuf + start,
  126. left)) > 0) { /* Be defensive */
  127. start += sent;
  128. left -= sent;
  129. }
  130. if (!sent) {
  131. s->codec.txavail = 0;
  132. omap_eac_out_dmarequest_update(s);
  133. }
  134. if (start)
  135. s->codec.txlen = 0;
  136. }
  137. static void omap_eac_in_cb(void *opaque, int avail_b)
  138. {
  139. struct omap_eac_s *s = (struct omap_eac_s *) opaque;
  140. s->codec.rxavail = avail_b >> 2;
  141. omap_eac_in_refill(s);
  142. /* TODO: possibly discard current buffer if overrun */
  143. omap_eac_in_dmarequest_update(s);
  144. }
  145. static void omap_eac_out_cb(void *opaque, int free_b)
  146. {
  147. struct omap_eac_s *s = (struct omap_eac_s *) opaque;
  148. s->codec.txavail = free_b >> 2;
  149. if (s->codec.txlen)
  150. omap_eac_out_empty(s);
  151. else
  152. omap_eac_out_dmarequest_update(s);
  153. }
  154. static void omap_eac_enable_update(struct omap_eac_s *s)
  155. {
  156. s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
  157. (s->codec.config[1] & 2) && /* AUDEN */
  158. s->codec.hw_enable;
  159. }
  160. static const int omap_eac_fsint[4] = {
  161. 8000,
  162. 11025,
  163. 22050,
  164. 44100,
  165. };
  166. static const int omap_eac_fsint2[8] = {
  167. 8000,
  168. 11025,
  169. 22050,
  170. 44100,
  171. 48000,
  172. 0, 0, 0,
  173. };
  174. static const int omap_eac_fsint3[16] = {
  175. 8000,
  176. 11025,
  177. 16000,
  178. 22050,
  179. 24000,
  180. 32000,
  181. 44100,
  182. 48000,
  183. 0, 0, 0, 0, 0, 0, 0, 0,
  184. };
  185. static void omap_eac_rate_update(struct omap_eac_s *s)
  186. {
  187. int fsint[3];
  188. fsint[2] = (s->codec.config[3] >> 9) & 0xf;
  189. fsint[1] = (s->codec.config[2] >> 0) & 0x7;
  190. fsint[0] = (s->codec.config[0] >> 6) & 0x3;
  191. if (fsint[2] < 0xf)
  192. s->codec.rate = omap_eac_fsint3[fsint[2]];
  193. else if (fsint[1] < 0x7)
  194. s->codec.rate = omap_eac_fsint2[fsint[1]];
  195. else
  196. s->codec.rate = omap_eac_fsint[fsint[0]];
  197. }
  198. static void omap_eac_volume_update(struct omap_eac_s *s)
  199. {
  200. /* TODO */
  201. }
  202. static void omap_eac_format_update(struct omap_eac_s *s)
  203. {
  204. struct audsettings fmt;
  205. /* The hardware buffers at most one sample */
  206. if (s->codec.rxlen)
  207. s->codec.rxlen = 1;
  208. if (s->codec.in_voice) {
  209. AUD_set_active_in(s->codec.in_voice, 0);
  210. AUD_close_in(&s->codec.card, s->codec.in_voice);
  211. s->codec.in_voice = NULL;
  212. }
  213. if (s->codec.out_voice) {
  214. omap_eac_out_empty(s);
  215. AUD_set_active_out(s->codec.out_voice, 0);
  216. AUD_close_out(&s->codec.card, s->codec.out_voice);
  217. s->codec.out_voice = NULL;
  218. s->codec.txavail = 0;
  219. }
  220. /* Discard what couldn't be written */
  221. s->codec.txlen = 0;
  222. omap_eac_enable_update(s);
  223. if (!s->codec.enable)
  224. return;
  225. omap_eac_rate_update(s);
  226. fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
  227. fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
  228. fmt.freq = s->codec.rate;
  229. /* TODO: signedness possibly depends on the CODEC hardware - or
  230. * does I2S specify it? */
  231. /* All register writes are 16 bits so we we store 16-bit samples
  232. * in the buffers regardless of AGCFR[B8_16] value. */
  233. fmt.fmt = AUD_FMT_U16;
  234. s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
  235. "eac.codec.in", s, omap_eac_in_cb, &fmt);
  236. s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
  237. "eac.codec.out", s, omap_eac_out_cb, &fmt);
  238. omap_eac_volume_update(s);
  239. AUD_set_active_in(s->codec.in_voice, 1);
  240. AUD_set_active_out(s->codec.out_voice, 1);
  241. }
  242. static void omap_eac_reset(struct omap_eac_s *s)
  243. {
  244. s->sysconfig = 0;
  245. s->config[0] = 0x0c;
  246. s->config[1] = 0x09;
  247. s->config[2] = 0xab;
  248. s->config[3] = 0x03;
  249. s->control = 0x00;
  250. s->address = 0x00;
  251. s->data = 0x0000;
  252. s->vtol = 0x00;
  253. s->vtsl = 0x00;
  254. s->mixer = 0x0000;
  255. s->gain[0] = 0xe7e7;
  256. s->gain[1] = 0x6767;
  257. s->gain[2] = 0x6767;
  258. s->gain[3] = 0x6767;
  259. s->att = 0xce;
  260. s->max[0] = 0;
  261. s->max[1] = 0;
  262. s->max[2] = 0;
  263. s->max[3] = 0;
  264. s->max[4] = 0;
  265. s->max[5] = 0;
  266. s->max[6] = 0;
  267. s->modem.control = 0x00;
  268. s->modem.config = 0x0000;
  269. s->bt.control = 0x00;
  270. s->bt.config = 0x0000;
  271. s->codec.config[0] = 0x0649;
  272. s->codec.config[1] = 0x0000;
  273. s->codec.config[2] = 0x0007;
  274. s->codec.config[3] = 0x1ffc;
  275. s->codec.rxoff = 0;
  276. s->codec.rxlen = 0;
  277. s->codec.txlen = 0;
  278. s->codec.rxavail = 0;
  279. s->codec.txavail = 0;
  280. omap_eac_format_update(s);
  281. omap_eac_interrupt_update(s);
  282. }
  283. static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
  284. {
  285. struct omap_eac_s *s = (struct omap_eac_s *) opaque;
  286. uint32_t ret;
  287. switch (addr) {
  288. case 0x000: /* CPCFR1 */
  289. return s->config[0];
  290. case 0x004: /* CPCFR2 */
  291. return s->config[1];
  292. case 0x008: /* CPCFR3 */
  293. return s->config[2];
  294. case 0x00c: /* CPCFR4 */
  295. return s->config[3];
  296. case 0x010: /* CPTCTL */
  297. return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
  298. ((s->codec.txlen < s->codec.txavail) << 5);
  299. case 0x014: /* CPTTADR */
  300. return s->address;
  301. case 0x018: /* CPTDATL */
  302. return s->data & 0xff;
  303. case 0x01c: /* CPTDATH */
  304. return s->data >> 8;
  305. case 0x020: /* CPTVSLL */
  306. return s->vtol;
  307. case 0x024: /* CPTVSLH */
  308. return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
  309. case 0x040: /* MPCTR */
  310. return s->modem.control;
  311. case 0x044: /* MPMCCFR */
  312. return s->modem.config;
  313. case 0x060: /* BPCTR */
  314. return s->bt.control;
  315. case 0x064: /* BPMCCFR */
  316. return s->bt.config;
  317. case 0x080: /* AMSCFR */
  318. return s->mixer;
  319. case 0x084: /* AMVCTR */
  320. return s->gain[0];
  321. case 0x088: /* AM1VCTR */
  322. return s->gain[1];
  323. case 0x08c: /* AM2VCTR */
  324. return s->gain[2];
  325. case 0x090: /* AM3VCTR */
  326. return s->gain[3];
  327. case 0x094: /* ASTCTR */
  328. return s->att;
  329. case 0x098: /* APD1LCR */
  330. return s->max[0];
  331. case 0x09c: /* APD1RCR */
  332. return s->max[1];
  333. case 0x0a0: /* APD2LCR */
  334. return s->max[2];
  335. case 0x0a4: /* APD2RCR */
  336. return s->max[3];
  337. case 0x0a8: /* APD3LCR */
  338. return s->max[4];
  339. case 0x0ac: /* APD3RCR */
  340. return s->max[5];
  341. case 0x0b0: /* APD4R */
  342. return s->max[6];
  343. case 0x0b4: /* ADWR */
  344. /* This should be write-only? Docs list it as read-only. */
  345. return 0x0000;
  346. case 0x0b8: /* ADRDR */
  347. if (likely(s->codec.rxlen > 1)) {
  348. ret = s->codec.rxbuf[s->codec.rxoff ++];
  349. s->codec.rxlen --;
  350. s->codec.rxoff &= EAC_BUF_LEN - 1;
  351. return ret;
  352. } else if (s->codec.rxlen) {
  353. ret = s->codec.rxbuf[s->codec.rxoff ++];
  354. s->codec.rxlen --;
  355. s->codec.rxoff &= EAC_BUF_LEN - 1;
  356. if (s->codec.rxavail)
  357. omap_eac_in_refill(s);
  358. omap_eac_in_dmarequest_update(s);
  359. return ret;
  360. }
  361. return 0x0000;
  362. case 0x0bc: /* AGCFR */
  363. return s->codec.config[0];
  364. case 0x0c0: /* AGCTR */
  365. return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
  366. case 0x0c4: /* AGCFR2 */
  367. return s->codec.config[2];
  368. case 0x0c8: /* AGCFR3 */
  369. return s->codec.config[3];
  370. case 0x0cc: /* MBPDMACTR */
  371. case 0x0d0: /* MPDDMARR */
  372. case 0x0d8: /* MPUDMARR */
  373. case 0x0e4: /* BPDDMARR */
  374. case 0x0ec: /* BPUDMARR */
  375. return 0x0000;
  376. case 0x100: /* VERSION_NUMBER */
  377. return 0x0010;
  378. case 0x104: /* SYSCONFIG */
  379. return s->sysconfig;
  380. case 0x108: /* SYSSTATUS */
  381. return 1 | 0xe; /* RESETDONE | stuff */
  382. }
  383. OMAP_BAD_REG(addr);
  384. return 0;
  385. }
  386. static void omap_eac_write(void *opaque, target_phys_addr_t addr,
  387. uint32_t value)
  388. {
  389. struct omap_eac_s *s = (struct omap_eac_s *) opaque;
  390. switch (addr) {
  391. case 0x098: /* APD1LCR */
  392. case 0x09c: /* APD1RCR */
  393. case 0x0a0: /* APD2LCR */
  394. case 0x0a4: /* APD2RCR */
  395. case 0x0a8: /* APD3LCR */
  396. case 0x0ac: /* APD3RCR */
  397. case 0x0b0: /* APD4R */
  398. case 0x0b8: /* ADRDR */
  399. case 0x0d0: /* MPDDMARR */
  400. case 0x0d8: /* MPUDMARR */
  401. case 0x0e4: /* BPDDMARR */
  402. case 0x0ec: /* BPUDMARR */
  403. case 0x100: /* VERSION_NUMBER */
  404. case 0x108: /* SYSSTATUS */
  405. OMAP_RO_REG(addr);
  406. return;
  407. case 0x000: /* CPCFR1 */
  408. s->config[0] = value & 0xff;
  409. omap_eac_format_update(s);
  410. break;
  411. case 0x004: /* CPCFR2 */
  412. s->config[1] = value & 0xff;
  413. omap_eac_format_update(s);
  414. break;
  415. case 0x008: /* CPCFR3 */
  416. s->config[2] = value & 0xff;
  417. omap_eac_format_update(s);
  418. break;
  419. case 0x00c: /* CPCFR4 */
  420. s->config[3] = value & 0xff;
  421. omap_eac_format_update(s);
  422. break;
  423. case 0x010: /* CPTCTL */
  424. /* Assuming TXF and TXE bits are read-only... */
  425. s->control = value & 0x5f;
  426. omap_eac_interrupt_update(s);
  427. break;
  428. case 0x014: /* CPTTADR */
  429. s->address = value & 0xff;
  430. break;
  431. case 0x018: /* CPTDATL */
  432. s->data &= 0xff00;
  433. s->data |= value & 0xff;
  434. break;
  435. case 0x01c: /* CPTDATH */
  436. s->data &= 0x00ff;
  437. s->data |= value << 8;
  438. break;
  439. case 0x020: /* CPTVSLL */
  440. s->vtol = value & 0xf8;
  441. break;
  442. case 0x024: /* CPTVSLH */
  443. s->vtsl = value & 0x9f;
  444. break;
  445. case 0x040: /* MPCTR */
  446. s->modem.control = value & 0x8f;
  447. break;
  448. case 0x044: /* MPMCCFR */
  449. s->modem.config = value & 0x7fff;
  450. break;
  451. case 0x060: /* BPCTR */
  452. s->bt.control = value & 0x8f;
  453. break;
  454. case 0x064: /* BPMCCFR */
  455. s->bt.config = value & 0x7fff;
  456. break;
  457. case 0x080: /* AMSCFR */
  458. s->mixer = value & 0x0fff;
  459. break;
  460. case 0x084: /* AMVCTR */
  461. s->gain[0] = value & 0xffff;
  462. break;
  463. case 0x088: /* AM1VCTR */
  464. s->gain[1] = value & 0xff7f;
  465. break;
  466. case 0x08c: /* AM2VCTR */
  467. s->gain[2] = value & 0xff7f;
  468. break;
  469. case 0x090: /* AM3VCTR */
  470. s->gain[3] = value & 0xff7f;
  471. break;
  472. case 0x094: /* ASTCTR */
  473. s->att = value & 0xff;
  474. break;
  475. case 0x0b4: /* ADWR */
  476. s->codec.txbuf[s->codec.txlen ++] = value;
  477. if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
  478. s->codec.txlen == s->codec.txavail)) {
  479. if (s->codec.txavail)
  480. omap_eac_out_empty(s);
  481. /* Discard what couldn't be written */
  482. s->codec.txlen = 0;
  483. }
  484. break;
  485. case 0x0bc: /* AGCFR */
  486. s->codec.config[0] = value & 0x07ff;
  487. omap_eac_format_update(s);
  488. break;
  489. case 0x0c0: /* AGCTR */
  490. s->codec.config[1] = value & 0x780f;
  491. omap_eac_format_update(s);
  492. break;
  493. case 0x0c4: /* AGCFR2 */
  494. s->codec.config[2] = value & 0x003f;
  495. omap_eac_format_update(s);
  496. break;
  497. case 0x0c8: /* AGCFR3 */
  498. s->codec.config[3] = value & 0xffff;
  499. omap_eac_format_update(s);
  500. break;
  501. case 0x0cc: /* MBPDMACTR */
  502. case 0x0d4: /* MPDDMAWR */
  503. case 0x0e0: /* MPUDMAWR */
  504. case 0x0e8: /* BPDDMAWR */
  505. case 0x0f0: /* BPUDMAWR */
  506. break;
  507. case 0x104: /* SYSCONFIG */
  508. if (value & (1 << 1)) /* SOFTRESET */
  509. omap_eac_reset(s);
  510. s->sysconfig = value & 0x31d;
  511. break;
  512. default:
  513. OMAP_BAD_REG(addr);
  514. return;
  515. }
  516. }
  517. static CPUReadMemoryFunc * const omap_eac_readfn[] = {
  518. omap_badwidth_read16,
  519. omap_eac_read,
  520. omap_badwidth_read16,
  521. };
  522. static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
  523. omap_badwidth_write16,
  524. omap_eac_write,
  525. omap_badwidth_write16,
  526. };
  527. static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
  528. qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
  529. {
  530. int iomemtype;
  531. struct omap_eac_s *s = (struct omap_eac_s *)
  532. qemu_mallocz(sizeof(struct omap_eac_s));
  533. s->irq = irq;
  534. s->codec.rxdrq = *drq ++;
  535. s->codec.txdrq = *drq;
  536. omap_eac_reset(s);
  537. AUD_register_card("OMAP EAC", &s->codec.card);
  538. iomemtype = cpu_register_io_memory(omap_eac_readfn,
  539. omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN);
  540. omap_l4_attach(ta, 0, iomemtype);
  541. return s;
  542. }
  543. /* STI/XTI (emulation interface) console - reverse engineered only */
  544. struct omap_sti_s {
  545. qemu_irq irq;
  546. CharDriverState *chr;
  547. uint32_t sysconfig;
  548. uint32_t systest;
  549. uint32_t irqst;
  550. uint32_t irqen;
  551. uint32_t clkcontrol;
  552. uint32_t serial_config;
  553. };
  554. #define STI_TRACE_CONSOLE_CHANNEL 239
  555. #define STI_TRACE_CONTROL_CHANNEL 253
  556. static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
  557. {
  558. qemu_set_irq(s->irq, s->irqst & s->irqen);
  559. }
  560. static void omap_sti_reset(struct omap_sti_s *s)
  561. {
  562. s->sysconfig = 0;
  563. s->irqst = 0;
  564. s->irqen = 0;
  565. s->clkcontrol = 0;
  566. s->serial_config = 0;
  567. omap_sti_interrupt_update(s);
  568. }
  569. static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
  570. {
  571. struct omap_sti_s *s = (struct omap_sti_s *) opaque;
  572. switch (addr) {
  573. case 0x00: /* STI_REVISION */
  574. return 0x10;
  575. case 0x10: /* STI_SYSCONFIG */
  576. return s->sysconfig;
  577. case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
  578. return 0x00;
  579. case 0x18: /* STI_IRQSTATUS */
  580. return s->irqst;
  581. case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
  582. return s->irqen;
  583. case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
  584. case 0x28: /* STI_RX_DR / XTI_RXDATA */
  585. /* TODO */
  586. return 0;
  587. case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
  588. return s->clkcontrol;
  589. case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
  590. return s->serial_config;
  591. }
  592. OMAP_BAD_REG(addr);
  593. return 0;
  594. }
  595. static void omap_sti_write(void *opaque, target_phys_addr_t addr,
  596. uint32_t value)
  597. {
  598. struct omap_sti_s *s = (struct omap_sti_s *) opaque;
  599. switch (addr) {
  600. case 0x00: /* STI_REVISION */
  601. case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
  602. OMAP_RO_REG(addr);
  603. return;
  604. case 0x10: /* STI_SYSCONFIG */
  605. if (value & (1 << 1)) /* SOFTRESET */
  606. omap_sti_reset(s);
  607. s->sysconfig = value & 0xfe;
  608. break;
  609. case 0x18: /* STI_IRQSTATUS */
  610. s->irqst &= ~value;
  611. omap_sti_interrupt_update(s);
  612. break;
  613. case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
  614. s->irqen = value & 0xffff;
  615. omap_sti_interrupt_update(s);
  616. break;
  617. case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
  618. s->clkcontrol = value & 0xff;
  619. break;
  620. case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
  621. s->serial_config = value & 0xff;
  622. break;
  623. case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
  624. case 0x28: /* STI_RX_DR / XTI_RXDATA */
  625. /* TODO */
  626. return;
  627. default:
  628. OMAP_BAD_REG(addr);
  629. return;
  630. }
  631. }
  632. static CPUReadMemoryFunc * const omap_sti_readfn[] = {
  633. omap_badwidth_read32,
  634. omap_badwidth_read32,
  635. omap_sti_read,
  636. };
  637. static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
  638. omap_badwidth_write32,
  639. omap_badwidth_write32,
  640. omap_sti_write,
  641. };
  642. static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
  643. {
  644. OMAP_BAD_REG(addr);
  645. return 0;
  646. }
  647. static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
  648. uint32_t value)
  649. {
  650. struct omap_sti_s *s = (struct omap_sti_s *) opaque;
  651. int ch = addr >> 6;
  652. uint8_t byte = value;
  653. if (ch == STI_TRACE_CONTROL_CHANNEL) {
  654. /* Flush channel <i>value</i>. */
  655. qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
  656. } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
  657. if (value == 0xc0 || value == 0xc3) {
  658. /* Open channel <i>ch</i>. */
  659. } else if (value == 0x00)
  660. qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
  661. else
  662. qemu_chr_write(s->chr, &byte, 1);
  663. }
  664. }
  665. static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
  666. omap_sti_fifo_read,
  667. omap_badwidth_read8,
  668. omap_badwidth_read8,
  669. };
  670. static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
  671. omap_sti_fifo_write,
  672. omap_badwidth_write8,
  673. omap_badwidth_write8,
  674. };
  675. static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
  676. target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
  677. CharDriverState *chr)
  678. {
  679. int iomemtype;
  680. struct omap_sti_s *s = (struct omap_sti_s *)
  681. qemu_mallocz(sizeof(struct omap_sti_s));
  682. s->irq = irq;
  683. omap_sti_reset(s);
  684. s->chr = chr ?: qemu_chr_open("null", "null", NULL);
  685. iomemtype = l4_register_io_memory(omap_sti_readfn,
  686. omap_sti_writefn, s);
  687. omap_l4_attach(ta, 0, iomemtype);
  688. iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
  689. omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN);
  690. cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
  691. return s;
  692. }
  693. /* L4 Interconnect */
  694. #define L4TA(n) (n)
  695. #define L4TAO(n) ((n) + 39)
  696. static const struct omap_l4_region_s omap_l4_region[125] = {
  697. [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
  698. [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
  699. [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
  700. [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
  701. [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
  702. [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
  703. [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
  704. [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
  705. [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
  706. [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
  707. [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
  708. [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
  709. [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
  710. [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
  711. [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
  712. [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
  713. [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
  714. [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
  715. [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
  716. [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
  717. [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
  718. [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
  719. [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
  720. [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
  721. [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
  722. [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
  723. [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
  724. [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
  725. [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
  726. [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
  727. [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
  728. [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
  729. [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
  730. [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
  731. [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
  732. [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
  733. [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
  734. [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
  735. [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
  736. [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
  737. [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
  738. [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
  739. [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
  740. [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
  741. [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
  742. [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
  743. [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
  744. [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
  745. [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
  746. [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
  747. [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
  748. [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
  749. [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
  750. [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
  751. [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
  752. [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
  753. [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
  754. [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
  755. [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
  756. [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
  757. [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
  758. [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
  759. [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
  760. [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
  761. [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
  762. [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
  763. [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
  764. [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
  765. [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
  766. [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
  767. [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
  768. [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
  769. [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
  770. [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
  771. [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
  772. [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
  773. [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
  774. [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
  775. [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
  776. [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
  777. [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
  778. [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
  779. [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
  780. [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
  781. [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
  782. [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
  783. [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
  784. [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
  785. [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
  786. [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
  787. [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
  788. [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
  789. [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
  790. [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
  791. [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
  792. [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
  793. [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
  794. [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
  795. [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
  796. [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
  797. [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
  798. [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
  799. [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
  800. [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
  801. [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
  802. [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
  803. [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
  804. [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
  805. [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
  806. [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
  807. [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
  808. [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
  809. [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
  810. [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
  811. [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
  812. [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
  813. [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
  814. [117] = { 0xa6000, 0x1000, 32 }, /* AES */
  815. [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
  816. [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
  817. [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
  818. [121] = { 0xb0000, 0x1000, 32 }, /* MG */
  819. [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
  820. [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
  821. [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
  822. };
  823. static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
  824. { 0, 0, 3, 2 }, /* L4IA initiatior agent */
  825. { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
  826. { L4TAO(2), 5, 2, 1 }, /* 32K timer */
  827. { L4TAO(3), 7, 3, 2 }, /* PRCM */
  828. { L4TA(1), 10, 2, 1 }, /* BCM */
  829. { L4TA(2), 12, 2, 1 }, /* Test JTAG */
  830. { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
  831. { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
  832. { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
  833. { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
  834. { L4TA(10), 28, 5, 4 }, /* Display subsystem */
  835. { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
  836. { L4TA(12), 38, 2, 1 }, /* sDMA */
  837. { L4TA(13), 40, 5, 4 }, /* SSI */
  838. { L4TAO(4), 45, 2, 1 }, /* USB */
  839. { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
  840. { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
  841. { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
  842. { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
  843. { L4TA(18), 55, 2, 1 }, /* XTI */
  844. { L4TA(19), 57, 2, 1 }, /* UART1 */
  845. { L4TA(20), 59, 2, 1 }, /* UART2 */
  846. { L4TA(21), 61, 2, 1 }, /* UART3 */
  847. { L4TAO(5), 63, 2, 1 }, /* I2C1 */
  848. { L4TAO(6), 65, 2, 1 }, /* I2C2 */
  849. { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
  850. { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
  851. { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
  852. { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
  853. { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
  854. { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
  855. { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
  856. { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
  857. { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
  858. { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
  859. { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
  860. { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
  861. { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
  862. { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
  863. { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
  864. { L4TA(32), 97, 2, 1 }, /* EAC */
  865. { L4TA(33), 99, 2, 1 }, /* FAC */
  866. { L4TA(34), 101, 2, 1 }, /* IPC */
  867. { L4TA(35), 103, 2, 1 }, /* SPI1 */
  868. { L4TA(36), 105, 2, 1 }, /* SPI2 */
  869. { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
  870. { L4TAO(10), 109, 2, 1 },
  871. { L4TAO(11), 111, 2, 1 }, /* RNG */
  872. { L4TAO(12), 113, 2, 1 }, /* DES3DES */
  873. { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
  874. { L4TA(37), 117, 2, 1 }, /* AES */
  875. { L4TA(38), 119, 2, 1 }, /* PKA */
  876. { -1, 121, 2, 1 },
  877. { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
  878. };
  879. #define omap_l4ta(bus, cs) \
  880. omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
  881. #define omap_l4tao(bus, cs) \
  882. omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
  883. /* Power, Reset, and Clock Management */
  884. struct omap_prcm_s {
  885. qemu_irq irq[3];
  886. struct omap_mpu_state_s *mpu;
  887. uint32_t irqst[3];
  888. uint32_t irqen[3];
  889. uint32_t sysconfig;
  890. uint32_t voltctrl;
  891. uint32_t scratch[20];
  892. uint32_t clksrc[1];
  893. uint32_t clkout[1];
  894. uint32_t clkemul[1];
  895. uint32_t clkpol[1];
  896. uint32_t clksel[8];
  897. uint32_t clken[12];
  898. uint32_t clkctrl[4];
  899. uint32_t clkidle[7];
  900. uint32_t setuptime[2];
  901. uint32_t wkup[3];
  902. uint32_t wken[3];
  903. uint32_t wkst[3];
  904. uint32_t rst[4];
  905. uint32_t rstctrl[1];
  906. uint32_t power[4];
  907. uint32_t rsttime_wkup;
  908. uint32_t ev;
  909. uint32_t evtime[2];
  910. int dpll_lock, apll_lock[2];
  911. };
  912. static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
  913. {
  914. qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
  915. /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
  916. }
  917. static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
  918. {
  919. struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
  920. uint32_t ret;
  921. switch (addr) {
  922. case 0x000: /* PRCM_REVISION */
  923. return 0x10;
  924. case 0x010: /* PRCM_SYSCONFIG */
  925. return s->sysconfig;
  926. case 0x018: /* PRCM_IRQSTATUS_MPU */
  927. return s->irqst[0];
  928. case 0x01c: /* PRCM_IRQENABLE_MPU */
  929. return s->irqen[0];
  930. case 0x050: /* PRCM_VOLTCTRL */
  931. return s->voltctrl;
  932. case 0x054: /* PRCM_VOLTST */
  933. return s->voltctrl & 3;
  934. case 0x060: /* PRCM_CLKSRC_CTRL */
  935. return s->clksrc[0];
  936. case 0x070: /* PRCM_CLKOUT_CTRL */
  937. return s->clkout[0];
  938. case 0x078: /* PRCM_CLKEMUL_CTRL */
  939. return s->clkemul[0];
  940. case 0x080: /* PRCM_CLKCFG_CTRL */
  941. case 0x084: /* PRCM_CLKCFG_STATUS */
  942. return 0;
  943. case 0x090: /* PRCM_VOLTSETUP */
  944. return s->setuptime[0];
  945. case 0x094: /* PRCM_CLKSSETUP */
  946. return s->setuptime[1];
  947. case 0x098: /* PRCM_POLCTRL */
  948. return s->clkpol[0];
  949. case 0x0b0: /* GENERAL_PURPOSE1 */
  950. case 0x0b4: /* GENERAL_PURPOSE2 */
  951. case 0x0b8: /* GENERAL_PURPOSE3 */
  952. case 0x0bc: /* GENERAL_PURPOSE4 */
  953. case 0x0c0: /* GENERAL_PURPOSE5 */
  954. case 0x0c4: /* GENERAL_PURPOSE6 */
  955. case 0x0c8: /* GENERAL_PURPOSE7 */
  956. case 0x0cc: /* GENERAL_PURPOSE8 */
  957. case 0x0d0: /* GENERAL_PURPOSE9 */
  958. case 0x0d4: /* GENERAL_PURPOSE10 */
  959. case 0x0d8: /* GENERAL_PURPOSE11 */
  960. case 0x0dc: /* GENERAL_PURPOSE12 */
  961. case 0x0e0: /* GENERAL_PURPOSE13 */
  962. case 0x0e4: /* GENERAL_PURPOSE14 */
  963. case 0x0e8: /* GENERAL_PURPOSE15 */
  964. case 0x0ec: /* GENERAL_PURPOSE16 */
  965. case 0x0f0: /* GENERAL_PURPOSE17 */
  966. case 0x0f4: /* GENERAL_PURPOSE18 */
  967. case 0x0f8: /* GENERAL_PURPOSE19 */
  968. case 0x0fc: /* GENERAL_PURPOSE20 */
  969. return s->scratch[(addr - 0xb0) >> 2];
  970. case 0x140: /* CM_CLKSEL_MPU */
  971. return s->clksel[0];
  972. case 0x148: /* CM_CLKSTCTRL_MPU */
  973. return s->clkctrl[0];
  974. case 0x158: /* RM_RSTST_MPU */
  975. return s->rst[0];
  976. case 0x1c8: /* PM_WKDEP_MPU */
  977. return s->wkup[0];
  978. case 0x1d4: /* PM_EVGENCTRL_MPU */
  979. return s->ev;
  980. case 0x1d8: /* PM_EVEGENONTIM_MPU */
  981. return s->evtime[0];
  982. case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
  983. return s->evtime[1];
  984. case 0x1e0: /* PM_PWSTCTRL_MPU */
  985. return s->power[0];
  986. case 0x1e4: /* PM_PWSTST_MPU */
  987. return 0;
  988. case 0x200: /* CM_FCLKEN1_CORE */
  989. return s->clken[0];
  990. case 0x204: /* CM_FCLKEN2_CORE */
  991. return s->clken[1];
  992. case 0x210: /* CM_ICLKEN1_CORE */
  993. return s->clken[2];
  994. case 0x214: /* CM_ICLKEN2_CORE */
  995. return s->clken[3];
  996. case 0x21c: /* CM_ICLKEN4_CORE */
  997. return s->clken[4];
  998. case 0x220: /* CM_IDLEST1_CORE */
  999. /* TODO: check the actual iclk status */
  1000. return 0x7ffffff9;
  1001. case 0x224: /* CM_IDLEST2_CORE */
  1002. /* TODO: check the actual iclk status */
  1003. return 0x00000007;
  1004. case 0x22c: /* CM_IDLEST4_CORE */
  1005. /* TODO: check the actual iclk status */
  1006. return 0x0000001f;
  1007. case 0x230: /* CM_AUTOIDLE1_CORE */
  1008. return s->clkidle[0];
  1009. case 0x234: /* CM_AUTOIDLE2_CORE */
  1010. return s->clkidle[1];
  1011. case 0x238: /* CM_AUTOIDLE3_CORE */
  1012. return s->clkidle[2];
  1013. case 0x23c: /* CM_AUTOIDLE4_CORE */
  1014. return s->clkidle[3];
  1015. case 0x240: /* CM_CLKSEL1_CORE */
  1016. return s->clksel[1];
  1017. case 0x244: /* CM_CLKSEL2_CORE */
  1018. return s->clksel[2];
  1019. case 0x248: /* CM_CLKSTCTRL_CORE */
  1020. return s->clkctrl[1];
  1021. case 0x2a0: /* PM_WKEN1_CORE */
  1022. return s->wken[0];
  1023. case 0x2a4: /* PM_WKEN2_CORE */
  1024. return s->wken[1];
  1025. case 0x2b0: /* PM_WKST1_CORE */
  1026. return s->wkst[0];
  1027. case 0x2b4: /* PM_WKST2_CORE */
  1028. return s->wkst[1];
  1029. case 0x2c8: /* PM_WKDEP_CORE */
  1030. return 0x1e;
  1031. case 0x2e0: /* PM_PWSTCTRL_CORE */
  1032. return s->power[1];
  1033. case 0x2e4: /* PM_PWSTST_CORE */
  1034. return 0x000030 | (s->power[1] & 0xfc00);
  1035. case 0x300: /* CM_FCLKEN_GFX */
  1036. return s->clken[5];
  1037. case 0x310: /* CM_ICLKEN_GFX */
  1038. return s->clken[6];
  1039. case 0x320: /* CM_IDLEST_GFX */
  1040. /* TODO: check the actual iclk status */
  1041. return 0x00000001;
  1042. case 0x340: /* CM_CLKSEL_GFX */
  1043. return s->clksel[3];
  1044. case 0x348: /* CM_CLKSTCTRL_GFX */
  1045. return s->clkctrl[2];
  1046. case 0x350: /* RM_RSTCTRL_GFX */
  1047. return s->rstctrl[0];
  1048. case 0x358: /* RM_RSTST_GFX */
  1049. return s->rst[1];
  1050. case 0x3c8: /* PM_WKDEP_GFX */
  1051. return s->wkup[1];
  1052. case 0x3e0: /* PM_PWSTCTRL_GFX */
  1053. return s->power[2];
  1054. case 0x3e4: /* PM_PWSTST_GFX */
  1055. return s->power[2] & 3;
  1056. case 0x400: /* CM_FCLKEN_WKUP */
  1057. return s->clken[7];
  1058. case 0x410: /* CM_ICLKEN_WKUP */
  1059. return s->clken[8];
  1060. case 0x420: /* CM_IDLEST_WKUP */
  1061. /* TODO: check the actual iclk status */
  1062. return 0x0000003f;
  1063. case 0x430: /* CM_AUTOIDLE_WKUP */
  1064. return s->clkidle[4];
  1065. case 0x440: /* CM_CLKSEL_WKUP */
  1066. return s->clksel[4];
  1067. case 0x450: /* RM_RSTCTRL_WKUP */
  1068. return 0;
  1069. case 0x454: /* RM_RSTTIME_WKUP */
  1070. return s->rsttime_wkup;
  1071. case 0x458: /* RM_RSTST_WKUP */
  1072. return s->rst[2];
  1073. case 0x4a0: /* PM_WKEN_WKUP */
  1074. return s->wken[2];
  1075. case 0x4b0: /* PM_WKST_WKUP */
  1076. return s->wkst[2];
  1077. case 0x500: /* CM_CLKEN_PLL */
  1078. return s->clken[9];
  1079. case 0x520: /* CM_IDLEST_CKGEN */
  1080. ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
  1081. if (!(s->clksel[6] & 3))
  1082. /* Core uses 32-kHz clock */
  1083. ret |= 3 << 0;
  1084. else if (!s->dpll_lock)
  1085. /* DPLL not locked, core uses ref_clk */
  1086. ret |= 1 << 0;
  1087. else
  1088. /* Core uses DPLL */
  1089. ret |= 2 << 0;
  1090. return ret;
  1091. case 0x530: /* CM_AUTOIDLE_PLL */
  1092. return s->clkidle[5];
  1093. case 0x540: /* CM_CLKSEL1_PLL */
  1094. return s->clksel[5];
  1095. case 0x544: /* CM_CLKSEL2_PLL */
  1096. return s->clksel[6];
  1097. case 0x800: /* CM_FCLKEN_DSP */
  1098. return s->clken[10];
  1099. case 0x810: /* CM_ICLKEN_DSP */
  1100. return s->clken[11];
  1101. case 0x820: /* CM_IDLEST_DSP */
  1102. /* TODO: check the actual iclk status */
  1103. return 0x00000103;
  1104. case 0x830: /* CM_AUTOIDLE_DSP */
  1105. return s->clkidle[6];
  1106. case 0x840: /* CM_CLKSEL_DSP */
  1107. return s->clksel[7];
  1108. case 0x848: /* CM_CLKSTCTRL_DSP */
  1109. return s->clkctrl[3];
  1110. case 0x850: /* RM_RSTCTRL_DSP */
  1111. return 0;
  1112. case 0x858: /* RM_RSTST_DSP */
  1113. return s->rst[3];
  1114. case 0x8c8: /* PM_WKDEP_DSP */
  1115. return s->wkup[2];
  1116. case 0x8e0: /* PM_PWSTCTRL_DSP */
  1117. return s->power[3];
  1118. case 0x8e4: /* PM_PWSTST_DSP */
  1119. return 0x008030 | (s->power[3] & 0x3003);
  1120. case 0x8f0: /* PRCM_IRQSTATUS_DSP */
  1121. return s->irqst[1];
  1122. case 0x8f4: /* PRCM_IRQENABLE_DSP */
  1123. return s->irqen[1];
  1124. case 0x8f8: /* PRCM_IRQSTATUS_IVA */
  1125. return s->irqst[2];
  1126. case 0x8fc: /* PRCM_IRQENABLE_IVA */
  1127. return s->irqen[2];
  1128. }
  1129. OMAP_BAD_REG(addr);
  1130. return 0;
  1131. }
  1132. static void omap_prcm_apll_update(struct omap_prcm_s *s)
  1133. {
  1134. int mode[2];
  1135. mode[0] = (s->clken[9] >> 6) & 3;
  1136. s->apll_lock[0] = (mode[0] == 3);
  1137. mode[1] = (s->clken[9] >> 2) & 3;
  1138. s->apll_lock[1] = (mode[1] == 3);
  1139. /* TODO: update clocks */
  1140. if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
  1141. fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
  1142. __FUNCTION__);
  1143. }
  1144. static void omap_prcm_dpll_update(struct omap_prcm_s *s)
  1145. {
  1146. omap_clk dpll = omap_findclk(s->mpu, "dpll");
  1147. omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
  1148. omap_clk core = omap_findclk(s->mpu, "core_clk");
  1149. int mode = (s->clken[9] >> 0) & 3;
  1150. int mult, div;
  1151. mult = (s->clksel[5] >> 12) & 0x3ff;
  1152. div = (s->clksel[5] >> 8) & 0xf;
  1153. if (mult == 0 || mult == 1)
  1154. mode = 1; /* Bypass */
  1155. s->dpll_lock = 0;
  1156. switch (mode) {
  1157. case 0:
  1158. fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
  1159. break;
  1160. case 1: /* Low-power bypass mode (Default) */
  1161. case 2: /* Fast-relock bypass mode */
  1162. omap_clk_setrate(dpll, 1, 1);
  1163. omap_clk_setrate(dpll_x2, 1, 1);
  1164. break;
  1165. case 3: /* Lock mode */
  1166. s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
  1167. omap_clk_setrate(dpll, div + 1, mult);
  1168. omap_clk_setrate(dpll_x2, div + 1, mult * 2);
  1169. break;
  1170. }
  1171. switch ((s->clksel[6] >> 0) & 3) {
  1172. case 0:
  1173. omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
  1174. break;
  1175. case 1:
  1176. omap_clk_reparent(core, dpll);
  1177. break;
  1178. case 2:
  1179. /* Default */
  1180. omap_clk_reparent(core, dpll_x2);
  1181. break;
  1182. case 3:
  1183. fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
  1184. break;
  1185. }
  1186. }
  1187. static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
  1188. uint32_t value)
  1189. {
  1190. struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
  1191. switch (addr) {
  1192. case 0x000: /* PRCM_REVISION */
  1193. case 0x054: /* PRCM_VOLTST */
  1194. case 0x084: /* PRCM_CLKCFG_STATUS */
  1195. case 0x1e4: /* PM_PWSTST_MPU */
  1196. case 0x220: /* CM_IDLEST1_CORE */
  1197. case 0x224: /* CM_IDLEST2_CORE */
  1198. case 0x22c: /* CM_IDLEST4_CORE */
  1199. case 0x2c8: /* PM_WKDEP_CORE */
  1200. case 0x2e4: /* PM_PWSTST_CORE */
  1201. case 0x320: /* CM_IDLEST_GFX */
  1202. case 0x3e4: /* PM_PWSTST_GFX */
  1203. case 0x420: /* CM_IDLEST_WKUP */
  1204. case 0x520: /* CM_IDLEST_CKGEN */
  1205. case 0x820: /* CM_IDLEST_DSP */
  1206. case 0x8e4: /* PM_PWSTST_DSP */
  1207. OMAP_RO_REG(addr);
  1208. return;
  1209. case 0x010: /* PRCM_SYSCONFIG */
  1210. s->sysconfig = value & 1;
  1211. break;
  1212. case 0x018: /* PRCM_IRQSTATUS_MPU */
  1213. s->irqst[0] &= ~value;
  1214. omap_prcm_int_update(s, 0);
  1215. break;
  1216. case 0x01c: /* PRCM_IRQENABLE_MPU */
  1217. s->irqen[0] = value & 0x3f;
  1218. omap_prcm_int_update(s, 0);
  1219. break;
  1220. case 0x050: /* PRCM_VOLTCTRL */
  1221. s->voltctrl = value & 0xf1c3;
  1222. break;
  1223. case 0x060: /* PRCM_CLKSRC_CTRL */
  1224. s->clksrc[0] = value & 0xdb;
  1225. /* TODO update clocks */
  1226. break;
  1227. case 0x070: /* PRCM_CLKOUT_CTRL */
  1228. s->clkout[0] = value & 0xbbbb;
  1229. /* TODO update clocks */
  1230. break;
  1231. case 0x078: /* PRCM_CLKEMUL_CTRL */
  1232. s->clkemul[0] = value & 1;
  1233. /* TODO update clocks */
  1234. break;
  1235. case 0x080: /* PRCM_CLKCFG_CTRL */
  1236. break;
  1237. case 0x090: /* PRCM_VOLTSETUP */
  1238. s->setuptime[0] = value & 0xffff;
  1239. break;
  1240. case 0x094: /* PRCM_CLKSSETUP */
  1241. s->setuptime[1] = value & 0xffff;
  1242. break;
  1243. case 0x098: /* PRCM_POLCTRL */
  1244. s->clkpol[0] = value & 0x701;
  1245. break;
  1246. case 0x0b0: /* GENERAL_PURPOSE1 */
  1247. case 0x0b4: /* GENERAL_PURPOSE2 */
  1248. case 0x0b8: /* GENERAL_PURPOSE3 */
  1249. case 0x0bc: /* GENERAL_PURPOSE4 */
  1250. case 0x0c0: /* GENERAL_PURPOSE5 */
  1251. case 0x0c4: /* GENERAL_PURPOSE6 */
  1252. case 0x0c8: /* GENERAL_PURPOSE7 */
  1253. case 0x0cc: /* GENERAL_PURPOSE8 */
  1254. case 0x0d0: /* GENERAL_PURPOSE9 */
  1255. case 0x0d4: /* GENERAL_PURPOSE10 */
  1256. case 0x0d8: /* GENERAL_PURPOSE11 */
  1257. case 0x0dc: /* GENERAL_PURPOSE12 */
  1258. case 0x0e0: /* GENERAL_PURPOSE13 */
  1259. case 0x0e4: /* GENERAL_PURPOSE14 */
  1260. case 0x0e8: /* GENERAL_PURPOSE15 */
  1261. case 0x0ec: /* GENERAL_PURPOSE16 */
  1262. case 0x0f0: /* GENERAL_PURPOSE17 */
  1263. case 0x0f4: /* GENERAL_PURPOSE18 */
  1264. case 0x0f8: /* GENERAL_PURPOSE19 */
  1265. case 0x0fc: /* GENERAL_PURPOSE20 */
  1266. s->scratch[(addr - 0xb0) >> 2] = value;
  1267. break;
  1268. case 0x140: /* CM_CLKSEL_MPU */
  1269. s->clksel[0] = value & 0x1f;
  1270. /* TODO update clocks */
  1271. break;
  1272. case 0x148: /* CM_CLKSTCTRL_MPU */
  1273. s->clkctrl[0] = value & 0x1f;
  1274. break;
  1275. case 0x158: /* RM_RSTST_MPU */
  1276. s->rst[0] &= ~value;
  1277. break;
  1278. case 0x1c8: /* PM_WKDEP_MPU */
  1279. s->wkup[0] = value & 0x15;
  1280. break;
  1281. case 0x1d4: /* PM_EVGENCTRL_MPU */
  1282. s->ev = value & 0x1f;
  1283. break;
  1284. case 0x1d8: /* PM_EVEGENONTIM_MPU */
  1285. s->evtime[0] = value;
  1286. break;
  1287. case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
  1288. s->evtime[1] = value;
  1289. break;
  1290. case 0x1e0: /* PM_PWSTCTRL_MPU */
  1291. s->power[0] = value & 0xc0f;
  1292. break;
  1293. case 0x200: /* CM_FCLKEN1_CORE */
  1294. s->clken[0] = value & 0xbfffffff;
  1295. /* TODO update clocks */
  1296. /* The EN_EAC bit only gets/puts func_96m_clk. */
  1297. break;
  1298. case 0x204: /* CM_FCLKEN2_CORE */
  1299. s->clken[1] = value & 0x00000007;
  1300. /* TODO update clocks */
  1301. break;
  1302. case 0x210: /* CM_ICLKEN1_CORE */
  1303. s->clken[2] = value & 0xfffffff9;
  1304. /* TODO update clocks */
  1305. /* The EN_EAC bit only gets/puts core_l4_iclk. */
  1306. break;
  1307. case 0x214: /* CM_ICLKEN2_CORE */
  1308. s->clken[3] = value & 0x00000007;
  1309. /* TODO update clocks */
  1310. break;
  1311. case 0x21c: /* CM_ICLKEN4_CORE */
  1312. s->clken[4] = value & 0x0000001f;
  1313. /* TODO update clocks */
  1314. break;
  1315. case 0x230: /* CM_AUTOIDLE1_CORE */
  1316. s->clkidle[0] = value & 0xfffffff9;
  1317. /* TODO update clocks */
  1318. break;
  1319. case 0x234: /* CM_AUTOIDLE2_CORE */
  1320. s->clkidle[1] = value & 0x00000007;
  1321. /* TODO update clocks */
  1322. break;
  1323. case 0x238: /* CM_AUTOIDLE3_CORE */
  1324. s->clkidle[2] = value & 0x00000007;
  1325. /* TODO update clocks */
  1326. break;
  1327. case 0x23c: /* CM_AUTOIDLE4_CORE */
  1328. s->clkidle[3] = value & 0x0000001f;
  1329. /* TODO update clocks */
  1330. break;
  1331. case 0x240: /* CM_CLKSEL1_CORE */
  1332. s->clksel[1] = value & 0x0fffbf7f;
  1333. /* TODO update clocks */
  1334. break;
  1335. case 0x244: /* CM_CLKSEL2_CORE */
  1336. s->clksel[2] = value & 0x00fffffc;
  1337. /* TODO update clocks */
  1338. break;
  1339. case 0x248: /* CM_CLKSTCTRL_CORE */
  1340. s->clkctrl[1] = value & 0x7;
  1341. break;
  1342. case 0x2a0: /* PM_WKEN1_CORE */
  1343. s->wken[0] = value & 0x04667ff8;
  1344. break;
  1345. case 0x2a4: /* PM_WKEN2_CORE */
  1346. s->wken[1] = value & 0x00000005;
  1347. break;
  1348. case 0x2b0: /* PM_WKST1_CORE */
  1349. s->wkst[0] &= ~value;
  1350. break;
  1351. case 0x2b4: /* PM_WKST2_CORE */
  1352. s->wkst[1] &= ~value;
  1353. break;
  1354. case 0x2e0: /* PM_PWSTCTRL_CORE */
  1355. s->power[1] = (value & 0x00fc3f) | (1 << 2);
  1356. break;
  1357. case 0x300: /* CM_FCLKEN_GFX */
  1358. s->clken[5] = value & 6;
  1359. /* TODO update clocks */
  1360. break;
  1361. case 0x310: /* CM_ICLKEN_GFX */
  1362. s->clken[6] = value & 1;
  1363. /* TODO update clocks */
  1364. break;
  1365. case 0x340: /* CM_CLKSEL_GFX */
  1366. s->clksel[3] = value & 7;
  1367. /* TODO update clocks */
  1368. break;
  1369. case 0x348: /* CM_CLKSTCTRL_GFX */
  1370. s->clkctrl[2] = value & 1;
  1371. break;
  1372. case 0x350: /* RM_RSTCTRL_GFX */
  1373. s->rstctrl[0] = value & 1;
  1374. /* TODO: reset */
  1375. break;
  1376. case 0x358: /* RM_RSTST_GFX */
  1377. s->rst[1] &= ~value;
  1378. break;
  1379. case 0x3c8: /* PM_WKDEP_GFX */
  1380. s->wkup[1] = value & 0x13;
  1381. break;
  1382. case 0x3e0: /* PM_PWSTCTRL_GFX */
  1383. s->power[2] = (value & 0x00c0f) | (3 << 2);
  1384. break;
  1385. case 0x400: /* CM_FCLKEN_WKUP */
  1386. s->clken[7] = value & 0xd;
  1387. /* TODO update clocks */
  1388. break;
  1389. case 0x410: /* CM_ICLKEN_WKUP */
  1390. s->clken[8] = value & 0x3f;
  1391. /* TODO update clocks */
  1392. break;
  1393. case 0x430: /* CM_AUTOIDLE_WKUP */
  1394. s->clkidle[4] = value & 0x0000003f;
  1395. /* TODO update clocks */
  1396. break;
  1397. case 0x440: /* CM_CLKSEL_WKUP */
  1398. s->clksel[4] = value & 3;
  1399. /* TODO update clocks */
  1400. break;
  1401. case 0x450: /* RM_RSTCTRL_WKUP */
  1402. /* TODO: reset */
  1403. if (value & 2)
  1404. qemu_system_reset_request();
  1405. break;
  1406. case 0x454: /* RM_RSTTIME_WKUP */
  1407. s->rsttime_wkup = value & 0x1fff;
  1408. break;
  1409. case 0x458: /* RM_RSTST_WKUP */
  1410. s->rst[2] &= ~value;
  1411. break;
  1412. case 0x4a0: /* PM_WKEN_WKUP */
  1413. s->wken[2] = value & 0x00000005;
  1414. break;
  1415. case 0x4b0: /* PM_WKST_WKUP */
  1416. s->wkst[2] &= ~value;
  1417. break;
  1418. case 0x500: /* CM_CLKEN_PLL */
  1419. if (value & 0xffffff30)
  1420. fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
  1421. "future compatiblity\n", __FUNCTION__);
  1422. if ((s->clken[9] ^ value) & 0xcc) {
  1423. s->clken[9] &= ~0xcc;
  1424. s->clken[9] |= value & 0xcc;
  1425. omap_prcm_apll_update(s);
  1426. }
  1427. if ((s->clken[9] ^ value) & 3) {
  1428. s->clken[9] &= ~3;
  1429. s->clken[9] |= value & 3;
  1430. omap_prcm_dpll_update(s);
  1431. }
  1432. break;
  1433. case 0x530: /* CM_AUTOIDLE_PLL */
  1434. s->clkidle[5] = value & 0x000000cf;
  1435. /* TODO update clocks */
  1436. break;
  1437. case 0x540: /* CM_CLKSEL1_PLL */
  1438. if (value & 0xfc4000d7)
  1439. fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
  1440. "future compatiblity\n", __FUNCTION__);
  1441. if ((s->clksel[5] ^ value) & 0x003fff00) {
  1442. s->clksel[5] = value & 0x03bfff28;
  1443. omap_prcm_dpll_update(s);
  1444. }
  1445. /* TODO update the other clocks */
  1446. s->clksel[5] = value & 0x03bfff28;
  1447. break;
  1448. case 0x544: /* CM_CLKSEL2_PLL */
  1449. if (value & ~3)
  1450. fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
  1451. "future compatiblity\n", __FUNCTION__);
  1452. if (s->clksel[6] != (value & 3)) {
  1453. s->clksel[6] = value & 3;
  1454. omap_prcm_dpll_update(s);
  1455. }
  1456. break;
  1457. case 0x800: /* CM_FCLKEN_DSP */
  1458. s->clken[10] = value & 0x501;
  1459. /* TODO update clocks */
  1460. break;
  1461. case 0x810: /* CM_ICLKEN_DSP */
  1462. s->clken[11] = value & 0x2;
  1463. /* TODO update clocks */
  1464. break;
  1465. case 0x830: /* CM_AUTOIDLE_DSP */
  1466. s->clkidle[6] = value & 0x2;
  1467. /* TODO update clocks */
  1468. break;
  1469. case 0x840: /* CM_CLKSEL_DSP */
  1470. s->clksel[7] = value & 0x3fff;
  1471. /* TODO update clocks */
  1472. break;
  1473. case 0x848: /* CM_CLKSTCTRL_DSP */
  1474. s->clkctrl[3] = value & 0x101;
  1475. break;
  1476. case 0x850: /* RM_RSTCTRL_DSP */
  1477. /* TODO: reset */
  1478. break;
  1479. case 0x858: /* RM_RSTST_DSP */
  1480. s->rst[3] &= ~value;
  1481. break;
  1482. case 0x8c8: /* PM_WKDEP_DSP */
  1483. s->wkup[2] = value & 0x13;
  1484. break;
  1485. case 0x8e0: /* PM_PWSTCTRL_DSP */
  1486. s->power[3] = (value & 0x03017) | (3 << 2);
  1487. break;
  1488. case 0x8f0: /* PRCM_IRQSTATUS_DSP */
  1489. s->irqst[1] &= ~value;
  1490. omap_prcm_int_update(s, 1);
  1491. break;
  1492. case 0x8f4: /* PRCM_IRQENABLE_DSP */
  1493. s->irqen[1] = value & 0x7;
  1494. omap_prcm_int_update(s, 1);
  1495. break;
  1496. case 0x8f8: /* PRCM_IRQSTATUS_IVA */
  1497. s->irqst[2] &= ~value;
  1498. omap_prcm_int_update(s, 2);
  1499. break;
  1500. case 0x8fc: /* PRCM_IRQENABLE_IVA */
  1501. s->irqen[2] = value & 0x7;
  1502. omap_prcm_int_update(s, 2);
  1503. break;
  1504. default:
  1505. OMAP_BAD_REG(addr);
  1506. return;
  1507. }
  1508. }
  1509. static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
  1510. omap_badwidth_read32,
  1511. omap_badwidth_read32,
  1512. omap_prcm_read,
  1513. };
  1514. static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
  1515. omap_badwidth_write32,
  1516. omap_badwidth_write32,
  1517. omap_prcm_write,
  1518. };
  1519. static void omap_prcm_reset(struct omap_prcm_s *s)
  1520. {
  1521. s->sysconfig = 0;
  1522. s->irqst[0] = 0;
  1523. s->irqst[1] = 0;
  1524. s->irqst[2] = 0;
  1525. s->irqen[0] = 0;
  1526. s->irqen[1] = 0;
  1527. s->irqen[2] = 0;
  1528. s->voltctrl = 0x1040;
  1529. s->ev = 0x14;
  1530. s->evtime[0] = 0;
  1531. s->evtime[1] = 0;
  1532. s->clkctrl[0] = 0;
  1533. s->clkctrl[1] = 0;
  1534. s->clkctrl[2] = 0;
  1535. s->clkctrl[3] = 0;
  1536. s->clken[1] = 7;
  1537. s->clken[3] = 7;
  1538. s->clken[4] = 0;
  1539. s->clken[5] = 0;
  1540. s->clken[6] = 0;
  1541. s->clken[7] = 0xc;
  1542. s->clken[8] = 0x3e;
  1543. s->clken[9] = 0x0d;
  1544. s->clken[10] = 0;
  1545. s->clken[11] = 0;
  1546. s->clkidle[0] = 0;
  1547. s->clkidle[2] = 7;
  1548. s->clkidle[3] = 0;
  1549. s->clkidle[4] = 0;
  1550. s->clkidle[5] = 0x0c;
  1551. s->clkidle[6] = 0;
  1552. s->clksel[0] = 0x01;
  1553. s->clksel[1] = 0x02100121;
  1554. s->clksel[2] = 0x00000000;
  1555. s->clksel[3] = 0x01;
  1556. s->clksel[4] = 0;
  1557. s->clksel[7] = 0x0121;
  1558. s->wkup[0] = 0x15;
  1559. s->wkup[1] = 0x13;
  1560. s->wkup[2] = 0x13;
  1561. s->wken[0] = 0x04667ff8;
  1562. s->wken[1] = 0x00000005;
  1563. s->wken[2] = 5;
  1564. s->wkst[0] = 0;
  1565. s->wkst[1] = 0;
  1566. s->wkst[2] = 0;
  1567. s->power[0] = 0x00c;
  1568. s->power[1] = 4;
  1569. s->power[2] = 0x0000c;
  1570. s->power[3] = 0x14;
  1571. s->rstctrl[0] = 1;
  1572. s->rst[3] = 1;
  1573. omap_prcm_apll_update(s);
  1574. omap_prcm_dpll_update(s);
  1575. }
  1576. static void omap_prcm_coldreset(struct omap_prcm_s *s)
  1577. {
  1578. s->setuptime[0] = 0;
  1579. s->setuptime[1] = 0;
  1580. memset(&s->scratch, 0, sizeof(s->scratch));
  1581. s->rst[0] = 0x01;
  1582. s->rst[1] = 0x00;
  1583. s->rst[2] = 0x01;
  1584. s->clken[0] = 0;
  1585. s->clken[2] = 0;
  1586. s->clkidle[1] = 0;
  1587. s->clksel[5] = 0;
  1588. s->clksel[6] = 2;
  1589. s->clksrc[0] = 0x43;
  1590. s->clkout[0] = 0x0303;
  1591. s->clkemul[0] = 0;
  1592. s->clkpol[0] = 0x100;
  1593. s->rsttime_wkup = 0x1002;
  1594. omap_prcm_reset(s);
  1595. }
  1596. static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
  1597. qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
  1598. struct omap_mpu_state_s *mpu)
  1599. {
  1600. int iomemtype;
  1601. struct omap_prcm_s *s = (struct omap_prcm_s *)
  1602. qemu_mallocz(sizeof(struct omap_prcm_s));
  1603. s->irq[0] = mpu_int;
  1604. s->irq[1] = dsp_int;
  1605. s->irq[2] = iva_int;
  1606. s->mpu = mpu;
  1607. omap_prcm_coldreset(s);
  1608. iomemtype = l4_register_io_memory(omap_prcm_readfn,
  1609. omap_prcm_writefn, s);
  1610. omap_l4_attach(ta, 0, iomemtype);
  1611. omap_l4_attach(ta, 1, iomemtype);
  1612. return s;
  1613. }
  1614. /* System and Pinout control */
  1615. struct omap_sysctl_s {
  1616. struct omap_mpu_state_s *mpu;
  1617. uint32_t sysconfig;
  1618. uint32_t devconfig;
  1619. uint32_t psaconfig;
  1620. uint32_t padconf[0x45];
  1621. uint8_t obs;
  1622. uint32_t msuspendmux[5];
  1623. };
  1624. static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
  1625. {
  1626. struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
  1627. int pad_offset, byte_offset;
  1628. int value;
  1629. switch (addr) {
  1630. case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
  1631. pad_offset = (addr - 0x30) >> 2;
  1632. byte_offset = (addr - 0x30) & (4 - 1);
  1633. value = s->padconf[pad_offset];
  1634. value = (value >> (byte_offset * 8)) & 0xff;
  1635. return value;
  1636. default:
  1637. break;
  1638. }
  1639. OMAP_BAD_REG(addr);
  1640. return 0;
  1641. }
  1642. static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
  1643. {
  1644. struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
  1645. switch (addr) {
  1646. case 0x000: /* CONTROL_REVISION */
  1647. return 0x20;
  1648. case 0x010: /* CONTROL_SYSCONFIG */
  1649. return s->sysconfig;
  1650. case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
  1651. return s->padconf[(addr - 0x30) >> 2];
  1652. case 0x270: /* CONTROL_DEBOBS */
  1653. return s->obs;
  1654. case 0x274: /* CONTROL_DEVCONF */
  1655. return s->devconfig;
  1656. case 0x28c: /* CONTROL_EMU_SUPPORT */
  1657. return 0;
  1658. case 0x290: /* CONTROL_MSUSPENDMUX_0 */
  1659. return s->msuspendmux[0];
  1660. case 0x294: /* CONTROL_MSUSPENDMUX_1 */
  1661. return s->msuspendmux[1];
  1662. case 0x298: /* CONTROL_MSUSPENDMUX_2 */
  1663. return s->msuspendmux[2];
  1664. case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
  1665. return s->msuspendmux[3];
  1666. case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
  1667. return s->msuspendmux[4];
  1668. case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
  1669. return 0;
  1670. case 0x2b8: /* CONTROL_PSA_CTRL */
  1671. return s->psaconfig;
  1672. case 0x2bc: /* CONTROL_PSA_CMD */
  1673. case 0x2c0: /* CONTROL_PSA_VALUE */
  1674. return 0;
  1675. case 0x2b0: /* CONTROL_SEC_CTRL */
  1676. return 0x800000f1;
  1677. case 0x2d0: /* CONTROL_SEC_EMU */
  1678. return 0x80000015;
  1679. case 0x2d4: /* CONTROL_SEC_TAP */
  1680. return 0x8000007f;
  1681. case 0x2b4: /* CONTROL_SEC_TEST */
  1682. case 0x2f0: /* CONTROL_SEC_STATUS */
  1683. case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
  1684. /* Secure mode is not present on general-pusrpose device. Outside
  1685. * secure mode these values cannot be read or written. */
  1686. return 0;
  1687. case 0x2d8: /* CONTROL_OCM_RAM_PERM */
  1688. return 0xff;
  1689. case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
  1690. case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
  1691. case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
  1692. /* No secure mode so no Extended Secure RAM present. */
  1693. return 0;
  1694. case 0x2f8: /* CONTROL_STATUS */
  1695. /* Device Type => General-purpose */
  1696. return 0x0300;
  1697. case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
  1698. case 0x300: /* CONTROL_RPUB_KEY_H_0 */
  1699. case 0x304: /* CONTROL_RPUB_KEY_H_1 */
  1700. case 0x308: /* CONTROL_RPUB_KEY_H_2 */
  1701. case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
  1702. return 0xdecafbad;
  1703. case 0x310: /* CONTROL_RAND_KEY_0 */
  1704. case 0x314: /* CONTROL_RAND_KEY_1 */
  1705. case 0x318: /* CONTROL_RAND_KEY_2 */
  1706. case 0x31c: /* CONTROL_RAND_KEY_3 */
  1707. case 0x320: /* CONTROL_CUST_KEY_0 */
  1708. case 0x324: /* CONTROL_CUST_KEY_1 */
  1709. case 0x330: /* CONTROL_TEST_KEY_0 */
  1710. case 0x334: /* CONTROL_TEST_KEY_1 */
  1711. case 0x338: /* CONTROL_TEST_KEY_2 */
  1712. case 0x33c: /* CONTROL_TEST_KEY_3 */
  1713. case 0x340: /* CONTROL_TEST_KEY_4 */
  1714. case 0x344: /* CONTROL_TEST_KEY_5 */
  1715. case 0x348: /* CONTROL_TEST_KEY_6 */
  1716. case 0x34c: /* CONTROL_TEST_KEY_7 */
  1717. case 0x350: /* CONTROL_TEST_KEY_8 */
  1718. case 0x354: /* CONTROL_TEST_KEY_9 */
  1719. /* Can only be accessed in secure mode and when C_FieldAccEnable
  1720. * bit is set in CONTROL_SEC_CTRL.
  1721. * TODO: otherwise an interconnect access error is generated. */
  1722. return 0;
  1723. }
  1724. OMAP_BAD_REG(addr);
  1725. return 0;
  1726. }
  1727. static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
  1728. uint32_t value)
  1729. {
  1730. struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
  1731. int pad_offset, byte_offset;
  1732. int prev_value;
  1733. switch (addr) {
  1734. case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
  1735. pad_offset = (addr - 0x30) >> 2;
  1736. byte_offset = (addr - 0x30) & (4 - 1);
  1737. prev_value = s->padconf[pad_offset];
  1738. prev_value &= ~(0xff << (byte_offset * 8));
  1739. prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
  1740. s->padconf[pad_offset] = prev_value;
  1741. break;
  1742. default:
  1743. OMAP_BAD_REG(addr);
  1744. break;
  1745. }
  1746. }
  1747. static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
  1748. uint32_t value)
  1749. {
  1750. struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
  1751. switch (addr) {
  1752. case 0x000: /* CONTROL_REVISION */
  1753. case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
  1754. case 0x2c0: /* CONTROL_PSA_VALUE */
  1755. case 0x2f8: /* CONTROL_STATUS */
  1756. case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
  1757. case 0x300: /* CONTROL_RPUB_KEY_H_0 */
  1758. case 0x304: /* CONTROL_RPUB_KEY_H_1 */
  1759. case 0x308: /* CONTROL_RPUB_KEY_H_2 */
  1760. case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
  1761. case 0x310: /* CONTROL_RAND_KEY_0 */
  1762. case 0x314: /* CONTROL_RAND_KEY_1 */
  1763. case 0x318: /* CONTROL_RAND_KEY_2 */
  1764. case 0x31c: /* CONTROL_RAND_KEY_3 */
  1765. case 0x320: /* CONTROL_CUST_KEY_0 */
  1766. case 0x324: /* CONTROL_CUST_KEY_1 */
  1767. case 0x330: /* CONTROL_TEST_KEY_0 */
  1768. case 0x334: /* CONTROL_TEST_KEY_1 */
  1769. case 0x338: /* CONTROL_TEST_KEY_2 */
  1770. case 0x33c: /* CONTROL_TEST_KEY_3 */
  1771. case 0x340: /* CONTROL_TEST_KEY_4 */
  1772. case 0x344: /* CONTROL_TEST_KEY_5 */
  1773. case 0x348: /* CONTROL_TEST_KEY_6 */
  1774. case 0x34c: /* CONTROL_TEST_KEY_7 */
  1775. case 0x350: /* CONTROL_TEST_KEY_8 */
  1776. case 0x354: /* CONTROL_TEST_KEY_9 */
  1777. OMAP_RO_REG(addr);
  1778. return;
  1779. case 0x010: /* CONTROL_SYSCONFIG */
  1780. s->sysconfig = value & 0x1e;
  1781. break;
  1782. case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
  1783. /* XXX: should check constant bits */
  1784. s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
  1785. break;
  1786. case 0x270: /* CONTROL_DEBOBS */
  1787. s->obs = value & 0xff;
  1788. break;
  1789. case 0x274: /* CONTROL_DEVCONF */
  1790. s->devconfig = value & 0xffffc7ff;
  1791. break;
  1792. case 0x28c: /* CONTROL_EMU_SUPPORT */
  1793. break;
  1794. case 0x290: /* CONTROL_MSUSPENDMUX_0 */
  1795. s->msuspendmux[0] = value & 0x3fffffff;
  1796. break;
  1797. case 0x294: /* CONTROL_MSUSPENDMUX_1 */
  1798. s->msuspendmux[1] = value & 0x3fffffff;
  1799. break;
  1800. case 0x298: /* CONTROL_MSUSPENDMUX_2 */
  1801. s->msuspendmux[2] = value & 0x3fffffff;
  1802. break;
  1803. case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
  1804. s->msuspendmux[3] = value & 0x3fffffff;
  1805. break;
  1806. case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
  1807. s->msuspendmux[4] = value & 0x3fffffff;
  1808. break;
  1809. case 0x2b8: /* CONTROL_PSA_CTRL */
  1810. s->psaconfig = value & 0x1c;
  1811. s->psaconfig |= (value & 0x20) ? 2 : 1;
  1812. break;
  1813. case 0x2bc: /* CONTROL_PSA_CMD */
  1814. break;
  1815. case 0x2b0: /* CONTROL_SEC_CTRL */
  1816. case 0x2b4: /* CONTROL_SEC_TEST */
  1817. case 0x2d0: /* CONTROL_SEC_EMU */
  1818. case 0x2d4: /* CONTROL_SEC_TAP */
  1819. case 0x2d8: /* CONTROL_OCM_RAM_PERM */
  1820. case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
  1821. case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
  1822. case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
  1823. case 0x2f0: /* CONTROL_SEC_STATUS */
  1824. case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
  1825. break;
  1826. default:
  1827. OMAP_BAD_REG(addr);
  1828. return;
  1829. }
  1830. }
  1831. static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
  1832. omap_sysctl_read8,
  1833. omap_badwidth_read32, /* TODO */
  1834. omap_sysctl_read,
  1835. };
  1836. static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
  1837. omap_sysctl_write8,
  1838. omap_badwidth_write32, /* TODO */
  1839. omap_sysctl_write,
  1840. };
  1841. static void omap_sysctl_reset(struct omap_sysctl_s *s)
  1842. {
  1843. /* (power-on reset) */
  1844. s->sysconfig = 0;
  1845. s->obs = 0;
  1846. s->devconfig = 0x0c000000;
  1847. s->msuspendmux[0] = 0x00000000;
  1848. s->msuspendmux[1] = 0x00000000;
  1849. s->msuspendmux[2] = 0x00000000;
  1850. s->msuspendmux[3] = 0x00000000;
  1851. s->msuspendmux[4] = 0x00000000;
  1852. s->psaconfig = 1;
  1853. s->padconf[0x00] = 0x000f0f0f;
  1854. s->padconf[0x01] = 0x00000000;
  1855. s->padconf[0x02] = 0x00000000;
  1856. s->padconf[0x03] = 0x00000000;
  1857. s->padconf[0x04] = 0x00000000;
  1858. s->padconf[0x05] = 0x00000000;
  1859. s->padconf[0x06] = 0x00000000;
  1860. s->padconf[0x07] = 0x00000000;
  1861. s->padconf[0x08] = 0x08080800;
  1862. s->padconf[0x09] = 0x08080808;
  1863. s->padconf[0x0a] = 0x08080808;
  1864. s->padconf[0x0b] = 0x08080808;
  1865. s->padconf[0x0c] = 0x08080808;
  1866. s->padconf[0x0d] = 0x08080800;
  1867. s->padconf[0x0e] = 0x08080808;
  1868. s->padconf[0x0f] = 0x08080808;
  1869. s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
  1870. s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
  1871. s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
  1872. s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
  1873. s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
  1874. s->padconf[0x15] = 0x18181818;
  1875. s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
  1876. s->padconf[0x17] = 0x1f001f00;
  1877. s->padconf[0x18] = 0x1f1f1f1f;
  1878. s->padconf[0x19] = 0x00000000;
  1879. s->padconf[0x1a] = 0x1f180000;
  1880. s->padconf[0x1b] = 0x00001f1f;
  1881. s->padconf[0x1c] = 0x1f001f00;
  1882. s->padconf[0x1d] = 0x00000000;
  1883. s->padconf[0x1e] = 0x00000000;
  1884. s->padconf[0x1f] = 0x08000000;
  1885. s->padconf[0x20] = 0x08080808;
  1886. s->padconf[0x21] = 0x08080808;
  1887. s->padconf[0x22] = 0x0f080808;
  1888. s->padconf[0x23] = 0x0f0f0f0f;
  1889. s->padconf[0x24] = 0x000f0f0f;
  1890. s->padconf[0x25] = 0x1f1f1f0f;
  1891. s->padconf[0x26] = 0x080f0f1f;
  1892. s->padconf[0x27] = 0x070f1808;
  1893. s->padconf[0x28] = 0x0f070707;
  1894. s->padconf[0x29] = 0x000f0f1f;
  1895. s->padconf[0x2a] = 0x0f0f0f1f;
  1896. s->padconf[0x2b] = 0x08000000;
  1897. s->padconf[0x2c] = 0x0000001f;
  1898. s->padconf[0x2d] = 0x0f0f1f00;
  1899. s->padconf[0x2e] = 0x1f1f0f0f;
  1900. s->padconf[0x2f] = 0x0f1f1f1f;
  1901. s->padconf[0x30] = 0x0f0f0f0f;
  1902. s->padconf[0x31] = 0x0f1f0f1f;
  1903. s->padconf[0x32] = 0x0f0f0f0f;
  1904. s->padconf[0x33] = 0x0f1f0f1f;
  1905. s->padconf[0x34] = 0x1f1f0f0f;
  1906. s->padconf[0x35] = 0x0f0f1f1f;
  1907. s->padconf[0x36] = 0x0f0f1f0f;
  1908. s->padconf[0x37] = 0x0f0f0f0f;
  1909. s->padconf[0x38] = 0x1f18180f;
  1910. s->padconf[0x39] = 0x1f1f1f1f;
  1911. s->padconf[0x3a] = 0x00001f1f;
  1912. s->padconf[0x3b] = 0x00000000;
  1913. s->padconf[0x3c] = 0x00000000;
  1914. s->padconf[0x3d] = 0x0f0f0f0f;
  1915. s->padconf[0x3e] = 0x18000f0f;
  1916. s->padconf[0x3f] = 0x00070000;
  1917. s->padconf[0x40] = 0x00000707;
  1918. s->padconf[0x41] = 0x0f1f0700;
  1919. s->padconf[0x42] = 0x1f1f070f;
  1920. s->padconf[0x43] = 0x0008081f;
  1921. s->padconf[0x44] = 0x00000800;
  1922. }
  1923. static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
  1924. omap_clk iclk, struct omap_mpu_state_s *mpu)
  1925. {
  1926. int iomemtype;
  1927. struct omap_sysctl_s *s = (struct omap_sysctl_s *)
  1928. qemu_mallocz(sizeof(struct omap_sysctl_s));
  1929. s->mpu = mpu;
  1930. omap_sysctl_reset(s);
  1931. iomemtype = l4_register_io_memory(omap_sysctl_readfn,
  1932. omap_sysctl_writefn, s);
  1933. omap_l4_attach(ta, 0, iomemtype);
  1934. return s;
  1935. }
  1936. /* General chip reset */
  1937. static void omap2_mpu_reset(void *opaque)
  1938. {
  1939. struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
  1940. omap_inth_reset(mpu->ih[0]);
  1941. omap_dma_reset(mpu->dma);
  1942. omap_prcm_reset(mpu->prcm);
  1943. omap_sysctl_reset(mpu->sysc);
  1944. omap_gp_timer_reset(mpu->gptimer[0]);
  1945. omap_gp_timer_reset(mpu->gptimer[1]);
  1946. omap_gp_timer_reset(mpu->gptimer[2]);
  1947. omap_gp_timer_reset(mpu->gptimer[3]);
  1948. omap_gp_timer_reset(mpu->gptimer[4]);
  1949. omap_gp_timer_reset(mpu->gptimer[5]);
  1950. omap_gp_timer_reset(mpu->gptimer[6]);
  1951. omap_gp_timer_reset(mpu->gptimer[7]);
  1952. omap_gp_timer_reset(mpu->gptimer[8]);
  1953. omap_gp_timer_reset(mpu->gptimer[9]);
  1954. omap_gp_timer_reset(mpu->gptimer[10]);
  1955. omap_gp_timer_reset(mpu->gptimer[11]);
  1956. omap_synctimer_reset(mpu->synctimer);
  1957. omap_sdrc_reset(mpu->sdrc);
  1958. omap_gpmc_reset(mpu->gpmc);
  1959. omap_dss_reset(mpu->dss);
  1960. omap_uart_reset(mpu->uart[0]);
  1961. omap_uart_reset(mpu->uart[1]);
  1962. omap_uart_reset(mpu->uart[2]);
  1963. omap_mmc_reset(mpu->mmc);
  1964. omap_gpif_reset(mpu->gpif);
  1965. omap_mcspi_reset(mpu->mcspi[0]);
  1966. omap_mcspi_reset(mpu->mcspi[1]);
  1967. omap_i2c_reset(mpu->i2c[0]);
  1968. omap_i2c_reset(mpu->i2c[1]);
  1969. cpu_reset(mpu->env);
  1970. }
  1971. static int omap2_validate_addr(struct omap_mpu_state_s *s,
  1972. target_phys_addr_t addr)
  1973. {
  1974. return 1;
  1975. }
  1976. static const struct dma_irq_map omap2_dma_irq_map[] = {
  1977. { 0, OMAP_INT_24XX_SDMA_IRQ0 },
  1978. { 0, OMAP_INT_24XX_SDMA_IRQ1 },
  1979. { 0, OMAP_INT_24XX_SDMA_IRQ2 },
  1980. { 0, OMAP_INT_24XX_SDMA_IRQ3 },
  1981. };
  1982. struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
  1983. const char *core)
  1984. {
  1985. struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
  1986. qemu_mallocz(sizeof(struct omap_mpu_state_s));
  1987. ram_addr_t sram_base, q2_base;
  1988. qemu_irq *cpu_irq;
  1989. qemu_irq dma_irqs[4];
  1990. omap_clk gpio_clks[4];
  1991. DriveInfo *dinfo;
  1992. int i;
  1993. /* Core */
  1994. s->mpu_model = omap2420;
  1995. s->env = cpu_init(core ?: "arm1136-r2");
  1996. if (!s->env) {
  1997. fprintf(stderr, "Unable to find CPU definition\n");
  1998. exit(1);
  1999. }
  2000. s->sdram_size = sdram_size;
  2001. s->sram_size = OMAP242X_SRAM_SIZE;
  2002. s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
  2003. /* Clocks */
  2004. omap_clk_init(s);
  2005. /* Memory-mapped stuff */
  2006. cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
  2007. (q2_base = qemu_ram_alloc(NULL, "omap2.dram",
  2008. s->sdram_size)) | IO_MEM_RAM);
  2009. cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
  2010. (sram_base = qemu_ram_alloc(NULL, "omap2.sram",
  2011. s->sram_size)) | IO_MEM_RAM);
  2012. s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
  2013. /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
  2014. cpu_irq = arm_pic_init_cpu(s->env);
  2015. s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
  2016. cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
  2017. omap_findclk(s, "mpu_intc_fclk"),
  2018. omap_findclk(s, "mpu_intc_iclk"));
  2019. s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
  2020. s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
  2021. s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
  2022. omap_findclk(s, "omapctrl_iclk"), s);
  2023. for (i = 0; i < 4; i ++)
  2024. dma_irqs[i] =
  2025. s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
  2026. s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
  2027. omap_findclk(s, "sdma_iclk"),
  2028. omap_findclk(s, "sdma_fclk"));
  2029. s->port->addr_valid = omap2_validate_addr;
  2030. /* Register SDRAM and SRAM ports for fast DMA transfers. */
  2031. soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
  2032. soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
  2033. s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
  2034. s->irq[0][OMAP_INT_24XX_UART1_IRQ],
  2035. omap_findclk(s, "uart1_fclk"),
  2036. omap_findclk(s, "uart1_iclk"),
  2037. s->drq[OMAP24XX_DMA_UART1_TX],
  2038. s->drq[OMAP24XX_DMA_UART1_RX],
  2039. "uart1",
  2040. serial_hds[0]);
  2041. s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
  2042. s->irq[0][OMAP_INT_24XX_UART2_IRQ],
  2043. omap_findclk(s, "uart2_fclk"),
  2044. omap_findclk(s, "uart2_iclk"),
  2045. s->drq[OMAP24XX_DMA_UART2_TX],
  2046. s->drq[OMAP24XX_DMA_UART2_RX],
  2047. "uart2",
  2048. serial_hds[0] ? serial_hds[1] : NULL);
  2049. s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
  2050. s->irq[0][OMAP_INT_24XX_UART3_IRQ],
  2051. omap_findclk(s, "uart3_fclk"),
  2052. omap_findclk(s, "uart3_iclk"),
  2053. s->drq[OMAP24XX_DMA_UART3_TX],
  2054. s->drq[OMAP24XX_DMA_UART3_RX],
  2055. "uart3",
  2056. serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
  2057. s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
  2058. s->irq[0][OMAP_INT_24XX_GPTIMER1],
  2059. omap_findclk(s, "wu_gpt1_clk"),
  2060. omap_findclk(s, "wu_l4_iclk"));
  2061. s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
  2062. s->irq[0][OMAP_INT_24XX_GPTIMER2],
  2063. omap_findclk(s, "core_gpt2_clk"),
  2064. omap_findclk(s, "core_l4_iclk"));
  2065. s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
  2066. s->irq[0][OMAP_INT_24XX_GPTIMER3],
  2067. omap_findclk(s, "core_gpt3_clk"),
  2068. omap_findclk(s, "core_l4_iclk"));
  2069. s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
  2070. s->irq[0][OMAP_INT_24XX_GPTIMER4],
  2071. omap_findclk(s, "core_gpt4_clk"),
  2072. omap_findclk(s, "core_l4_iclk"));
  2073. s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
  2074. s->irq[0][OMAP_INT_24XX_GPTIMER5],
  2075. omap_findclk(s, "core_gpt5_clk"),
  2076. omap_findclk(s, "core_l4_iclk"));
  2077. s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
  2078. s->irq[0][OMAP_INT_24XX_GPTIMER6],
  2079. omap_findclk(s, "core_gpt6_clk"),
  2080. omap_findclk(s, "core_l4_iclk"));
  2081. s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
  2082. s->irq[0][OMAP_INT_24XX_GPTIMER7],
  2083. omap_findclk(s, "core_gpt7_clk"),
  2084. omap_findclk(s, "core_l4_iclk"));
  2085. s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
  2086. s->irq[0][OMAP_INT_24XX_GPTIMER8],
  2087. omap_findclk(s, "core_gpt8_clk"),
  2088. omap_findclk(s, "core_l4_iclk"));
  2089. s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
  2090. s->irq[0][OMAP_INT_24XX_GPTIMER9],
  2091. omap_findclk(s, "core_gpt9_clk"),
  2092. omap_findclk(s, "core_l4_iclk"));
  2093. s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
  2094. s->irq[0][OMAP_INT_24XX_GPTIMER10],
  2095. omap_findclk(s, "core_gpt10_clk"),
  2096. omap_findclk(s, "core_l4_iclk"));
  2097. s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
  2098. s->irq[0][OMAP_INT_24XX_GPTIMER11],
  2099. omap_findclk(s, "core_gpt11_clk"),
  2100. omap_findclk(s, "core_l4_iclk"));
  2101. s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
  2102. s->irq[0][OMAP_INT_24XX_GPTIMER12],
  2103. omap_findclk(s, "core_gpt12_clk"),
  2104. omap_findclk(s, "core_l4_iclk"));
  2105. omap_tap_init(omap_l4ta(s->l4, 2), s);
  2106. s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
  2107. omap_findclk(s, "clk32-kHz"),
  2108. omap_findclk(s, "core_l4_iclk"));
  2109. s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
  2110. s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
  2111. &s->drq[OMAP24XX_DMA_I2C1_TX],
  2112. omap_findclk(s, "i2c1.fclk"),
  2113. omap_findclk(s, "i2c1.iclk"));
  2114. s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
  2115. s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
  2116. &s->drq[OMAP24XX_DMA_I2C2_TX],
  2117. omap_findclk(s, "i2c2.fclk"),
  2118. omap_findclk(s, "i2c2.iclk"));
  2119. gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
  2120. gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
  2121. gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
  2122. gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
  2123. s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
  2124. &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
  2125. gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
  2126. s->sdrc = omap_sdrc_init(0x68009000);
  2127. s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
  2128. dinfo = drive_get(IF_SD, 0, 0);
  2129. if (!dinfo) {
  2130. fprintf(stderr, "qemu: missing SecureDigital device\n");
  2131. exit(1);
  2132. }
  2133. s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
  2134. s->irq[0][OMAP_INT_24XX_MMC_IRQ],
  2135. &s->drq[OMAP24XX_DMA_MMC1_TX],
  2136. omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
  2137. s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
  2138. s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
  2139. &s->drq[OMAP24XX_DMA_SPI1_TX0],
  2140. omap_findclk(s, "spi1_fclk"),
  2141. omap_findclk(s, "spi1_iclk"));
  2142. s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
  2143. s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
  2144. &s->drq[OMAP24XX_DMA_SPI2_TX0],
  2145. omap_findclk(s, "spi2_fclk"),
  2146. omap_findclk(s, "spi2_iclk"));
  2147. s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
  2148. /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
  2149. s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
  2150. omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
  2151. omap_findclk(s, "dss_54m_clk"),
  2152. omap_findclk(s, "dss_l3_iclk"),
  2153. omap_findclk(s, "dss_l4_iclk"));
  2154. omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
  2155. s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
  2156. serial_hds[0] && serial_hds[1] && serial_hds[2] ?
  2157. serial_hds[3] : NULL);
  2158. s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
  2159. s->irq[0][OMAP_INT_24XX_EAC_IRQ],
  2160. /* Ten consecutive lines */
  2161. &s->drq[OMAP24XX_DMA_EAC_AC_RD],
  2162. omap_findclk(s, "func_96m_clk"),
  2163. omap_findclk(s, "core_l4_iclk"));
  2164. /* All register mappings (includin those not currenlty implemented):
  2165. * SystemControlMod 48000000 - 48000fff
  2166. * SystemControlL4 48001000 - 48001fff
  2167. * 32kHz Timer Mod 48004000 - 48004fff
  2168. * 32kHz Timer L4 48005000 - 48005fff
  2169. * PRCM ModA 48008000 - 480087ff
  2170. * PRCM ModB 48008800 - 48008fff
  2171. * PRCM L4 48009000 - 48009fff
  2172. * TEST-BCM Mod 48012000 - 48012fff
  2173. * TEST-BCM L4 48013000 - 48013fff
  2174. * TEST-TAP Mod 48014000 - 48014fff
  2175. * TEST-TAP L4 48015000 - 48015fff
  2176. * GPIO1 Mod 48018000 - 48018fff
  2177. * GPIO Top 48019000 - 48019fff
  2178. * GPIO2 Mod 4801a000 - 4801afff
  2179. * GPIO L4 4801b000 - 4801bfff
  2180. * GPIO3 Mod 4801c000 - 4801cfff
  2181. * GPIO4 Mod 4801e000 - 4801efff
  2182. * WDTIMER1 Mod 48020000 - 48010fff
  2183. * WDTIMER Top 48021000 - 48011fff
  2184. * WDTIMER2 Mod 48022000 - 48012fff
  2185. * WDTIMER L4 48023000 - 48013fff
  2186. * WDTIMER3 Mod 48024000 - 48014fff
  2187. * WDTIMER3 L4 48025000 - 48015fff
  2188. * WDTIMER4 Mod 48026000 - 48016fff
  2189. * WDTIMER4 L4 48027000 - 48017fff
  2190. * GPTIMER1 Mod 48028000 - 48018fff
  2191. * GPTIMER1 L4 48029000 - 48019fff
  2192. * GPTIMER2 Mod 4802a000 - 4801afff
  2193. * GPTIMER2 L4 4802b000 - 4801bfff
  2194. * L4-Config AP 48040000 - 480407ff
  2195. * L4-Config IP 48040800 - 48040fff
  2196. * L4-Config LA 48041000 - 48041fff
  2197. * ARM11ETB Mod 48048000 - 48049fff
  2198. * ARM11ETB L4 4804a000 - 4804afff
  2199. * DISPLAY Top 48050000 - 480503ff
  2200. * DISPLAY DISPC 48050400 - 480507ff
  2201. * DISPLAY RFBI 48050800 - 48050bff
  2202. * DISPLAY VENC 48050c00 - 48050fff
  2203. * DISPLAY L4 48051000 - 48051fff
  2204. * CAMERA Top 48052000 - 480523ff
  2205. * CAMERA core 48052400 - 480527ff
  2206. * CAMERA DMA 48052800 - 48052bff
  2207. * CAMERA MMU 48052c00 - 48052fff
  2208. * CAMERA L4 48053000 - 48053fff
  2209. * SDMA Mod 48056000 - 48056fff
  2210. * SDMA L4 48057000 - 48057fff
  2211. * SSI Top 48058000 - 48058fff
  2212. * SSI GDD 48059000 - 48059fff
  2213. * SSI Port1 4805a000 - 4805afff
  2214. * SSI Port2 4805b000 - 4805bfff
  2215. * SSI L4 4805c000 - 4805cfff
  2216. * USB Mod 4805e000 - 480fefff
  2217. * USB L4 4805f000 - 480fffff
  2218. * WIN_TRACER1 Mod 48060000 - 48060fff
  2219. * WIN_TRACER1 L4 48061000 - 48061fff
  2220. * WIN_TRACER2 Mod 48062000 - 48062fff
  2221. * WIN_TRACER2 L4 48063000 - 48063fff
  2222. * WIN_TRACER3 Mod 48064000 - 48064fff
  2223. * WIN_TRACER3 L4 48065000 - 48065fff
  2224. * WIN_TRACER4 Top 48066000 - 480660ff
  2225. * WIN_TRACER4 ETT 48066100 - 480661ff
  2226. * WIN_TRACER4 WT 48066200 - 480662ff
  2227. * WIN_TRACER4 L4 48067000 - 48067fff
  2228. * XTI Mod 48068000 - 48068fff
  2229. * XTI L4 48069000 - 48069fff
  2230. * UART1 Mod 4806a000 - 4806afff
  2231. * UART1 L4 4806b000 - 4806bfff
  2232. * UART2 Mod 4806c000 - 4806cfff
  2233. * UART2 L4 4806d000 - 4806dfff
  2234. * UART3 Mod 4806e000 - 4806efff
  2235. * UART3 L4 4806f000 - 4806ffff
  2236. * I2C1 Mod 48070000 - 48070fff
  2237. * I2C1 L4 48071000 - 48071fff
  2238. * I2C2 Mod 48072000 - 48072fff
  2239. * I2C2 L4 48073000 - 48073fff
  2240. * McBSP1 Mod 48074000 - 48074fff
  2241. * McBSP1 L4 48075000 - 48075fff
  2242. * McBSP2 Mod 48076000 - 48076fff
  2243. * McBSP2 L4 48077000 - 48077fff
  2244. * GPTIMER3 Mod 48078000 - 48078fff
  2245. * GPTIMER3 L4 48079000 - 48079fff
  2246. * GPTIMER4 Mod 4807a000 - 4807afff
  2247. * GPTIMER4 L4 4807b000 - 4807bfff
  2248. * GPTIMER5 Mod 4807c000 - 4807cfff
  2249. * GPTIMER5 L4 4807d000 - 4807dfff
  2250. * GPTIMER6 Mod 4807e000 - 4807efff
  2251. * GPTIMER6 L4 4807f000 - 4807ffff
  2252. * GPTIMER7 Mod 48080000 - 48080fff
  2253. * GPTIMER7 L4 48081000 - 48081fff
  2254. * GPTIMER8 Mod 48082000 - 48082fff
  2255. * GPTIMER8 L4 48083000 - 48083fff
  2256. * GPTIMER9 Mod 48084000 - 48084fff
  2257. * GPTIMER9 L4 48085000 - 48085fff
  2258. * GPTIMER10 Mod 48086000 - 48086fff
  2259. * GPTIMER10 L4 48087000 - 48087fff
  2260. * GPTIMER11 Mod 48088000 - 48088fff
  2261. * GPTIMER11 L4 48089000 - 48089fff
  2262. * GPTIMER12 Mod 4808a000 - 4808afff
  2263. * GPTIMER12 L4 4808b000 - 4808bfff
  2264. * EAC Mod 48090000 - 48090fff
  2265. * EAC L4 48091000 - 48091fff
  2266. * FAC Mod 48092000 - 48092fff
  2267. * FAC L4 48093000 - 48093fff
  2268. * MAILBOX Mod 48094000 - 48094fff
  2269. * MAILBOX L4 48095000 - 48095fff
  2270. * SPI1 Mod 48098000 - 48098fff
  2271. * SPI1 L4 48099000 - 48099fff
  2272. * SPI2 Mod 4809a000 - 4809afff
  2273. * SPI2 L4 4809b000 - 4809bfff
  2274. * MMC/SDIO Mod 4809c000 - 4809cfff
  2275. * MMC/SDIO L4 4809d000 - 4809dfff
  2276. * MS_PRO Mod 4809e000 - 4809efff
  2277. * MS_PRO L4 4809f000 - 4809ffff
  2278. * RNG Mod 480a0000 - 480a0fff
  2279. * RNG L4 480a1000 - 480a1fff
  2280. * DES3DES Mod 480a2000 - 480a2fff
  2281. * DES3DES L4 480a3000 - 480a3fff
  2282. * SHA1MD5 Mod 480a4000 - 480a4fff
  2283. * SHA1MD5 L4 480a5000 - 480a5fff
  2284. * AES Mod 480a6000 - 480a6fff
  2285. * AES L4 480a7000 - 480a7fff
  2286. * PKA Mod 480a8000 - 480a9fff
  2287. * PKA L4 480aa000 - 480aafff
  2288. * MG Mod 480b0000 - 480b0fff
  2289. * MG L4 480b1000 - 480b1fff
  2290. * HDQ/1-wire Mod 480b2000 - 480b2fff
  2291. * HDQ/1-wire L4 480b3000 - 480b3fff
  2292. * MPU interrupt 480fe000 - 480fefff
  2293. * STI channel base 54000000 - 5400ffff
  2294. * IVA RAM 5c000000 - 5c01ffff
  2295. * IVA ROM 5c020000 - 5c027fff
  2296. * IMG_BUF_A 5c040000 - 5c040fff
  2297. * IMG_BUF_B 5c042000 - 5c042fff
  2298. * VLCDS 5c048000 - 5c0487ff
  2299. * IMX_COEF 5c049000 - 5c04afff
  2300. * IMX_CMD 5c051000 - 5c051fff
  2301. * VLCDQ 5c053000 - 5c0533ff
  2302. * VLCDH 5c054000 - 5c054fff
  2303. * SEQ_CMD 5c055000 - 5c055fff
  2304. * IMX_REG 5c056000 - 5c0560ff
  2305. * VLCD_REG 5c056100 - 5c0561ff
  2306. * SEQ_REG 5c056200 - 5c0562ff
  2307. * IMG_BUF_REG 5c056300 - 5c0563ff
  2308. * SEQIRQ_REG 5c056400 - 5c0564ff
  2309. * OCP_REG 5c060000 - 5c060fff
  2310. * SYSC_REG 5c070000 - 5c070fff
  2311. * MMU_REG 5d000000 - 5d000fff
  2312. * sDMA R 68000400 - 680005ff
  2313. * sDMA W 68000600 - 680007ff
  2314. * Display Control 68000800 - 680009ff
  2315. * DSP subsystem 68000a00 - 68000bff
  2316. * MPU subsystem 68000c00 - 68000dff
  2317. * IVA subsystem 68001000 - 680011ff
  2318. * USB 68001200 - 680013ff
  2319. * Camera 68001400 - 680015ff
  2320. * VLYNQ (firewall) 68001800 - 68001bff
  2321. * VLYNQ 68001e00 - 68001fff
  2322. * SSI 68002000 - 680021ff
  2323. * L4 68002400 - 680025ff
  2324. * DSP (firewall) 68002800 - 68002bff
  2325. * DSP subsystem 68002e00 - 68002fff
  2326. * IVA (firewall) 68003000 - 680033ff
  2327. * IVA 68003600 - 680037ff
  2328. * GFX 68003a00 - 68003bff
  2329. * CMDWR emulation 68003c00 - 68003dff
  2330. * SMS 68004000 - 680041ff
  2331. * OCM 68004200 - 680043ff
  2332. * GPMC 68004400 - 680045ff
  2333. * RAM (firewall) 68005000 - 680053ff
  2334. * RAM (err login) 68005400 - 680057ff
  2335. * ROM (firewall) 68005800 - 68005bff
  2336. * ROM (err login) 68005c00 - 68005fff
  2337. * GPMC (firewall) 68006000 - 680063ff
  2338. * GPMC (err login) 68006400 - 680067ff
  2339. * SMS (err login) 68006c00 - 68006fff
  2340. * SMS registers 68008000 - 68008fff
  2341. * SDRC registers 68009000 - 68009fff
  2342. * GPMC registers 6800a000 6800afff
  2343. */
  2344. qemu_register_reset(omap2_mpu_reset, s);
  2345. return s;
  2346. }