lance.c 4.6 KB

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  1. /*
  2. * QEMU AMD PC-Net II (Am79C970A) emulation
  3. *
  4. * Copyright (c) 2004 Antony T Curtis
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. /* This software was written to be compatible with the specification:
  25. * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  26. * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
  27. */
  28. /*
  29. * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
  30. * produced as NCR89C100. See
  31. * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  32. * and
  33. * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
  34. */
  35. #include "sysbus.h"
  36. #include "net.h"
  37. #include "qemu-timer.h"
  38. #include "qemu_socket.h"
  39. #include "sun4m.h"
  40. #include "pcnet.h"
  41. #include "trace.h"
  42. typedef struct {
  43. SysBusDevice busdev;
  44. PCNetState state;
  45. } SysBusPCNetState;
  46. static void parent_lance_reset(void *opaque, int irq, int level)
  47. {
  48. SysBusPCNetState *d = opaque;
  49. if (level)
  50. pcnet_h_reset(&d->state);
  51. }
  52. static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
  53. uint32_t val)
  54. {
  55. SysBusPCNetState *d = opaque;
  56. trace_lance_mem_writew(addr, val & 0xffff);
  57. pcnet_ioport_writew(&d->state, addr, val & 0xffff);
  58. }
  59. static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
  60. {
  61. SysBusPCNetState *d = opaque;
  62. uint32_t val;
  63. val = pcnet_ioport_readw(&d->state, addr);
  64. trace_lance_mem_readw(addr, val & 0xffff);
  65. return val & 0xffff;
  66. }
  67. static CPUReadMemoryFunc * const lance_mem_read[3] = {
  68. NULL,
  69. lance_mem_readw,
  70. NULL,
  71. };
  72. static CPUWriteMemoryFunc * const lance_mem_write[3] = {
  73. NULL,
  74. lance_mem_writew,
  75. NULL,
  76. };
  77. static void lance_cleanup(VLANClientState *nc)
  78. {
  79. PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
  80. pcnet_common_cleanup(d);
  81. }
  82. static NetClientInfo net_lance_info = {
  83. .type = NET_CLIENT_TYPE_NIC,
  84. .size = sizeof(NICState),
  85. .can_receive = pcnet_can_receive,
  86. .receive = pcnet_receive,
  87. .cleanup = lance_cleanup,
  88. };
  89. static const VMStateDescription vmstate_lance = {
  90. .name = "pcnet",
  91. .version_id = 3,
  92. .minimum_version_id = 2,
  93. .minimum_version_id_old = 2,
  94. .fields = (VMStateField []) {
  95. VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
  96. VMSTATE_END_OF_LIST()
  97. }
  98. };
  99. static int lance_init(SysBusDevice *dev)
  100. {
  101. SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
  102. PCNetState *s = &d->state;
  103. s->mmio_index =
  104. cpu_register_io_memory(lance_mem_read, lance_mem_write, d,
  105. DEVICE_NATIVE_ENDIAN);
  106. qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
  107. sysbus_init_mmio(dev, 4, s->mmio_index);
  108. sysbus_init_irq(dev, &s->irq);
  109. s->phys_mem_read = ledma_memory_read;
  110. s->phys_mem_write = ledma_memory_write;
  111. return pcnet_common_init(&dev->qdev, s, &net_lance_info);
  112. }
  113. static void lance_reset(DeviceState *dev)
  114. {
  115. SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev);
  116. pcnet_h_reset(&d->state);
  117. }
  118. static SysBusDeviceInfo lance_info = {
  119. .init = lance_init,
  120. .qdev.name = "lance",
  121. .qdev.fw_name = "ethernet",
  122. .qdev.size = sizeof(SysBusPCNetState),
  123. .qdev.reset = lance_reset,
  124. .qdev.vmsd = &vmstate_lance,
  125. .qdev.props = (Property[]) {
  126. DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
  127. DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
  128. DEFINE_PROP_END_OF_LIST(),
  129. }
  130. };
  131. static void lance_register_devices(void)
  132. {
  133. sysbus_register_withprop(&lance_info);
  134. }
  135. device_init(lance_register_devices)