spitz.c 30 KB

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  1. /*
  2. * PXA270-based Clamshell PDA platforms.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Written by Andrzej Zaborowski <balrog@zabor.org>
  6. *
  7. * This code is licensed under the GNU GPL v2.
  8. */
  9. #include "hw.h"
  10. #include "pxa.h"
  11. #include "arm-misc.h"
  12. #include "sysemu.h"
  13. #include "pcmcia.h"
  14. #include "i2c.h"
  15. #include "flash.h"
  16. #include "qemu-timer.h"
  17. #include "devices.h"
  18. #include "sharpsl.h"
  19. #include "console.h"
  20. #include "block.h"
  21. #include "audio/audio.h"
  22. #include "boards.h"
  23. #undef REG_FMT
  24. #if TARGET_PHYS_ADDR_BITS == 32
  25. #define REG_FMT "0x%02x"
  26. #else
  27. #define REG_FMT "0x%02lx"
  28. #endif
  29. /* Spitz Flash */
  30. #define FLASH_BASE 0x0c000000
  31. #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
  32. #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
  33. #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
  34. #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
  35. #define FLASH_ECCCLRR 0x10 /* Clear ECC */
  36. #define FLASH_FLASHIO 0x14 /* Flash I/O */
  37. #define FLASH_FLASHCTL 0x18 /* Flash Control */
  38. #define FLASHCTL_CE0 (1 << 0)
  39. #define FLASHCTL_CLE (1 << 1)
  40. #define FLASHCTL_ALE (1 << 2)
  41. #define FLASHCTL_WP (1 << 3)
  42. #define FLASHCTL_CE1 (1 << 4)
  43. #define FLASHCTL_RYBY (1 << 5)
  44. #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
  45. struct sl_nand_s {
  46. struct nand_flash_s *nand;
  47. uint8_t ctl;
  48. struct ecc_state_s ecc;
  49. };
  50. static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
  51. {
  52. struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  53. int ryby;
  54. switch (addr) {
  55. #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  56. case FLASH_ECCLPLB:
  57. return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  58. BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  59. #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  60. case FLASH_ECCLPUB:
  61. return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  62. BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  63. case FLASH_ECCCP:
  64. return s->ecc.cp;
  65. case FLASH_ECCCNTR:
  66. return s->ecc.count & 0xff;
  67. case FLASH_FLASHCTL:
  68. nand_getpins(s->nand, &ryby);
  69. if (ryby)
  70. return s->ctl | FLASHCTL_RYBY;
  71. else
  72. return s->ctl;
  73. case FLASH_FLASHIO:
  74. return ecc_digest(&s->ecc, nand_getio(s->nand));
  75. default:
  76. zaurus_printf("Bad register offset " REG_FMT "\n", addr);
  77. }
  78. return 0;
  79. }
  80. static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
  81. {
  82. struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  83. if (addr == FLASH_FLASHIO)
  84. return ecc_digest(&s->ecc, nand_getio(s->nand)) |
  85. (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
  86. return sl_readb(opaque, addr);
  87. }
  88. static void sl_writeb(void *opaque, target_phys_addr_t addr,
  89. uint32_t value)
  90. {
  91. struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  92. switch (addr) {
  93. case FLASH_ECCCLRR:
  94. /* Value is ignored. */
  95. ecc_reset(&s->ecc);
  96. break;
  97. case FLASH_FLASHCTL:
  98. s->ctl = value & 0xff & ~FLASHCTL_RYBY;
  99. nand_setpins(s->nand,
  100. s->ctl & FLASHCTL_CLE,
  101. s->ctl & FLASHCTL_ALE,
  102. s->ctl & FLASHCTL_NCE,
  103. s->ctl & FLASHCTL_WP,
  104. 0);
  105. break;
  106. case FLASH_FLASHIO:
  107. nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
  108. break;
  109. default:
  110. zaurus_printf("Bad register offset " REG_FMT "\n", addr);
  111. }
  112. }
  113. static void sl_save(QEMUFile *f, void *opaque)
  114. {
  115. struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  116. qemu_put_8s(f, &s->ctl);
  117. ecc_put(f, &s->ecc);
  118. }
  119. static int sl_load(QEMUFile *f, void *opaque, int version_id)
  120. {
  121. struct sl_nand_s *s = (struct sl_nand_s *) opaque;
  122. qemu_get_8s(f, &s->ctl);
  123. ecc_get(f, &s->ecc);
  124. return 0;
  125. }
  126. enum {
  127. FLASH_128M,
  128. FLASH_1024M,
  129. };
  130. static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
  131. {
  132. int iomemtype;
  133. struct sl_nand_s *s;
  134. CPUReadMemoryFunc *sl_readfn[] = {
  135. sl_readb,
  136. sl_readb,
  137. sl_readl,
  138. };
  139. CPUWriteMemoryFunc *sl_writefn[] = {
  140. sl_writeb,
  141. sl_writeb,
  142. sl_writeb,
  143. };
  144. s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
  145. s->ctl = 0;
  146. if (size == FLASH_128M)
  147. s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
  148. else if (size == FLASH_1024M)
  149. s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
  150. iomemtype = cpu_register_io_memory(0, sl_readfn,
  151. sl_writefn, s);
  152. cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
  153. register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
  154. }
  155. /* Spitz Keyboard */
  156. #define SPITZ_KEY_STROBE_NUM 11
  157. #define SPITZ_KEY_SENSE_NUM 7
  158. static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
  159. 12, 17, 91, 34, 36, 38, 39
  160. };
  161. static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
  162. 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
  163. };
  164. /* Eighth additional row maps the special keys */
  165. static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
  166. { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
  167. { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
  168. { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
  169. { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
  170. { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
  171. { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
  172. { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
  173. { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
  174. };
  175. #define SPITZ_GPIO_AK_INT 13 /* Remote control */
  176. #define SPITZ_GPIO_SYNC 16 /* Sync button */
  177. #define SPITZ_GPIO_ON_KEY 95 /* Power button */
  178. #define SPITZ_GPIO_SWA 97 /* Lid */
  179. #define SPITZ_GPIO_SWB 96 /* Tablet mode */
  180. /* The special buttons are mapped to unused keys */
  181. static const int spitz_gpiomap[5] = {
  182. SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
  183. SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
  184. };
  185. static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
  186. struct spitz_keyboard_s {
  187. qemu_irq sense[SPITZ_KEY_SENSE_NUM];
  188. qemu_irq *strobe;
  189. qemu_irq gpiomap[5];
  190. int keymap[0x80];
  191. uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
  192. uint16_t strobe_state;
  193. uint16_t sense_state;
  194. uint16_t pre_map[0x100];
  195. uint16_t modifiers;
  196. uint16_t imodifiers;
  197. uint8_t fifo[16];
  198. int fifopos, fifolen;
  199. QEMUTimer *kbdtimer;
  200. };
  201. static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
  202. {
  203. int i;
  204. uint16_t strobe, sense = 0;
  205. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
  206. strobe = s->keyrow[i] & s->strobe_state;
  207. if (strobe) {
  208. sense |= 1 << i;
  209. if (!(s->sense_state & (1 << i)))
  210. qemu_irq_raise(s->sense[i]);
  211. } else if (s->sense_state & (1 << i))
  212. qemu_irq_lower(s->sense[i]);
  213. }
  214. s->sense_state = sense;
  215. }
  216. static void spitz_keyboard_strobe(void *opaque, int line, int level)
  217. {
  218. struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  219. if (level)
  220. s->strobe_state |= 1 << line;
  221. else
  222. s->strobe_state &= ~(1 << line);
  223. spitz_keyboard_sense_update(s);
  224. }
  225. static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
  226. {
  227. int spitz_keycode = s->keymap[keycode & 0x7f];
  228. if (spitz_keycode == -1)
  229. return;
  230. /* Handle the additional keys */
  231. if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
  232. qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
  233. spitz_gpio_invert[spitz_keycode & 0xf]);
  234. return;
  235. }
  236. if (keycode & 0x80)
  237. s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
  238. else
  239. s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
  240. spitz_keyboard_sense_update(s);
  241. }
  242. #define SHIFT (1 << 7)
  243. #define CTRL (1 << 8)
  244. #define FN (1 << 9)
  245. #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  246. static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
  247. {
  248. uint16_t code;
  249. int mapcode;
  250. switch (keycode) {
  251. case 0x2a: /* Left Shift */
  252. s->modifiers |= 1;
  253. break;
  254. case 0xaa:
  255. s->modifiers &= ~1;
  256. break;
  257. case 0x36: /* Right Shift */
  258. s->modifiers |= 2;
  259. break;
  260. case 0xb6:
  261. s->modifiers &= ~2;
  262. break;
  263. case 0x1d: /* Control */
  264. s->modifiers |= 4;
  265. break;
  266. case 0x9d:
  267. s->modifiers &= ~4;
  268. break;
  269. case 0x38: /* Alt */
  270. s->modifiers |= 8;
  271. break;
  272. case 0xb8:
  273. s->modifiers &= ~8;
  274. break;
  275. }
  276. code = s->pre_map[mapcode = ((s->modifiers & 3) ?
  277. (keycode | SHIFT) :
  278. (keycode & ~SHIFT))];
  279. if (code != mapcode) {
  280. #if 0
  281. if ((code & SHIFT) && !(s->modifiers & 1))
  282. QUEUE_KEY(0x2a | (keycode & 0x80));
  283. if ((code & CTRL ) && !(s->modifiers & 4))
  284. QUEUE_KEY(0x1d | (keycode & 0x80));
  285. if ((code & FN ) && !(s->modifiers & 8))
  286. QUEUE_KEY(0x38 | (keycode & 0x80));
  287. if ((code & FN ) && (s->modifiers & 1))
  288. QUEUE_KEY(0x2a | (~keycode & 0x80));
  289. if ((code & FN ) && (s->modifiers & 2))
  290. QUEUE_KEY(0x36 | (~keycode & 0x80));
  291. #else
  292. if (keycode & 0x80) {
  293. if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
  294. QUEUE_KEY(0x2a | 0x80);
  295. if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
  296. QUEUE_KEY(0x1d | 0x80);
  297. if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
  298. QUEUE_KEY(0x38 | 0x80);
  299. if ((s->imodifiers & 0x10) && (s->modifiers & 1))
  300. QUEUE_KEY(0x2a);
  301. if ((s->imodifiers & 0x20) && (s->modifiers & 2))
  302. QUEUE_KEY(0x36);
  303. s->imodifiers = 0;
  304. } else {
  305. if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
  306. QUEUE_KEY(0x2a);
  307. s->imodifiers |= 1;
  308. }
  309. if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
  310. QUEUE_KEY(0x1d);
  311. s->imodifiers |= 4;
  312. }
  313. if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
  314. QUEUE_KEY(0x38);
  315. s->imodifiers |= 8;
  316. }
  317. if ((code & FN ) && (s->modifiers & 1) &&
  318. !(s->imodifiers & 0x10)) {
  319. QUEUE_KEY(0x2a | 0x80);
  320. s->imodifiers |= 0x10;
  321. }
  322. if ((code & FN ) && (s->modifiers & 2) &&
  323. !(s->imodifiers & 0x20)) {
  324. QUEUE_KEY(0x36 | 0x80);
  325. s->imodifiers |= 0x20;
  326. }
  327. }
  328. #endif
  329. }
  330. QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
  331. }
  332. static void spitz_keyboard_tick(void *opaque)
  333. {
  334. struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  335. if (s->fifolen) {
  336. spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
  337. s->fifolen --;
  338. if (s->fifopos >= 16)
  339. s->fifopos = 0;
  340. }
  341. qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
  342. }
  343. static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
  344. {
  345. int i;
  346. for (i = 0; i < 0x100; i ++)
  347. s->pre_map[i] = i;
  348. s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
  349. s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
  350. s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
  351. s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
  352. s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
  353. s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
  354. s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
  355. s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
  356. s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
  357. s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
  358. s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
  359. s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
  360. s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
  361. s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
  362. s->pre_map[0x0d ] = 0x12 | FN; /* equal */
  363. s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
  364. s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
  365. s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
  366. s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
  367. s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
  368. s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
  369. s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
  370. s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
  371. s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
  372. s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
  373. s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
  374. s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
  375. s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
  376. s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
  377. s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
  378. s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
  379. s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
  380. s->modifiers = 0;
  381. s->imodifiers = 0;
  382. s->fifopos = 0;
  383. s->fifolen = 0;
  384. s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
  385. spitz_keyboard_tick(s);
  386. }
  387. #undef SHIFT
  388. #undef CTRL
  389. #undef FN
  390. static void spitz_keyboard_save(QEMUFile *f, void *opaque)
  391. {
  392. struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  393. int i;
  394. qemu_put_be16s(f, &s->sense_state);
  395. qemu_put_be16s(f, &s->strobe_state);
  396. for (i = 0; i < 5; i ++)
  397. qemu_put_byte(f, spitz_gpio_invert[i]);
  398. }
  399. static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
  400. {
  401. struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
  402. int i;
  403. qemu_get_be16s(f, &s->sense_state);
  404. qemu_get_be16s(f, &s->strobe_state);
  405. for (i = 0; i < 5; i ++)
  406. spitz_gpio_invert[i] = qemu_get_byte(f);
  407. /* Release all pressed keys */
  408. memset(s->keyrow, 0, sizeof(s->keyrow));
  409. spitz_keyboard_sense_update(s);
  410. s->modifiers = 0;
  411. s->imodifiers = 0;
  412. s->fifopos = 0;
  413. s->fifolen = 0;
  414. return 0;
  415. }
  416. static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
  417. {
  418. int i, j;
  419. struct spitz_keyboard_s *s;
  420. s = (struct spitz_keyboard_s *)
  421. qemu_mallocz(sizeof(struct spitz_keyboard_s));
  422. memset(s, 0, sizeof(struct spitz_keyboard_s));
  423. for (i = 0; i < 0x80; i ++)
  424. s->keymap[i] = -1;
  425. for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
  426. for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
  427. if (spitz_keymap[i][j] != -1)
  428. s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
  429. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
  430. s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
  431. for (i = 0; i < 5; i ++)
  432. s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
  433. s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
  434. SPITZ_KEY_STROBE_NUM);
  435. for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
  436. pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
  437. spitz_keyboard_pre_map(s);
  438. qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
  439. register_savevm("spitz_keyboard", 0, 0,
  440. spitz_keyboard_save, spitz_keyboard_load, s);
  441. }
  442. /* LCD backlight controller */
  443. #define LCDTG_RESCTL 0x00
  444. #define LCDTG_PHACTRL 0x01
  445. #define LCDTG_DUTYCTRL 0x02
  446. #define LCDTG_POWERREG0 0x03
  447. #define LCDTG_POWERREG1 0x04
  448. #define LCDTG_GPOR3 0x05
  449. #define LCDTG_PICTRL 0x06
  450. #define LCDTG_POLCTRL 0x07
  451. static int bl_intensity, bl_power;
  452. static void spitz_bl_update(struct pxa2xx_state_s *s)
  453. {
  454. if (bl_power && bl_intensity)
  455. zaurus_printf("LCD Backlight now at %i/63\n", bl_intensity);
  456. else
  457. zaurus_printf("LCD Backlight now off\n");
  458. }
  459. static inline void spitz_bl_bit5(void *opaque, int line, int level)
  460. {
  461. int prev = bl_intensity;
  462. if (level)
  463. bl_intensity &= ~0x20;
  464. else
  465. bl_intensity |= 0x20;
  466. if (bl_power && prev != bl_intensity)
  467. spitz_bl_update((struct pxa2xx_state_s *) opaque);
  468. }
  469. static inline void spitz_bl_power(void *opaque, int line, int level)
  470. {
  471. bl_power = !!level;
  472. spitz_bl_update((struct pxa2xx_state_s *) opaque);
  473. }
  474. static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
  475. {
  476. int addr, value;
  477. addr = cmd >> 5;
  478. value = cmd & 0x1f;
  479. switch (addr) {
  480. case LCDTG_RESCTL:
  481. if (value)
  482. zaurus_printf("LCD in QVGA mode\n");
  483. else
  484. zaurus_printf("LCD in VGA mode\n");
  485. break;
  486. case LCDTG_DUTYCTRL:
  487. bl_intensity &= ~0x1f;
  488. bl_intensity |= value;
  489. if (bl_power)
  490. spitz_bl_update((struct pxa2xx_state_s *) opaque);
  491. break;
  492. case LCDTG_POWERREG0:
  493. /* Set common voltage to M62332FP */
  494. break;
  495. }
  496. }
  497. /* SSP devices */
  498. #define CORGI_SSP_PORT 2
  499. #define SPITZ_GPIO_LCDCON_CS 53
  500. #define SPITZ_GPIO_ADS7846_CS 14
  501. #define SPITZ_GPIO_MAX1111_CS 20
  502. #define SPITZ_GPIO_TP_INT 11
  503. static int lcd_en, ads_en, max_en;
  504. static struct max111x_s *max1111;
  505. static struct ads7846_state_s *ads7846;
  506. /* "Demux" the signal based on current chipselect */
  507. static uint32_t corgi_ssp_read(void *opaque)
  508. {
  509. if (lcd_en)
  510. return 0;
  511. if (ads_en)
  512. return ads7846_read(ads7846);
  513. if (max_en)
  514. return max111x_read(max1111);
  515. return 0;
  516. }
  517. static void corgi_ssp_write(void *opaque, uint32_t value)
  518. {
  519. if (lcd_en)
  520. spitz_lcdtg_dac_put(opaque, value);
  521. if (ads_en)
  522. ads7846_write(ads7846, value);
  523. if (max_en)
  524. max111x_write(max1111, value);
  525. }
  526. static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  527. {
  528. switch (line) {
  529. case 0:
  530. lcd_en = !level;
  531. break;
  532. case 1:
  533. ads_en = !level;
  534. break;
  535. case 2:
  536. max_en = !level;
  537. break;
  538. }
  539. }
  540. #define MAX1111_BATT_VOLT 1
  541. #define MAX1111_BATT_TEMP 2
  542. #define MAX1111_ACIN_VOLT 3
  543. #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
  544. #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
  545. #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
  546. static void spitz_adc_temp_on(void *opaque, int line, int level)
  547. {
  548. if (!max1111)
  549. return;
  550. if (level)
  551. max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
  552. else
  553. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  554. }
  555. static void spitz_ssp_save(QEMUFile *f, void *opaque)
  556. {
  557. qemu_put_be32(f, lcd_en);
  558. qemu_put_be32(f, ads_en);
  559. qemu_put_be32(f, max_en);
  560. qemu_put_be32(f, bl_intensity);
  561. qemu_put_be32(f, bl_power);
  562. }
  563. static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
  564. {
  565. lcd_en = qemu_get_be32(f);
  566. ads_en = qemu_get_be32(f);
  567. max_en = qemu_get_be32(f);
  568. bl_intensity = qemu_get_be32(f);
  569. bl_power = qemu_get_be32(f);
  570. return 0;
  571. }
  572. static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
  573. {
  574. qemu_irq *chipselects;
  575. lcd_en = ads_en = max_en = 0;
  576. ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
  577. max1111 = max1111_init(0);
  578. max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
  579. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  580. max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
  581. pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
  582. corgi_ssp_write, cpu);
  583. chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
  584. pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
  585. pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
  586. pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
  587. bl_intensity = 0x20;
  588. bl_power = 0;
  589. register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
  590. }
  591. /* CF Microdrive */
  592. static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu, int slot)
  593. {
  594. struct pcmcia_card_s *md;
  595. int index;
  596. BlockDriverState *bs;
  597. index = drive_get_index(IF_IDE, 0, 0);
  598. if (index == -1)
  599. return;
  600. bs = drives_table[index].bdrv;
  601. if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
  602. md = dscm1xxxx_init(bs);
  603. pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
  604. }
  605. }
  606. /* Wm8750 and Max7310 on I2C */
  607. #define AKITA_MAX_ADDR 0x18
  608. #define SPITZ_WM_ADDRL 0x1b
  609. #define SPITZ_WM_ADDRH 0x1a
  610. #define SPITZ_GPIO_WM 5
  611. #ifdef HAS_AUDIO
  612. static void spitz_wm8750_addr(void *opaque, int line, int level)
  613. {
  614. i2c_slave *wm = (i2c_slave *) opaque;
  615. if (level)
  616. i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
  617. else
  618. i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
  619. }
  620. #endif
  621. static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
  622. {
  623. /* Attach the CPU on one end of our I2C bus. */
  624. i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
  625. #ifdef HAS_AUDIO
  626. AudioState *audio;
  627. i2c_slave *wm;
  628. audio = AUD_init();
  629. if (!audio)
  630. return;
  631. /* Attach a WM8750 to the bus */
  632. wm = wm8750_init(bus, audio);
  633. spitz_wm8750_addr(wm, 0, 0);
  634. pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
  635. qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
  636. /* .. and to the sound interface. */
  637. cpu->i2s->opaque = wm;
  638. cpu->i2s->codec_out = wm8750_dac_dat;
  639. cpu->i2s->codec_in = wm8750_adc_dat;
  640. wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
  641. #endif
  642. }
  643. static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
  644. {
  645. /* Attach a Max7310 to Akita I2C bus. */
  646. i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
  647. AKITA_MAX_ADDR);
  648. }
  649. /* Other peripherals */
  650. static void spitz_out_switch(void *opaque, int line, int level)
  651. {
  652. switch (line) {
  653. case 0:
  654. zaurus_printf("Charging %s.\n", level ? "off" : "on");
  655. break;
  656. case 1:
  657. zaurus_printf("Discharging %s.\n", level ? "on" : "off");
  658. break;
  659. case 2:
  660. zaurus_printf("Green LED %s.\n", level ? "on" : "off");
  661. break;
  662. case 3:
  663. zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
  664. break;
  665. case 4:
  666. spitz_bl_bit5(opaque, line, level);
  667. break;
  668. case 5:
  669. spitz_bl_power(opaque, line, level);
  670. break;
  671. case 6:
  672. spitz_adc_temp_on(opaque, line, level);
  673. break;
  674. }
  675. }
  676. #define SPITZ_SCP_LED_GREEN 1
  677. #define SPITZ_SCP_JK_B 2
  678. #define SPITZ_SCP_CHRG_ON 3
  679. #define SPITZ_SCP_MUTE_L 4
  680. #define SPITZ_SCP_MUTE_R 5
  681. #define SPITZ_SCP_CF_POWER 6
  682. #define SPITZ_SCP_LED_ORANGE 7
  683. #define SPITZ_SCP_JK_A 8
  684. #define SPITZ_SCP_ADC_TEMP_ON 9
  685. #define SPITZ_SCP2_IR_ON 1
  686. #define SPITZ_SCP2_AKIN_PULLUP 2
  687. #define SPITZ_SCP2_BACKLIGHT_CONT 7
  688. #define SPITZ_SCP2_BACKLIGHT_ON 8
  689. #define SPITZ_SCP2_MIC_BIAS 9
  690. static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
  691. struct scoop_info_s *scp0, struct scoop_info_s *scp1)
  692. {
  693. qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
  694. scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
  695. scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
  696. scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
  697. scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
  698. if (scp1) {
  699. scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
  700. scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
  701. }
  702. scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  703. }
  704. #define SPITZ_GPIO_HSYNC 22
  705. #define SPITZ_GPIO_SD_DETECT 9
  706. #define SPITZ_GPIO_SD_WP 81
  707. #define SPITZ_GPIO_ON_RESET 89
  708. #define SPITZ_GPIO_BAT_COVER 90
  709. #define SPITZ_GPIO_CF1_IRQ 105
  710. #define SPITZ_GPIO_CF1_CD 94
  711. #define SPITZ_GPIO_CF2_IRQ 106
  712. #define SPITZ_GPIO_CF2_CD 93
  713. static int spitz_hsync;
  714. static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
  715. {
  716. struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
  717. qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
  718. spitz_hsync ^= 1;
  719. }
  720. static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
  721. {
  722. qemu_irq lcd_hsync;
  723. /*
  724. * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
  725. * read to satisfy broken guests that poll-wait for hsync.
  726. * Simulating a real hsync event would be less practical and
  727. * wouldn't guarantee that a guest ever exits the loop.
  728. */
  729. spitz_hsync = 0;
  730. lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
  731. pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
  732. pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
  733. /* MMC/SD host */
  734. pxa2xx_mmci_handlers(cpu->mmc,
  735. pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
  736. pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
  737. /* Battery lock always closed */
  738. qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
  739. /* Handle reset */
  740. pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
  741. /* PCMCIA signals: card's IRQ and Card-Detect */
  742. if (slots >= 1)
  743. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
  744. pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
  745. pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
  746. if (slots >= 2)
  747. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
  748. pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
  749. pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
  750. /* Initialise the screen rotation related signals */
  751. spitz_gpio_invert[3] = 0; /* Always open */
  752. if (graphic_rotate) { /* Tablet mode */
  753. spitz_gpio_invert[4] = 0;
  754. } else { /* Portrait mode */
  755. spitz_gpio_invert[4] = 1;
  756. }
  757. qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
  758. spitz_gpio_invert[3]);
  759. qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
  760. spitz_gpio_invert[4]);
  761. }
  762. /* Board init. */
  763. enum spitz_model_e { spitz, akita, borzoi, terrier };
  764. #define SPITZ_RAM 0x04000000
  765. #define SPITZ_ROM 0x00800000
  766. static struct arm_boot_info spitz_binfo = {
  767. .loader_start = PXA2XX_SDRAM_BASE,
  768. .ram_size = 0x04000000,
  769. };
  770. static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
  771. const char *kernel_filename,
  772. const char *kernel_cmdline, const char *initrd_filename,
  773. const char *cpu_model, enum spitz_model_e model, int arm_id)
  774. {
  775. struct pxa2xx_state_s *cpu;
  776. struct scoop_info_s *scp0, *scp1 = NULL;
  777. if (!cpu_model)
  778. cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
  779. /* Setup CPU & memory */
  780. if (ram_size < SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE) {
  781. fprintf(stderr, "This platform requires %i bytes of memory\n",
  782. SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE);
  783. exit(1);
  784. }
  785. cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
  786. sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
  787. cpu_register_physical_memory(0, SPITZ_ROM,
  788. qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM);
  789. /* Setup peripherals */
  790. spitz_keyboard_register(cpu);
  791. spitz_ssp_attach(cpu);
  792. scp0 = scoop_init(cpu, 0, 0x10800000);
  793. if (model != akita) {
  794. scp1 = scoop_init(cpu, 1, 0x08800040);
  795. }
  796. spitz_scoop_gpio_setup(cpu, scp0, scp1);
  797. spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
  798. spitz_i2c_setup(cpu);
  799. if (model == akita)
  800. spitz_akita_i2c_setup(cpu);
  801. if (model == terrier)
  802. /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
  803. spitz_microdrive_attach(cpu, 1);
  804. else if (model != akita)
  805. /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
  806. spitz_microdrive_attach(cpu, 0);
  807. /* Setup initial (reset) machine state */
  808. cpu->env->regs[15] = spitz_binfo.loader_start;
  809. spitz_binfo.kernel_filename = kernel_filename;
  810. spitz_binfo.kernel_cmdline = kernel_cmdline;
  811. spitz_binfo.initrd_filename = initrd_filename;
  812. spitz_binfo.board_id = arm_id;
  813. arm_load_kernel(cpu->env, &spitz_binfo);
  814. sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
  815. }
  816. static void spitz_init(ram_addr_t ram_size, int vga_ram_size,
  817. const char *boot_device,
  818. const char *kernel_filename, const char *kernel_cmdline,
  819. const char *initrd_filename, const char *cpu_model)
  820. {
  821. spitz_common_init(ram_size, vga_ram_size, kernel_filename,
  822. kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
  823. }
  824. static void borzoi_init(ram_addr_t ram_size, int vga_ram_size,
  825. const char *boot_device,
  826. const char *kernel_filename, const char *kernel_cmdline,
  827. const char *initrd_filename, const char *cpu_model)
  828. {
  829. spitz_common_init(ram_size, vga_ram_size, kernel_filename,
  830. kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
  831. }
  832. static void akita_init(ram_addr_t ram_size, int vga_ram_size,
  833. const char *boot_device,
  834. const char *kernel_filename, const char *kernel_cmdline,
  835. const char *initrd_filename, const char *cpu_model)
  836. {
  837. spitz_common_init(ram_size, vga_ram_size, kernel_filename,
  838. kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
  839. }
  840. static void terrier_init(ram_addr_t ram_size, int vga_ram_size,
  841. const char *boot_device,
  842. const char *kernel_filename, const char *kernel_cmdline,
  843. const char *initrd_filename, const char *cpu_model)
  844. {
  845. spitz_common_init(ram_size, vga_ram_size, kernel_filename,
  846. kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
  847. }
  848. QEMUMachine akitapda_machine = {
  849. .name = "akita",
  850. .desc = "Akita PDA (PXA270)",
  851. .init = akita_init,
  852. .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
  853. };
  854. QEMUMachine spitzpda_machine = {
  855. .name = "spitz",
  856. .desc = "Spitz PDA (PXA270)",
  857. .init = spitz_init,
  858. .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
  859. };
  860. QEMUMachine borzoipda_machine = {
  861. .name = "borzoi",
  862. .desc = "Borzoi PDA (PXA270)",
  863. .init = borzoi_init,
  864. .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
  865. };
  866. QEMUMachine terrierpda_machine = {
  867. .name = "terrier",
  868. .desc = "Terrier PDA (PXA270)",
  869. .init = terrier_init,
  870. .ram_require = SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
  871. };