omap_dss.c 31 KB

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  1. /*
  2. * OMAP2 Display Subsystem.
  3. *
  4. * Copyright (C) 2008 Nokia Corporation
  5. * Written by Andrzej Zaborowski <andrew@openedhand.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 or
  10. * (at your option) version 3 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20. */
  21. #include "hw.h"
  22. #include "console.h"
  23. #include "omap.h"
  24. struct omap_dss_s {
  25. qemu_irq irq;
  26. qemu_irq drq;
  27. DisplayState *state;
  28. int autoidle;
  29. int control;
  30. int enable;
  31. struct omap_dss_panel_s {
  32. int enable;
  33. int nx;
  34. int ny;
  35. int x;
  36. int y;
  37. } dig, lcd;
  38. struct {
  39. uint32_t idlemode;
  40. uint32_t irqst;
  41. uint32_t irqen;
  42. uint32_t control;
  43. uint32_t config;
  44. uint32_t capable;
  45. uint32_t timing[4];
  46. int line;
  47. uint32_t bg[2];
  48. uint32_t trans[2];
  49. struct omap_dss_plane_s {
  50. int enable;
  51. int bpp;
  52. int posx;
  53. int posy;
  54. int nx;
  55. int ny;
  56. target_phys_addr_t addr[3];
  57. uint32_t attr;
  58. uint32_t tresh;
  59. int rowinc;
  60. int colinc;
  61. int wininc;
  62. } l[3];
  63. int invalidate;
  64. uint16_t palette[256];
  65. } dispc;
  66. struct {
  67. int idlemode;
  68. uint32_t control;
  69. int enable;
  70. int pixels;
  71. int busy;
  72. int skiplines;
  73. uint16_t rxbuf;
  74. uint32_t config[2];
  75. uint32_t time[4];
  76. uint32_t data[6];
  77. uint16_t vsync;
  78. uint16_t hsync;
  79. struct rfbi_chip_s *chip[2];
  80. } rfbi;
  81. };
  82. static void omap_dispc_interrupt_update(struct omap_dss_s *s)
  83. {
  84. qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen);
  85. }
  86. static void omap_rfbi_reset(struct omap_dss_s *s)
  87. {
  88. s->rfbi.idlemode = 0;
  89. s->rfbi.control = 2;
  90. s->rfbi.enable = 0;
  91. s->rfbi.pixels = 0;
  92. s->rfbi.skiplines = 0;
  93. s->rfbi.busy = 0;
  94. s->rfbi.config[0] = 0x00310000;
  95. s->rfbi.config[1] = 0x00310000;
  96. s->rfbi.time[0] = 0;
  97. s->rfbi.time[1] = 0;
  98. s->rfbi.time[2] = 0;
  99. s->rfbi.time[3] = 0;
  100. s->rfbi.data[0] = 0;
  101. s->rfbi.data[1] = 0;
  102. s->rfbi.data[2] = 0;
  103. s->rfbi.data[3] = 0;
  104. s->rfbi.data[4] = 0;
  105. s->rfbi.data[5] = 0;
  106. s->rfbi.vsync = 0;
  107. s->rfbi.hsync = 0;
  108. }
  109. void omap_dss_reset(struct omap_dss_s *s)
  110. {
  111. s->autoidle = 0;
  112. s->control = 0;
  113. s->enable = 0;
  114. s->dig.enable = 0;
  115. s->dig.nx = 1;
  116. s->dig.ny = 1;
  117. s->lcd.enable = 0;
  118. s->lcd.nx = 1;
  119. s->lcd.ny = 1;
  120. s->dispc.idlemode = 0;
  121. s->dispc.irqst = 0;
  122. s->dispc.irqen = 0;
  123. s->dispc.control = 0;
  124. s->dispc.config = 0;
  125. s->dispc.capable = 0x161;
  126. s->dispc.timing[0] = 0;
  127. s->dispc.timing[1] = 0;
  128. s->dispc.timing[2] = 0;
  129. s->dispc.timing[3] = 0;
  130. s->dispc.line = 0;
  131. s->dispc.bg[0] = 0;
  132. s->dispc.bg[1] = 0;
  133. s->dispc.trans[0] = 0;
  134. s->dispc.trans[1] = 0;
  135. s->dispc.l[0].enable = 0;
  136. s->dispc.l[0].bpp = 0;
  137. s->dispc.l[0].addr[0] = 0;
  138. s->dispc.l[0].addr[1] = 0;
  139. s->dispc.l[0].addr[2] = 0;
  140. s->dispc.l[0].posx = 0;
  141. s->dispc.l[0].posy = 0;
  142. s->dispc.l[0].nx = 1;
  143. s->dispc.l[0].ny = 1;
  144. s->dispc.l[0].attr = 0;
  145. s->dispc.l[0].tresh = 0;
  146. s->dispc.l[0].rowinc = 1;
  147. s->dispc.l[0].colinc = 1;
  148. s->dispc.l[0].wininc = 0;
  149. omap_rfbi_reset(s);
  150. omap_dispc_interrupt_update(s);
  151. }
  152. static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
  153. {
  154. struct omap_dss_s *s = (struct omap_dss_s *) opaque;
  155. switch (addr) {
  156. case 0x00: /* DSS_REVISIONNUMBER */
  157. return 0x20;
  158. case 0x10: /* DSS_SYSCONFIG */
  159. return s->autoidle;
  160. case 0x14: /* DSS_SYSSTATUS */
  161. return 1; /* RESETDONE */
  162. case 0x40: /* DSS_CONTROL */
  163. return s->control;
  164. case 0x50: /* DSS_PSA_LCD_REG_1 */
  165. case 0x54: /* DSS_PSA_LCD_REG_2 */
  166. case 0x58: /* DSS_PSA_VIDEO_REG */
  167. /* TODO: fake some values when appropriate s->control bits are set */
  168. return 0;
  169. case 0x5c: /* DSS_STATUS */
  170. return 1 + (s->control & 1);
  171. default:
  172. break;
  173. }
  174. OMAP_BAD_REG(addr);
  175. return 0;
  176. }
  177. static void omap_diss_write(void *opaque, target_phys_addr_t addr,
  178. uint32_t value)
  179. {
  180. struct omap_dss_s *s = (struct omap_dss_s *) opaque;
  181. switch (addr) {
  182. case 0x00: /* DSS_REVISIONNUMBER */
  183. case 0x14: /* DSS_SYSSTATUS */
  184. case 0x50: /* DSS_PSA_LCD_REG_1 */
  185. case 0x54: /* DSS_PSA_LCD_REG_2 */
  186. case 0x58: /* DSS_PSA_VIDEO_REG */
  187. case 0x5c: /* DSS_STATUS */
  188. OMAP_RO_REG(addr);
  189. break;
  190. case 0x10: /* DSS_SYSCONFIG */
  191. if (value & 2) /* SOFTRESET */
  192. omap_dss_reset(s);
  193. s->autoidle = value & 1;
  194. break;
  195. case 0x40: /* DSS_CONTROL */
  196. s->control = value & 0x3dd;
  197. break;
  198. default:
  199. OMAP_BAD_REG(addr);
  200. }
  201. }
  202. static CPUReadMemoryFunc *omap_diss1_readfn[] = {
  203. omap_badwidth_read32,
  204. omap_badwidth_read32,
  205. omap_diss_read,
  206. };
  207. static CPUWriteMemoryFunc *omap_diss1_writefn[] = {
  208. omap_badwidth_write32,
  209. omap_badwidth_write32,
  210. omap_diss_write,
  211. };
  212. static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
  213. {
  214. struct omap_dss_s *s = (struct omap_dss_s *) opaque;
  215. switch (addr) {
  216. case 0x000: /* DISPC_REVISION */
  217. return 0x20;
  218. case 0x010: /* DISPC_SYSCONFIG */
  219. return s->dispc.idlemode;
  220. case 0x014: /* DISPC_SYSSTATUS */
  221. return 1; /* RESETDONE */
  222. case 0x018: /* DISPC_IRQSTATUS */
  223. return s->dispc.irqst;
  224. case 0x01c: /* DISPC_IRQENABLE */
  225. return s->dispc.irqen;
  226. case 0x040: /* DISPC_CONTROL */
  227. return s->dispc.control;
  228. case 0x044: /* DISPC_CONFIG */
  229. return s->dispc.config;
  230. case 0x048: /* DISPC_CAPABLE */
  231. return s->dispc.capable;
  232. case 0x04c: /* DISPC_DEFAULT_COLOR0 */
  233. return s->dispc.bg[0];
  234. case 0x050: /* DISPC_DEFAULT_COLOR1 */
  235. return s->dispc.bg[1];
  236. case 0x054: /* DISPC_TRANS_COLOR0 */
  237. return s->dispc.trans[0];
  238. case 0x058: /* DISPC_TRANS_COLOR1 */
  239. return s->dispc.trans[1];
  240. case 0x05c: /* DISPC_LINE_STATUS */
  241. return 0x7ff;
  242. case 0x060: /* DISPC_LINE_NUMBER */
  243. return s->dispc.line;
  244. case 0x064: /* DISPC_TIMING_H */
  245. return s->dispc.timing[0];
  246. case 0x068: /* DISPC_TIMING_V */
  247. return s->dispc.timing[1];
  248. case 0x06c: /* DISPC_POL_FREQ */
  249. return s->dispc.timing[2];
  250. case 0x070: /* DISPC_DIVISOR */
  251. return s->dispc.timing[3];
  252. case 0x078: /* DISPC_SIZE_DIG */
  253. return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1);
  254. case 0x07c: /* DISPC_SIZE_LCD */
  255. return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1);
  256. case 0x080: /* DISPC_GFX_BA0 */
  257. return s->dispc.l[0].addr[0];
  258. case 0x084: /* DISPC_GFX_BA1 */
  259. return s->dispc.l[0].addr[1];
  260. case 0x088: /* DISPC_GFX_POSITION */
  261. return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx;
  262. case 0x08c: /* DISPC_GFX_SIZE */
  263. return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1);
  264. case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
  265. return s->dispc.l[0].attr;
  266. case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
  267. return s->dispc.l[0].tresh;
  268. case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
  269. return 256;
  270. case 0x0ac: /* DISPC_GFX_ROW_INC */
  271. return s->dispc.l[0].rowinc;
  272. case 0x0b0: /* DISPC_GFX_PIXEL_INC */
  273. return s->dispc.l[0].colinc;
  274. case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
  275. return s->dispc.l[0].wininc;
  276. case 0x0b8: /* DISPC_GFX_TABLE_BA */
  277. return s->dispc.l[0].addr[2];
  278. case 0x0bc: /* DISPC_VID1_BA0 */
  279. case 0x0c0: /* DISPC_VID1_BA1 */
  280. case 0x0c4: /* DISPC_VID1_POSITION */
  281. case 0x0c8: /* DISPC_VID1_SIZE */
  282. case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
  283. case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
  284. case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
  285. case 0x0d8: /* DISPC_VID1_ROW_INC */
  286. case 0x0dc: /* DISPC_VID1_PIXEL_INC */
  287. case 0x0e0: /* DISPC_VID1_FIR */
  288. case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
  289. case 0x0e8: /* DISPC_VID1_ACCU0 */
  290. case 0x0ec: /* DISPC_VID1_ACCU1 */
  291. case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
  292. case 0x14c: /* DISPC_VID2_BA0 */
  293. case 0x150: /* DISPC_VID2_BA1 */
  294. case 0x154: /* DISPC_VID2_POSITION */
  295. case 0x158: /* DISPC_VID2_SIZE */
  296. case 0x15c: /* DISPC_VID2_ATTRIBUTES */
  297. case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
  298. case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
  299. case 0x168: /* DISPC_VID2_ROW_INC */
  300. case 0x16c: /* DISPC_VID2_PIXEL_INC */
  301. case 0x170: /* DISPC_VID2_FIR */
  302. case 0x174: /* DISPC_VID2_PICTURE_SIZE */
  303. case 0x178: /* DISPC_VID2_ACCU0 */
  304. case 0x17c: /* DISPC_VID2_ACCU1 */
  305. case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
  306. case 0x1d4: /* DISPC_DATA_CYCLE1 */
  307. case 0x1d8: /* DISPC_DATA_CYCLE2 */
  308. case 0x1dc: /* DISPC_DATA_CYCLE3 */
  309. return 0;
  310. default:
  311. break;
  312. }
  313. OMAP_BAD_REG(addr);
  314. return 0;
  315. }
  316. static void omap_disc_write(void *opaque, target_phys_addr_t addr,
  317. uint32_t value)
  318. {
  319. struct omap_dss_s *s = (struct omap_dss_s *) opaque;
  320. switch (addr) {
  321. case 0x010: /* DISPC_SYSCONFIG */
  322. if (value & 2) /* SOFTRESET */
  323. omap_dss_reset(s);
  324. s->dispc.idlemode = value & 0x301b;
  325. break;
  326. case 0x018: /* DISPC_IRQSTATUS */
  327. s->dispc.irqst &= ~value;
  328. omap_dispc_interrupt_update(s);
  329. break;
  330. case 0x01c: /* DISPC_IRQENABLE */
  331. s->dispc.irqen = value & 0xffff;
  332. omap_dispc_interrupt_update(s);
  333. break;
  334. case 0x040: /* DISPC_CONTROL */
  335. s->dispc.control = value & 0x07ff9fff;
  336. s->dig.enable = (value >> 1) & 1;
  337. s->lcd.enable = (value >> 0) & 1;
  338. if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
  339. if (~((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1))
  340. fprintf(stderr, "%s: Overlay Optimization when no overlay "
  341. "region effectively exists leads to "
  342. "unpredictable behaviour!\n", __FUNCTION__);
  343. if (value & (1 << 6)) { /* GODIGITAL */
  344. /* XXX: Shadowed fields are:
  345. * s->dispc.config
  346. * s->dispc.capable
  347. * s->dispc.bg[0]
  348. * s->dispc.bg[1]
  349. * s->dispc.trans[0]
  350. * s->dispc.trans[1]
  351. * s->dispc.line
  352. * s->dispc.timing[0]
  353. * s->dispc.timing[1]
  354. * s->dispc.timing[2]
  355. * s->dispc.timing[3]
  356. * s->lcd.nx
  357. * s->lcd.ny
  358. * s->dig.nx
  359. * s->dig.ny
  360. * s->dispc.l[0].addr[0]
  361. * s->dispc.l[0].addr[1]
  362. * s->dispc.l[0].addr[2]
  363. * s->dispc.l[0].posx
  364. * s->dispc.l[0].posy
  365. * s->dispc.l[0].nx
  366. * s->dispc.l[0].ny
  367. * s->dispc.l[0].tresh
  368. * s->dispc.l[0].rowinc
  369. * s->dispc.l[0].colinc
  370. * s->dispc.l[0].wininc
  371. * All they need to be loaded here from their shadow registers.
  372. */
  373. }
  374. if (value & (1 << 5)) { /* GOLCD */
  375. /* XXX: Likewise for LCD here. */
  376. }
  377. s->dispc.invalidate = 1;
  378. break;
  379. case 0x044: /* DISPC_CONFIG */
  380. s->dispc.config = value & 0x3fff;
  381. /* XXX:
  382. * bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
  383. * bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
  384. */
  385. s->dispc.invalidate = 1;
  386. break;
  387. case 0x048: /* DISPC_CAPABLE */
  388. s->dispc.capable = value & 0x3ff;
  389. break;
  390. case 0x04c: /* DISPC_DEFAULT_COLOR0 */
  391. s->dispc.bg[0] = value & 0xffffff;
  392. s->dispc.invalidate = 1;
  393. break;
  394. case 0x050: /* DISPC_DEFAULT_COLOR1 */
  395. s->dispc.bg[1] = value & 0xffffff;
  396. s->dispc.invalidate = 1;
  397. break;
  398. case 0x054: /* DISPC_TRANS_COLOR0 */
  399. s->dispc.trans[0] = value & 0xffffff;
  400. s->dispc.invalidate = 1;
  401. break;
  402. case 0x058: /* DISPC_TRANS_COLOR1 */
  403. s->dispc.trans[1] = value & 0xffffff;
  404. s->dispc.invalidate = 1;
  405. break;
  406. case 0x060: /* DISPC_LINE_NUMBER */
  407. s->dispc.line = value & 0x7ff;
  408. break;
  409. case 0x064: /* DISPC_TIMING_H */
  410. s->dispc.timing[0] = value & 0x0ff0ff3f;
  411. break;
  412. case 0x068: /* DISPC_TIMING_V */
  413. s->dispc.timing[1] = value & 0x0ff0ff3f;
  414. break;
  415. case 0x06c: /* DISPC_POL_FREQ */
  416. s->dispc.timing[2] = value & 0x0003ffff;
  417. break;
  418. case 0x070: /* DISPC_DIVISOR */
  419. s->dispc.timing[3] = value & 0x00ff00ff;
  420. break;
  421. case 0x078: /* DISPC_SIZE_DIG */
  422. s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
  423. s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
  424. s->dispc.invalidate = 1;
  425. break;
  426. case 0x07c: /* DISPC_SIZE_LCD */
  427. s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
  428. s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
  429. s->dispc.invalidate = 1;
  430. break;
  431. case 0x080: /* DISPC_GFX_BA0 */
  432. s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
  433. s->dispc.invalidate = 1;
  434. break;
  435. case 0x084: /* DISPC_GFX_BA1 */
  436. s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
  437. s->dispc.invalidate = 1;
  438. break;
  439. case 0x088: /* DISPC_GFX_POSITION */
  440. s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
  441. s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
  442. s->dispc.invalidate = 1;
  443. break;
  444. case 0x08c: /* DISPC_GFX_SIZE */
  445. s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
  446. s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
  447. s->dispc.invalidate = 1;
  448. break;
  449. case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
  450. s->dispc.l[0].attr = value & 0x7ff;
  451. if (value & (3 << 9))
  452. fprintf(stderr, "%s: Big-endian pixel format not supported\n",
  453. __FUNCTION__);
  454. s->dispc.l[0].enable = value & 1;
  455. s->dispc.l[0].bpp = (value >> 1) & 0xf;
  456. s->dispc.invalidate = 1;
  457. break;
  458. case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
  459. s->dispc.l[0].tresh = value & 0x01ff01ff;
  460. break;
  461. case 0x0ac: /* DISPC_GFX_ROW_INC */
  462. s->dispc.l[0].rowinc = value;
  463. s->dispc.invalidate = 1;
  464. break;
  465. case 0x0b0: /* DISPC_GFX_PIXEL_INC */
  466. s->dispc.l[0].colinc = value;
  467. s->dispc.invalidate = 1;
  468. break;
  469. case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
  470. s->dispc.l[0].wininc = value;
  471. break;
  472. case 0x0b8: /* DISPC_GFX_TABLE_BA */
  473. s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
  474. s->dispc.invalidate = 1;
  475. break;
  476. case 0x0bc: /* DISPC_VID1_BA0 */
  477. case 0x0c0: /* DISPC_VID1_BA1 */
  478. case 0x0c4: /* DISPC_VID1_POSITION */
  479. case 0x0c8: /* DISPC_VID1_SIZE */
  480. case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
  481. case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
  482. case 0x0d8: /* DISPC_VID1_ROW_INC */
  483. case 0x0dc: /* DISPC_VID1_PIXEL_INC */
  484. case 0x0e0: /* DISPC_VID1_FIR */
  485. case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
  486. case 0x0e8: /* DISPC_VID1_ACCU0 */
  487. case 0x0ec: /* DISPC_VID1_ACCU1 */
  488. case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
  489. case 0x14c: /* DISPC_VID2_BA0 */
  490. case 0x150: /* DISPC_VID2_BA1 */
  491. case 0x154: /* DISPC_VID2_POSITION */
  492. case 0x158: /* DISPC_VID2_SIZE */
  493. case 0x15c: /* DISPC_VID2_ATTRIBUTES */
  494. case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
  495. case 0x168: /* DISPC_VID2_ROW_INC */
  496. case 0x16c: /* DISPC_VID2_PIXEL_INC */
  497. case 0x170: /* DISPC_VID2_FIR */
  498. case 0x174: /* DISPC_VID2_PICTURE_SIZE */
  499. case 0x178: /* DISPC_VID2_ACCU0 */
  500. case 0x17c: /* DISPC_VID2_ACCU1 */
  501. case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
  502. case 0x1d4: /* DISPC_DATA_CYCLE1 */
  503. case 0x1d8: /* DISPC_DATA_CYCLE2 */
  504. case 0x1dc: /* DISPC_DATA_CYCLE3 */
  505. break;
  506. default:
  507. OMAP_BAD_REG(addr);
  508. }
  509. }
  510. static CPUReadMemoryFunc *omap_disc1_readfn[] = {
  511. omap_badwidth_read32,
  512. omap_badwidth_read32,
  513. omap_disc_read,
  514. };
  515. static CPUWriteMemoryFunc *omap_disc1_writefn[] = {
  516. omap_badwidth_write32,
  517. omap_badwidth_write32,
  518. omap_disc_write,
  519. };
  520. static void *omap_rfbi_get_buffer(struct omap_dss_s *s)
  521. {
  522. target_phys_addr_t fb;
  523. uint32_t pd;
  524. /* TODO */
  525. fb = s->dispc.l[0].addr[0];
  526. pd = cpu_get_physical_page_desc(fb);
  527. if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
  528. /* TODO */
  529. cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n",
  530. __FUNCTION__);
  531. else
  532. return phys_ram_base +
  533. (pd & TARGET_PAGE_MASK) +
  534. (fb & ~TARGET_PAGE_MASK);
  535. }
  536. static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
  537. {
  538. if (!s->rfbi.busy)
  539. return;
  540. /* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
  541. s->rfbi.busy = 0;
  542. }
  543. static void omap_rfbi_transfer_start(struct omap_dss_s *s)
  544. {
  545. void *data;
  546. size_t len;
  547. int pitch;
  548. if (!s->rfbi.enable || s->rfbi.busy)
  549. return;
  550. if (s->rfbi.control & (1 << 1)) { /* BYPASS */
  551. /* TODO: in non-Bypass mode we probably need to just assert the
  552. * DRQ and wait for DMA to write the pixels. */
  553. fprintf(stderr, "%s: Bypass mode unimplemented\n", __FUNCTION__);
  554. return;
  555. }
  556. if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
  557. return;
  558. /* TODO: check that LCD output is enabled in DISPC. */
  559. s->rfbi.busy = 1;
  560. data = omap_rfbi_get_buffer(s);
  561. /* TODO bpp */
  562. len = s->rfbi.pixels * 2;
  563. s->rfbi.pixels = 0;
  564. /* TODO: negative values */
  565. pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2;
  566. if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
  567. s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch);
  568. if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
  569. s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch);
  570. omap_rfbi_transfer_stop(s);
  571. /* TODO */
  572. s->dispc.irqst |= 1; /* FRAMEDONE */
  573. omap_dispc_interrupt_update(s);
  574. }
  575. static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
  576. {
  577. struct omap_dss_s *s = (struct omap_dss_s *) opaque;
  578. switch (addr) {
  579. case 0x00: /* RFBI_REVISION */
  580. return 0x10;
  581. case 0x10: /* RFBI_SYSCONFIG */
  582. return s->rfbi.idlemode;
  583. case 0x14: /* RFBI_SYSSTATUS */
  584. return 1 | (s->rfbi.busy << 8); /* RESETDONE */
  585. case 0x40: /* RFBI_CONTROL */
  586. return s->rfbi.control;
  587. case 0x44: /* RFBI_PIXELCNT */
  588. return s->rfbi.pixels;
  589. case 0x48: /* RFBI_LINE_NUMBER */
  590. return s->rfbi.skiplines;
  591. case 0x58: /* RFBI_READ */
  592. case 0x5c: /* RFBI_STATUS */
  593. return s->rfbi.rxbuf;
  594. case 0x60: /* RFBI_CONFIG0 */
  595. return s->rfbi.config[0];
  596. case 0x64: /* RFBI_ONOFF_TIME0 */
  597. return s->rfbi.time[0];
  598. case 0x68: /* RFBI_CYCLE_TIME0 */
  599. return s->rfbi.time[1];
  600. case 0x6c: /* RFBI_DATA_CYCLE1_0 */
  601. return s->rfbi.data[0];
  602. case 0x70: /* RFBI_DATA_CYCLE2_0 */
  603. return s->rfbi.data[1];
  604. case 0x74: /* RFBI_DATA_CYCLE3_0 */
  605. return s->rfbi.data[2];
  606. case 0x78: /* RFBI_CONFIG1 */
  607. return s->rfbi.config[1];
  608. case 0x7c: /* RFBI_ONOFF_TIME1 */
  609. return s->rfbi.time[2];
  610. case 0x80: /* RFBI_CYCLE_TIME1 */
  611. return s->rfbi.time[3];
  612. case 0x84: /* RFBI_DATA_CYCLE1_1 */
  613. return s->rfbi.data[3];
  614. case 0x88: /* RFBI_DATA_CYCLE2_1 */
  615. return s->rfbi.data[4];
  616. case 0x8c: /* RFBI_DATA_CYCLE3_1 */
  617. return s->rfbi.data[5];
  618. case 0x90: /* RFBI_VSYNC_WIDTH */
  619. return s->rfbi.vsync;
  620. case 0x94: /* RFBI_HSYNC_WIDTH */
  621. return s->rfbi.hsync;
  622. }
  623. OMAP_BAD_REG(addr);
  624. return 0;
  625. }
  626. static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
  627. uint32_t value)
  628. {
  629. struct omap_dss_s *s = (struct omap_dss_s *) opaque;
  630. switch (addr) {
  631. case 0x10: /* RFBI_SYSCONFIG */
  632. if (value & 2) /* SOFTRESET */
  633. omap_rfbi_reset(s);
  634. s->rfbi.idlemode = value & 0x19;
  635. break;
  636. case 0x40: /* RFBI_CONTROL */
  637. s->rfbi.control = value & 0xf;
  638. s->rfbi.enable = value & 1;
  639. if (value & (1 << 4) && /* ITE */
  640. !(s->rfbi.config[0] & s->rfbi.config[1] & 0xc))
  641. omap_rfbi_transfer_start(s);
  642. break;
  643. case 0x44: /* RFBI_PIXELCNT */
  644. s->rfbi.pixels = value;
  645. break;
  646. case 0x48: /* RFBI_LINE_NUMBER */
  647. s->rfbi.skiplines = value & 0x7ff;
  648. break;
  649. case 0x4c: /* RFBI_CMD */
  650. if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
  651. s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff);
  652. if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
  653. s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff);
  654. break;
  655. case 0x50: /* RFBI_PARAM */
  656. if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
  657. s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
  658. if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
  659. s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
  660. break;
  661. case 0x54: /* RFBI_DATA */
  662. /* TODO: take into account the format set up in s->rfbi.config[?] and
  663. * s->rfbi.data[?], but special-case the most usual scenario so that
  664. * speed doesn't suffer. */
  665. if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) {
  666. s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
  667. s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16);
  668. }
  669. if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) {
  670. s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
  671. s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16);
  672. }
  673. if (!-- s->rfbi.pixels)
  674. omap_rfbi_transfer_stop(s);
  675. break;
  676. case 0x58: /* RFBI_READ */
  677. if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
  678. s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
  679. else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
  680. s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
  681. if (!-- s->rfbi.pixels)
  682. omap_rfbi_transfer_stop(s);
  683. break;
  684. case 0x5c: /* RFBI_STATUS */
  685. if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
  686. s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
  687. else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
  688. s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
  689. if (!-- s->rfbi.pixels)
  690. omap_rfbi_transfer_stop(s);
  691. break;
  692. case 0x60: /* RFBI_CONFIG0 */
  693. s->rfbi.config[0] = value & 0x003f1fff;
  694. break;
  695. case 0x64: /* RFBI_ONOFF_TIME0 */
  696. s->rfbi.time[0] = value & 0x3fffffff;
  697. break;
  698. case 0x68: /* RFBI_CYCLE_TIME0 */
  699. s->rfbi.time[1] = value & 0x0fffffff;
  700. break;
  701. case 0x6c: /* RFBI_DATA_CYCLE1_0 */
  702. s->rfbi.data[0] = value & 0x0f1f0f1f;
  703. break;
  704. case 0x70: /* RFBI_DATA_CYCLE2_0 */
  705. s->rfbi.data[1] = value & 0x0f1f0f1f;
  706. break;
  707. case 0x74: /* RFBI_DATA_CYCLE3_0 */
  708. s->rfbi.data[2] = value & 0x0f1f0f1f;
  709. break;
  710. case 0x78: /* RFBI_CONFIG1 */
  711. s->rfbi.config[1] = value & 0x003f1fff;
  712. break;
  713. case 0x7c: /* RFBI_ONOFF_TIME1 */
  714. s->rfbi.time[2] = value & 0x3fffffff;
  715. break;
  716. case 0x80: /* RFBI_CYCLE_TIME1 */
  717. s->rfbi.time[3] = value & 0x0fffffff;
  718. break;
  719. case 0x84: /* RFBI_DATA_CYCLE1_1 */
  720. s->rfbi.data[3] = value & 0x0f1f0f1f;
  721. break;
  722. case 0x88: /* RFBI_DATA_CYCLE2_1 */
  723. s->rfbi.data[4] = value & 0x0f1f0f1f;
  724. break;
  725. case 0x8c: /* RFBI_DATA_CYCLE3_1 */
  726. s->rfbi.data[5] = value & 0x0f1f0f1f;
  727. break;
  728. case 0x90: /* RFBI_VSYNC_WIDTH */
  729. s->rfbi.vsync = value & 0xffff;
  730. break;
  731. case 0x94: /* RFBI_HSYNC_WIDTH */
  732. s->rfbi.hsync = value & 0xffff;
  733. break;
  734. default:
  735. OMAP_BAD_REG(addr);
  736. }
  737. }
  738. static CPUReadMemoryFunc *omap_rfbi1_readfn[] = {
  739. omap_badwidth_read32,
  740. omap_badwidth_read32,
  741. omap_rfbi_read,
  742. };
  743. static CPUWriteMemoryFunc *omap_rfbi1_writefn[] = {
  744. omap_badwidth_write32,
  745. omap_badwidth_write32,
  746. omap_rfbi_write,
  747. };
  748. static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
  749. {
  750. switch (addr) {
  751. case 0x00: /* REV_ID */
  752. case 0x04: /* STATUS */
  753. case 0x08: /* F_CONTROL */
  754. case 0x10: /* VIDOUT_CTRL */
  755. case 0x14: /* SYNC_CTRL */
  756. case 0x1c: /* LLEN */
  757. case 0x20: /* FLENS */
  758. case 0x24: /* HFLTR_CTRL */
  759. case 0x28: /* CC_CARR_WSS_CARR */
  760. case 0x2c: /* C_PHASE */
  761. case 0x30: /* GAIN_U */
  762. case 0x34: /* GAIN_V */
  763. case 0x38: /* GAIN_Y */
  764. case 0x3c: /* BLACK_LEVEL */
  765. case 0x40: /* BLANK_LEVEL */
  766. case 0x44: /* X_COLOR */
  767. case 0x48: /* M_CONTROL */
  768. case 0x4c: /* BSTAMP_WSS_DATA */
  769. case 0x50: /* S_CARR */
  770. case 0x54: /* LINE21 */
  771. case 0x58: /* LN_SEL */
  772. case 0x5c: /* L21__WC_CTL */
  773. case 0x60: /* HTRIGGER_VTRIGGER */
  774. case 0x64: /* SAVID__EAVID */
  775. case 0x68: /* FLEN__FAL */
  776. case 0x6c: /* LAL__PHASE_RESET */
  777. case 0x70: /* HS_INT_START_STOP_X */
  778. case 0x74: /* HS_EXT_START_STOP_X */
  779. case 0x78: /* VS_INT_START_X */
  780. case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
  781. case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
  782. case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
  783. case 0x88: /* VS_EXT_STOP_Y */
  784. case 0x90: /* AVID_START_STOP_X */
  785. case 0x94: /* AVID_START_STOP_Y */
  786. case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
  787. case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
  788. case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
  789. case 0xb0: /* TVDETGP_INT_START_STOP_X */
  790. case 0xb4: /* TVDETGP_INT_START_STOP_Y */
  791. case 0xb8: /* GEN_CTRL */
  792. case 0xc4: /* DAC_TST__DAC_A */
  793. case 0xc8: /* DAC_B__DAC_C */
  794. return 0;
  795. default:
  796. break;
  797. }
  798. OMAP_BAD_REG(addr);
  799. return 0;
  800. }
  801. static void omap_venc_write(void *opaque, target_phys_addr_t addr,
  802. uint32_t value)
  803. {
  804. switch (addr) {
  805. case 0x08: /* F_CONTROL */
  806. case 0x10: /* VIDOUT_CTRL */
  807. case 0x14: /* SYNC_CTRL */
  808. case 0x1c: /* LLEN */
  809. case 0x20: /* FLENS */
  810. case 0x24: /* HFLTR_CTRL */
  811. case 0x28: /* CC_CARR_WSS_CARR */
  812. case 0x2c: /* C_PHASE */
  813. case 0x30: /* GAIN_U */
  814. case 0x34: /* GAIN_V */
  815. case 0x38: /* GAIN_Y */
  816. case 0x3c: /* BLACK_LEVEL */
  817. case 0x40: /* BLANK_LEVEL */
  818. case 0x44: /* X_COLOR */
  819. case 0x48: /* M_CONTROL */
  820. case 0x4c: /* BSTAMP_WSS_DATA */
  821. case 0x50: /* S_CARR */
  822. case 0x54: /* LINE21 */
  823. case 0x58: /* LN_SEL */
  824. case 0x5c: /* L21__WC_CTL */
  825. case 0x60: /* HTRIGGER_VTRIGGER */
  826. case 0x64: /* SAVID__EAVID */
  827. case 0x68: /* FLEN__FAL */
  828. case 0x6c: /* LAL__PHASE_RESET */
  829. case 0x70: /* HS_INT_START_STOP_X */
  830. case 0x74: /* HS_EXT_START_STOP_X */
  831. case 0x78: /* VS_INT_START_X */
  832. case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
  833. case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
  834. case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
  835. case 0x88: /* VS_EXT_STOP_Y */
  836. case 0x90: /* AVID_START_STOP_X */
  837. case 0x94: /* AVID_START_STOP_Y */
  838. case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
  839. case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
  840. case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
  841. case 0xb0: /* TVDETGP_INT_START_STOP_X */
  842. case 0xb4: /* TVDETGP_INT_START_STOP_Y */
  843. case 0xb8: /* GEN_CTRL */
  844. case 0xc4: /* DAC_TST__DAC_A */
  845. case 0xc8: /* DAC_B__DAC_C */
  846. break;
  847. default:
  848. OMAP_BAD_REG(addr);
  849. }
  850. }
  851. static CPUReadMemoryFunc *omap_venc1_readfn[] = {
  852. omap_badwidth_read32,
  853. omap_badwidth_read32,
  854. omap_venc_read,
  855. };
  856. static CPUWriteMemoryFunc *omap_venc1_writefn[] = {
  857. omap_badwidth_write32,
  858. omap_badwidth_write32,
  859. omap_venc_write,
  860. };
  861. static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
  862. {
  863. switch (addr) {
  864. case 0x0a8: /* SBIMERRLOGA */
  865. case 0x0b0: /* SBIMERRLOG */
  866. case 0x190: /* SBIMSTATE */
  867. case 0x198: /* SBTMSTATE_L */
  868. case 0x19c: /* SBTMSTATE_H */
  869. case 0x1a8: /* SBIMCONFIG_L */
  870. case 0x1ac: /* SBIMCONFIG_H */
  871. case 0x1f8: /* SBID_L */
  872. case 0x1fc: /* SBID_H */
  873. return 0;
  874. default:
  875. break;
  876. }
  877. OMAP_BAD_REG(addr);
  878. return 0;
  879. }
  880. static void omap_im3_write(void *opaque, target_phys_addr_t addr,
  881. uint32_t value)
  882. {
  883. switch (addr) {
  884. case 0x0b0: /* SBIMERRLOG */
  885. case 0x190: /* SBIMSTATE */
  886. case 0x198: /* SBTMSTATE_L */
  887. case 0x19c: /* SBTMSTATE_H */
  888. case 0x1a8: /* SBIMCONFIG_L */
  889. case 0x1ac: /* SBIMCONFIG_H */
  890. break;
  891. default:
  892. OMAP_BAD_REG(addr);
  893. }
  894. }
  895. static CPUReadMemoryFunc *omap_im3_readfn[] = {
  896. omap_badwidth_read32,
  897. omap_badwidth_read32,
  898. omap_im3_read,
  899. };
  900. static CPUWriteMemoryFunc *omap_im3_writefn[] = {
  901. omap_badwidth_write32,
  902. omap_badwidth_write32,
  903. omap_im3_write,
  904. };
  905. struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
  906. target_phys_addr_t l3_base,
  907. qemu_irq irq, qemu_irq drq,
  908. omap_clk fck1, omap_clk fck2, omap_clk ck54m,
  909. omap_clk ick1, omap_clk ick2)
  910. {
  911. int iomemtype[5];
  912. struct omap_dss_s *s = (struct omap_dss_s *)
  913. qemu_mallocz(sizeof(struct omap_dss_s));
  914. s->irq = irq;
  915. s->drq = drq;
  916. omap_dss_reset(s);
  917. iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn,
  918. omap_diss1_writefn, s);
  919. iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn,
  920. omap_disc1_writefn, s);
  921. iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn,
  922. omap_rfbi1_writefn, s);
  923. iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn,
  924. omap_venc1_writefn, s);
  925. iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
  926. omap_im3_writefn, s);
  927. omap_l4_attach(ta, 0, iomemtype[0]);
  928. omap_l4_attach(ta, 1, iomemtype[1]);
  929. omap_l4_attach(ta, 2, iomemtype[2]);
  930. omap_l4_attach(ta, 3, iomemtype[3]);
  931. cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]);
  932. #if 0
  933. s->state = graphic_console_init(omap_update_display,
  934. omap_invalidate_display, omap_screen_dump, s);
  935. #endif
  936. return s;
  937. }
  938. void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip)
  939. {
  940. if (cs < 0 || cs > 1)
  941. cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
  942. s->rfbi.chip[cs] = chip;
  943. }