es1370.c 30 KB

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  1. /*
  2. * QEMU ES1370 emulation
  3. *
  4. * Copyright (c) 2005 Vassili Karpov (malc)
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. /* #define DEBUG_ES1370 */
  25. /* #define VERBOSE_ES1370 */
  26. #define SILENT_ES1370
  27. #include "hw.h"
  28. #include "audiodev.h"
  29. #include "audio/audio.h"
  30. #include "pci.h"
  31. /* Missing stuff:
  32. SCTRL_P[12](END|ST)INC
  33. SCTRL_P1SCTRLD
  34. SCTRL_P2DACSEN
  35. CTRL_DAC_SYNC
  36. MIDI
  37. non looped mode
  38. surely more
  39. */
  40. /*
  41. Following macros and samplerate array were copied verbatim from
  42. Linux kernel 2.4.30: drivers/sound/es1370.c
  43. Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
  44. */
  45. /* Start blatant GPL violation */
  46. #define ES1370_REG_CONTROL 0x00
  47. #define ES1370_REG_STATUS 0x04
  48. #define ES1370_REG_UART_DATA 0x08
  49. #define ES1370_REG_UART_STATUS 0x09
  50. #define ES1370_REG_UART_CONTROL 0x09
  51. #define ES1370_REG_UART_TEST 0x0a
  52. #define ES1370_REG_MEMPAGE 0x0c
  53. #define ES1370_REG_CODEC 0x10
  54. #define ES1370_REG_SERIAL_CONTROL 0x20
  55. #define ES1370_REG_DAC1_SCOUNT 0x24
  56. #define ES1370_REG_DAC2_SCOUNT 0x28
  57. #define ES1370_REG_ADC_SCOUNT 0x2c
  58. #define ES1370_REG_DAC1_FRAMEADR 0xc30
  59. #define ES1370_REG_DAC1_FRAMECNT 0xc34
  60. #define ES1370_REG_DAC2_FRAMEADR 0xc38
  61. #define ES1370_REG_DAC2_FRAMECNT 0xc3c
  62. #define ES1370_REG_ADC_FRAMEADR 0xd30
  63. #define ES1370_REG_ADC_FRAMECNT 0xd34
  64. #define ES1370_REG_PHANTOM_FRAMEADR 0xd38
  65. #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
  66. static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
  67. #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
  68. #define DAC2_DIVTOSR(x) (1411200/((x)+2))
  69. #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
  70. #define CTRL_XCTL1 0x40000000 /* electret mic bias */
  71. #define CTRL_OPEN 0x20000000 /* no function, can be read and written */
  72. #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
  73. #define CTRL_SH_PCLKDIV 16
  74. #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
  75. #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
  76. #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
  77. #define CTRL_SH_WTSRSEL 12
  78. #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
  79. #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
  80. #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */
  81. #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
  82. #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
  83. #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
  84. #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
  85. #define CTRL_ADC_EN 0x00000010 /* enable ADC */
  86. #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
  87. #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */
  88. #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
  89. #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
  90. #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
  91. #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */
  92. #define STAT_CBUSY 0x00000200 /* 1 = codec busy */
  93. #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
  94. #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
  95. #define STAT_SH_VC 5
  96. #define STAT_MCCB 0x00000010 /* CCB int pending */
  97. #define STAT_UART 0x00000008 /* UART int pending */
  98. #define STAT_DAC1 0x00000004 /* DAC1 int pending */
  99. #define STAT_DAC2 0x00000002 /* DAC2 int pending */
  100. #define STAT_ADC 0x00000001 /* ADC int pending */
  101. #define USTAT_RXINT 0x80 /* UART rx int pending */
  102. #define USTAT_TXINT 0x04 /* UART tx int pending */
  103. #define USTAT_TXRDY 0x02 /* UART tx ready */
  104. #define USTAT_RXRDY 0x01 /* UART rx ready */
  105. #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
  106. #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
  107. #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
  108. #define UCTRL_CNTRL 0x03 /* control field */
  109. #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
  110. #define SCTRL_P2ENDINC 0x00380000 /* */
  111. #define SCTRL_SH_P2ENDINC 19
  112. #define SCTRL_P2STINC 0x00070000 /* */
  113. #define SCTRL_SH_P2STINC 16
  114. #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
  115. #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
  116. #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
  117. #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
  118. #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
  119. #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
  120. #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
  121. #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
  122. #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
  123. #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
  124. #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
  125. #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
  126. #define SCTRL_R1FMT 0x00000030 /* format mask */
  127. #define SCTRL_SH_R1FMT 4
  128. #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
  129. #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
  130. #define SCTRL_P2FMT 0x0000000c /* format mask */
  131. #define SCTRL_SH_P2FMT 2
  132. #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
  133. #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
  134. #define SCTRL_P1FMT 0x00000003 /* format mask */
  135. #define SCTRL_SH_P1FMT 0
  136. /* End blatant GPL violation */
  137. #define NB_CHANNELS 3
  138. #define DAC1_CHANNEL 0
  139. #define DAC2_CHANNEL 1
  140. #define ADC_CHANNEL 2
  141. #define IO_READ_PROTO(n) \
  142. static uint32_t n (void *opaque, uint32_t addr)
  143. #define IO_WRITE_PROTO(n) \
  144. static void n (void *opaque, uint32_t addr, uint32_t val)
  145. static void es1370_dac1_callback (void *opaque, int free);
  146. static void es1370_dac2_callback (void *opaque, int free);
  147. static void es1370_adc_callback (void *opaque, int avail);
  148. #ifdef DEBUG_ES1370
  149. #define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
  150. static void print_ctl (uint32_t val)
  151. {
  152. char buf[1024];
  153. buf[0] = '\0';
  154. #define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
  155. a (ADC_STOP);
  156. a (XCTL1);
  157. a (OPEN);
  158. a (MSFMTSEL);
  159. a (M_SBB);
  160. a (DAC_SYNC);
  161. a (CCB_INTRM);
  162. a (M_CB);
  163. a (XCTL0);
  164. a (BREQ);
  165. a (DAC1_EN);
  166. a (DAC2_EN);
  167. a (ADC_EN);
  168. a (UART_EN);
  169. a (JYSTK_EN);
  170. a (CDC_EN);
  171. a (SERR_DIS);
  172. #undef a
  173. AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
  174. (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
  175. DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
  176. dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
  177. buf);
  178. }
  179. static void print_sctl (uint32_t val)
  180. {
  181. static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
  182. char buf[1024];
  183. buf[0] = '\0';
  184. #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
  185. #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
  186. b (R1LOOPSEL);
  187. b (P2LOOPSEL);
  188. b (P1LOOPSEL);
  189. a (P2PAUSE);
  190. a (P1PAUSE);
  191. a (R1INTEN);
  192. a (P2INTEN);
  193. a (P1INTEN);
  194. a (P1SCTRLD);
  195. a (P2DACSEN);
  196. if (buf[0]) {
  197. strcat (buf, "\n ");
  198. }
  199. else {
  200. buf[0] = ' ';
  201. buf[1] = '\0';
  202. }
  203. #undef b
  204. #undef a
  205. AUD_log ("es1370",
  206. "%s"
  207. "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
  208. buf,
  209. (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
  210. (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
  211. fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
  212. fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
  213. fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
  214. );
  215. }
  216. #else
  217. #define ldebug(...)
  218. #define print_ctl(...)
  219. #define print_sctl(...)
  220. #endif
  221. #ifdef VERBOSE_ES1370
  222. #define dolog(...) AUD_log ("es1370", __VA_ARGS__)
  223. #else
  224. #define dolog(...)
  225. #endif
  226. #ifndef SILENT_ES1370
  227. #define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__)
  228. #else
  229. #define lwarn(...)
  230. #endif
  231. struct chan {
  232. uint32_t shift;
  233. uint32_t leftover;
  234. uint32_t scount;
  235. uint32_t frame_addr;
  236. uint32_t frame_cnt;
  237. };
  238. typedef struct ES1370State {
  239. PCIDevice *pci_dev;
  240. QEMUSoundCard card;
  241. struct chan chan[NB_CHANNELS];
  242. SWVoiceOut *dac_voice[2];
  243. SWVoiceIn *adc_voice;
  244. uint32_t ctl;
  245. uint32_t status;
  246. uint32_t mempage;
  247. uint32_t codec;
  248. uint32_t sctl;
  249. } ES1370State;
  250. typedef struct PCIES1370State {
  251. PCIDevice dev;
  252. ES1370State es1370;
  253. } PCIES1370State;
  254. struct chan_bits {
  255. uint32_t ctl_en;
  256. uint32_t stat_int;
  257. uint32_t sctl_pause;
  258. uint32_t sctl_inten;
  259. uint32_t sctl_fmt;
  260. uint32_t sctl_sh_fmt;
  261. uint32_t sctl_loopsel;
  262. void (*calc_freq) (ES1370State *s, uint32_t ctl,
  263. uint32_t *old_freq, uint32_t *new_freq);
  264. };
  265. static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
  266. uint32_t *old_freq, uint32_t *new_freq);
  267. static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
  268. uint32_t *old_freq,
  269. uint32_t *new_freq);
  270. static const struct chan_bits es1370_chan_bits[] = {
  271. {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
  272. SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
  273. es1370_dac1_calc_freq},
  274. {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
  275. SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
  276. es1370_dac2_and_adc_calc_freq},
  277. {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
  278. SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
  279. es1370_dac2_and_adc_calc_freq}
  280. };
  281. static void es1370_update_status (ES1370State *s, uint32_t new_status)
  282. {
  283. uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
  284. if (level) {
  285. s->status = new_status | STAT_INTR;
  286. }
  287. else {
  288. s->status = new_status & ~STAT_INTR;
  289. }
  290. qemu_set_irq(s->pci_dev->irq[0], !!level);
  291. }
  292. static void es1370_reset (ES1370State *s)
  293. {
  294. size_t i;
  295. s->ctl = 1;
  296. s->status = 0x60;
  297. s->mempage = 0;
  298. s->codec = 0;
  299. s->sctl = 0;
  300. for (i = 0; i < NB_CHANNELS; ++i) {
  301. struct chan *d = &s->chan[i];
  302. d->scount = 0;
  303. d->leftover = 0;
  304. if (i == ADC_CHANNEL) {
  305. AUD_close_in (&s->card, s->adc_voice);
  306. s->adc_voice = NULL;
  307. }
  308. else {
  309. AUD_close_out (&s->card, s->dac_voice[i]);
  310. s->dac_voice[i] = NULL;
  311. }
  312. }
  313. qemu_irq_lower(s->pci_dev->irq[0]);
  314. }
  315. static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
  316. {
  317. uint32_t new_status = s->status;
  318. if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
  319. new_status &= ~STAT_DAC1;
  320. }
  321. if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
  322. new_status &= ~STAT_DAC2;
  323. }
  324. if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
  325. new_status &= ~STAT_ADC;
  326. }
  327. if (new_status != s->status) {
  328. es1370_update_status (s, new_status);
  329. }
  330. }
  331. static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
  332. uint32_t *old_freq, uint32_t *new_freq)
  333. {
  334. *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
  335. *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
  336. }
  337. static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
  338. uint32_t *old_freq,
  339. uint32_t *new_freq)
  340. {
  341. uint32_t old_pclkdiv, new_pclkdiv;
  342. new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
  343. old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
  344. *new_freq = DAC2_DIVTOSR (new_pclkdiv);
  345. *old_freq = DAC2_DIVTOSR (old_pclkdiv);
  346. }
  347. static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
  348. {
  349. size_t i;
  350. uint32_t old_freq, new_freq, old_fmt, new_fmt;
  351. for (i = 0; i < NB_CHANNELS; ++i) {
  352. struct chan *d = &s->chan[i];
  353. const struct chan_bits *b = &es1370_chan_bits[i];
  354. new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
  355. old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
  356. b->calc_freq (s, ctl, &old_freq, &new_freq);
  357. if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
  358. d->shift = (new_fmt & 1) + (new_fmt >> 1);
  359. ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
  360. i,
  361. new_freq,
  362. 1 << (new_fmt & 1),
  363. (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
  364. d->shift);
  365. if (new_freq) {
  366. struct audsettings as;
  367. as.freq = new_freq;
  368. as.nchannels = 1 << (new_fmt & 1);
  369. as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8;
  370. as.endianness = 0;
  371. if (i == ADC_CHANNEL) {
  372. s->adc_voice =
  373. AUD_open_in (
  374. &s->card,
  375. s->adc_voice,
  376. "es1370.adc",
  377. s,
  378. es1370_adc_callback,
  379. &as
  380. );
  381. }
  382. else {
  383. s->dac_voice[i] =
  384. AUD_open_out (
  385. &s->card,
  386. s->dac_voice[i],
  387. i ? "es1370.dac2" : "es1370.dac1",
  388. s,
  389. i ? es1370_dac2_callback : es1370_dac1_callback,
  390. &as
  391. );
  392. }
  393. }
  394. }
  395. if (((ctl ^ s->ctl) & b->ctl_en)
  396. || ((sctl ^ s->sctl) & b->sctl_pause)) {
  397. int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
  398. if (i == ADC_CHANNEL) {
  399. AUD_set_active_in (s->adc_voice, on);
  400. }
  401. else {
  402. AUD_set_active_out (s->dac_voice[i], on);
  403. }
  404. }
  405. }
  406. s->ctl = ctl;
  407. s->sctl = sctl;
  408. }
  409. static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
  410. {
  411. addr &= 0xff;
  412. if (addr >= 0x30 && addr <= 0x3f)
  413. addr |= s->mempage << 8;
  414. return addr;
  415. }
  416. IO_WRITE_PROTO (es1370_writeb)
  417. {
  418. ES1370State *s = opaque;
  419. uint32_t shift, mask;
  420. addr = es1370_fixup (s, addr);
  421. switch (addr) {
  422. case ES1370_REG_CONTROL:
  423. case ES1370_REG_CONTROL + 1:
  424. case ES1370_REG_CONTROL + 2:
  425. case ES1370_REG_CONTROL + 3:
  426. shift = (addr - ES1370_REG_CONTROL) << 3;
  427. mask = 0xff << shift;
  428. val = (s->ctl & ~mask) | ((val & 0xff) << shift);
  429. es1370_update_voices (s, val, s->sctl);
  430. print_ctl (val);
  431. break;
  432. case ES1370_REG_MEMPAGE:
  433. s->mempage = val;
  434. break;
  435. case ES1370_REG_SERIAL_CONTROL:
  436. case ES1370_REG_SERIAL_CONTROL + 1:
  437. case ES1370_REG_SERIAL_CONTROL + 2:
  438. case ES1370_REG_SERIAL_CONTROL + 3:
  439. shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
  440. mask = 0xff << shift;
  441. val = (s->sctl & ~mask) | ((val & 0xff) << shift);
  442. es1370_maybe_lower_irq (s, val);
  443. es1370_update_voices (s, s->ctl, val);
  444. print_sctl (val);
  445. break;
  446. default:
  447. lwarn ("writeb %#x <- %#x\n", addr, val);
  448. break;
  449. }
  450. }
  451. IO_WRITE_PROTO (es1370_writew)
  452. {
  453. ES1370State *s = opaque;
  454. addr = es1370_fixup (s, addr);
  455. uint32_t shift, mask;
  456. struct chan *d = &s->chan[0];
  457. switch (addr) {
  458. case ES1370_REG_CODEC:
  459. dolog ("ignored codec write address %#x, data %#x\n",
  460. (val >> 8) & 0xff, val & 0xff);
  461. s->codec = val;
  462. break;
  463. case ES1370_REG_CONTROL:
  464. case ES1370_REG_CONTROL + 2:
  465. shift = (addr != ES1370_REG_CONTROL) << 4;
  466. mask = 0xffff << shift;
  467. val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
  468. es1370_update_voices (s, val, s->sctl);
  469. print_ctl (val);
  470. break;
  471. case ES1370_REG_ADC_SCOUNT:
  472. d++;
  473. case ES1370_REG_DAC2_SCOUNT:
  474. d++;
  475. case ES1370_REG_DAC1_SCOUNT:
  476. d->scount = (d->scount & ~0xffff) | (val & 0xffff);
  477. break;
  478. default:
  479. lwarn ("writew %#x <- %#x\n", addr, val);
  480. break;
  481. }
  482. }
  483. IO_WRITE_PROTO (es1370_writel)
  484. {
  485. ES1370State *s = opaque;
  486. struct chan *d = &s->chan[0];
  487. addr = es1370_fixup (s, addr);
  488. switch (addr) {
  489. case ES1370_REG_CONTROL:
  490. es1370_update_voices (s, val, s->sctl);
  491. print_ctl (val);
  492. break;
  493. case ES1370_REG_MEMPAGE:
  494. s->mempage = val & 0xf;
  495. break;
  496. case ES1370_REG_SERIAL_CONTROL:
  497. es1370_maybe_lower_irq (s, val);
  498. es1370_update_voices (s, s->ctl, val);
  499. print_sctl (val);
  500. break;
  501. case ES1370_REG_ADC_SCOUNT:
  502. d++;
  503. case ES1370_REG_DAC2_SCOUNT:
  504. d++;
  505. case ES1370_REG_DAC1_SCOUNT:
  506. d->scount = (val & 0xffff) | (d->scount & ~0xffff);
  507. ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
  508. d - &s->chan[0], val >> 16, (val & 0xffff));
  509. break;
  510. case ES1370_REG_ADC_FRAMEADR:
  511. d++;
  512. case ES1370_REG_DAC2_FRAMEADR:
  513. d++;
  514. case ES1370_REG_DAC1_FRAMEADR:
  515. d->frame_addr = val;
  516. ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
  517. break;
  518. case ES1370_REG_PHANTOM_FRAMECNT:
  519. lwarn ("writing to phantom frame count %#x\n", val);
  520. break;
  521. case ES1370_REG_PHANTOM_FRAMEADR:
  522. lwarn ("writing to phantom frame address %#x\n", val);
  523. break;
  524. case ES1370_REG_ADC_FRAMECNT:
  525. d++;
  526. case ES1370_REG_DAC2_FRAMECNT:
  527. d++;
  528. case ES1370_REG_DAC1_FRAMECNT:
  529. d->frame_cnt = val;
  530. d->leftover = 0;
  531. ldebug ("chan %d frame count %d, buffer size %d\n",
  532. d - &s->chan[0], val >> 16, val & 0xffff);
  533. break;
  534. default:
  535. lwarn ("writel %#x <- %#x\n", addr, val);
  536. break;
  537. }
  538. }
  539. IO_READ_PROTO (es1370_readb)
  540. {
  541. ES1370State *s = opaque;
  542. uint32_t val;
  543. addr = es1370_fixup (s, addr);
  544. switch (addr) {
  545. case 0x1b: /* Legacy */
  546. lwarn ("Attempt to read from legacy register\n");
  547. val = 5;
  548. break;
  549. case ES1370_REG_MEMPAGE:
  550. val = s->mempage;
  551. break;
  552. case ES1370_REG_CONTROL + 0:
  553. case ES1370_REG_CONTROL + 1:
  554. case ES1370_REG_CONTROL + 2:
  555. case ES1370_REG_CONTROL + 3:
  556. val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
  557. break;
  558. case ES1370_REG_STATUS + 0:
  559. case ES1370_REG_STATUS + 1:
  560. case ES1370_REG_STATUS + 2:
  561. case ES1370_REG_STATUS + 3:
  562. val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
  563. break;
  564. default:
  565. val = ~0;
  566. lwarn ("readb %#x -> %#x\n", addr, val);
  567. break;
  568. }
  569. return val;
  570. }
  571. IO_READ_PROTO (es1370_readw)
  572. {
  573. ES1370State *s = opaque;
  574. struct chan *d = &s->chan[0];
  575. uint32_t val;
  576. addr = es1370_fixup (s, addr);
  577. switch (addr) {
  578. case ES1370_REG_ADC_SCOUNT + 2:
  579. d++;
  580. case ES1370_REG_DAC2_SCOUNT + 2:
  581. d++;
  582. case ES1370_REG_DAC1_SCOUNT + 2:
  583. val = d->scount >> 16;
  584. break;
  585. case ES1370_REG_ADC_FRAMECNT:
  586. d++;
  587. case ES1370_REG_DAC2_FRAMECNT:
  588. d++;
  589. case ES1370_REG_DAC1_FRAMECNT:
  590. val = d->frame_cnt & 0xffff;
  591. break;
  592. case ES1370_REG_ADC_FRAMECNT + 2:
  593. d++;
  594. case ES1370_REG_DAC2_FRAMECNT + 2:
  595. d++;
  596. case ES1370_REG_DAC1_FRAMECNT + 2:
  597. val = d->frame_cnt >> 16;
  598. break;
  599. default:
  600. val = ~0;
  601. lwarn ("readw %#x -> %#x\n", addr, val);
  602. break;
  603. }
  604. return val;
  605. }
  606. IO_READ_PROTO (es1370_readl)
  607. {
  608. ES1370State *s = opaque;
  609. uint32_t val;
  610. struct chan *d = &s->chan[0];
  611. addr = es1370_fixup (s, addr);
  612. switch (addr) {
  613. case ES1370_REG_CONTROL:
  614. val = s->ctl;
  615. break;
  616. case ES1370_REG_STATUS:
  617. val = s->status;
  618. break;
  619. case ES1370_REG_MEMPAGE:
  620. val = s->mempage;
  621. break;
  622. case ES1370_REG_CODEC:
  623. val = s->codec;
  624. break;
  625. case ES1370_REG_SERIAL_CONTROL:
  626. val = s->sctl;
  627. break;
  628. case ES1370_REG_ADC_SCOUNT:
  629. d++;
  630. case ES1370_REG_DAC2_SCOUNT:
  631. d++;
  632. case ES1370_REG_DAC1_SCOUNT:
  633. val = d->scount;
  634. #ifdef DEBUG_ES1370
  635. {
  636. uint32_t curr_count = d->scount >> 16;
  637. uint32_t count = d->scount & 0xffff;
  638. curr_count <<= d->shift;
  639. count <<= d->shift;
  640. dolog ("read scount curr %d, total %d\n", curr_count, count);
  641. }
  642. #endif
  643. break;
  644. case ES1370_REG_ADC_FRAMECNT:
  645. d++;
  646. case ES1370_REG_DAC2_FRAMECNT:
  647. d++;
  648. case ES1370_REG_DAC1_FRAMECNT:
  649. val = d->frame_cnt;
  650. #ifdef DEBUG_ES1370
  651. {
  652. uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
  653. uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
  654. if (curr > size)
  655. dolog ("read framecnt curr %d, size %d %d\n", curr, size,
  656. curr > size);
  657. }
  658. #endif
  659. break;
  660. case ES1370_REG_ADC_FRAMEADR:
  661. d++;
  662. case ES1370_REG_DAC2_FRAMEADR:
  663. d++;
  664. case ES1370_REG_DAC1_FRAMEADR:
  665. val = d->frame_addr;
  666. break;
  667. case ES1370_REG_PHANTOM_FRAMECNT:
  668. val = ~0U;
  669. lwarn ("reading from phantom frame count\n");
  670. break;
  671. case ES1370_REG_PHANTOM_FRAMEADR:
  672. val = ~0U;
  673. lwarn ("reading from phantom frame address\n");
  674. break;
  675. default:
  676. val = ~0U;
  677. lwarn ("readl %#x -> %#x\n", addr, val);
  678. break;
  679. }
  680. return val;
  681. }
  682. static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
  683. int max, int *irq)
  684. {
  685. uint8_t tmpbuf[4096];
  686. uint32_t addr = d->frame_addr;
  687. int sc = d->scount & 0xffff;
  688. int csc = d->scount >> 16;
  689. int csc_bytes = (csc + 1) << d->shift;
  690. int cnt = d->frame_cnt >> 16;
  691. int size = d->frame_cnt & 0xffff;
  692. int left = ((size - cnt + 1) << 2) + d->leftover;
  693. int transfered = 0;
  694. int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
  695. int index = d - &s->chan[0];
  696. addr += (cnt << 2) + d->leftover;
  697. if (index == ADC_CHANNEL) {
  698. while (temp) {
  699. int acquired, to_copy;
  700. to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
  701. acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
  702. if (!acquired)
  703. break;
  704. cpu_physical_memory_write (addr, tmpbuf, acquired);
  705. temp -= acquired;
  706. addr += acquired;
  707. transfered += acquired;
  708. }
  709. }
  710. else {
  711. SWVoiceOut *voice = s->dac_voice[index];
  712. while (temp) {
  713. int copied, to_copy;
  714. to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
  715. cpu_physical_memory_read (addr, tmpbuf, to_copy);
  716. copied = AUD_write (voice, tmpbuf, to_copy);
  717. if (!copied)
  718. break;
  719. temp -= copied;
  720. addr += copied;
  721. transfered += copied;
  722. }
  723. }
  724. if (csc_bytes == transfered) {
  725. *irq = 1;
  726. d->scount = sc | (sc << 16);
  727. ldebug ("sc = %d, rate = %f\n",
  728. (sc + 1) << d->shift,
  729. (sc + 1) / (double) 44100);
  730. }
  731. else {
  732. *irq = 0;
  733. d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16);
  734. }
  735. cnt += (transfered + d->leftover) >> 2;
  736. if (s->sctl & loop_sel) {
  737. /* Bah, how stupid is that having a 0 represent true value?
  738. i just spent few hours on this shit */
  739. AUD_log ("es1370: warning", "non looping mode\n");
  740. }
  741. else {
  742. d->frame_cnt = size;
  743. if ((uint32_t) cnt <= d->frame_cnt)
  744. d->frame_cnt |= cnt << 16;
  745. }
  746. d->leftover = (transfered + d->leftover) & 3;
  747. }
  748. static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
  749. {
  750. uint32_t new_status = s->status;
  751. int max_bytes, irq;
  752. struct chan *d = &s->chan[chan];
  753. const struct chan_bits *b = &es1370_chan_bits[chan];
  754. if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
  755. return;
  756. }
  757. max_bytes = free_or_avail;
  758. max_bytes &= ~((1 << d->shift) - 1);
  759. if (!max_bytes) {
  760. return;
  761. }
  762. es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
  763. if (irq) {
  764. if (s->sctl & b->sctl_inten) {
  765. new_status |= b->stat_int;
  766. }
  767. }
  768. if (new_status != s->status) {
  769. es1370_update_status (s, new_status);
  770. }
  771. }
  772. static void es1370_dac1_callback (void *opaque, int free)
  773. {
  774. ES1370State *s = opaque;
  775. es1370_run_channel (s, DAC1_CHANNEL, free);
  776. }
  777. static void es1370_dac2_callback (void *opaque, int free)
  778. {
  779. ES1370State *s = opaque;
  780. es1370_run_channel (s, DAC2_CHANNEL, free);
  781. }
  782. static void es1370_adc_callback (void *opaque, int avail)
  783. {
  784. ES1370State *s = opaque;
  785. es1370_run_channel (s, ADC_CHANNEL, avail);
  786. }
  787. static void es1370_map (PCIDevice *pci_dev, int region_num,
  788. uint32_t addr, uint32_t size, int type)
  789. {
  790. PCIES1370State *d = (PCIES1370State *) pci_dev;
  791. ES1370State *s = &d->es1370;
  792. (void) region_num;
  793. (void) size;
  794. (void) type;
  795. register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
  796. register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
  797. register_ioport_write (addr, 0x40, 4, es1370_writel, s);
  798. register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
  799. register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
  800. register_ioport_read (addr, 0x40, 4, es1370_readl, s);
  801. }
  802. static void es1370_save (QEMUFile *f, void *opaque)
  803. {
  804. ES1370State *s = opaque;
  805. size_t i;
  806. pci_device_save (s->pci_dev, f);
  807. for (i = 0; i < NB_CHANNELS; ++i) {
  808. struct chan *d = &s->chan[i];
  809. qemu_put_be32s (f, &d->shift);
  810. qemu_put_be32s (f, &d->leftover);
  811. qemu_put_be32s (f, &d->scount);
  812. qemu_put_be32s (f, &d->frame_addr);
  813. qemu_put_be32s (f, &d->frame_cnt);
  814. }
  815. qemu_put_be32s (f, &s->ctl);
  816. qemu_put_be32s (f, &s->status);
  817. qemu_put_be32s (f, &s->mempage);
  818. qemu_put_be32s (f, &s->codec);
  819. qemu_put_be32s (f, &s->sctl);
  820. }
  821. static int es1370_load (QEMUFile *f, void *opaque, int version_id)
  822. {
  823. int ret;
  824. uint32_t ctl, sctl;
  825. ES1370State *s = opaque;
  826. size_t i;
  827. if (version_id != 2)
  828. return -EINVAL;
  829. ret = pci_device_load (s->pci_dev, f);
  830. if (ret)
  831. return ret;
  832. for (i = 0; i < NB_CHANNELS; ++i) {
  833. struct chan *d = &s->chan[i];
  834. qemu_get_be32s (f, &d->shift);
  835. qemu_get_be32s (f, &d->leftover);
  836. qemu_get_be32s (f, &d->scount);
  837. qemu_get_be32s (f, &d->frame_addr);
  838. qemu_get_be32s (f, &d->frame_cnt);
  839. if (i == ADC_CHANNEL) {
  840. if (s->adc_voice) {
  841. AUD_close_in (&s->card, s->adc_voice);
  842. s->adc_voice = NULL;
  843. }
  844. }
  845. else {
  846. if (s->dac_voice[i]) {
  847. AUD_close_out (&s->card, s->dac_voice[i]);
  848. s->dac_voice[i] = NULL;
  849. }
  850. }
  851. }
  852. qemu_get_be32s (f, &ctl);
  853. qemu_get_be32s (f, &s->status);
  854. qemu_get_be32s (f, &s->mempage);
  855. qemu_get_be32s (f, &s->codec);
  856. qemu_get_be32s (f, &sctl);
  857. s->ctl = 0;
  858. s->sctl = 0;
  859. es1370_update_voices (s, ctl, sctl);
  860. return 0;
  861. }
  862. static void es1370_on_reset (void *opaque)
  863. {
  864. ES1370State *s = opaque;
  865. es1370_reset (s);
  866. }
  867. int es1370_init (PCIBus *bus, AudioState *audio)
  868. {
  869. PCIES1370State *d;
  870. ES1370State *s;
  871. uint8_t *c;
  872. if (!bus) {
  873. dolog ("No PCI bus\n");
  874. return -1;
  875. }
  876. if (!audio) {
  877. dolog ("No audio state\n");
  878. return -1;
  879. }
  880. d = (PCIES1370State *) pci_register_device (bus, "ES1370",
  881. sizeof (PCIES1370State),
  882. -1, NULL, NULL);
  883. if (!d) {
  884. AUD_log (NULL, "Failed to register PCI device for ES1370\n");
  885. return -1;
  886. }
  887. c = d->dev.config;
  888. pci_config_set_vendor_id(c, PCI_VENDOR_ID_ENSONIQ);
  889. pci_config_set_device_id(c, PCI_DEVICE_ID_ENSONIQ_ES1370);
  890. c[0x07] = 2 << 1;
  891. pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO);
  892. #if 1
  893. c[0x2c] = 0x42;
  894. c[0x2d] = 0x49;
  895. c[0x2e] = 0x4c;
  896. c[0x2f] = 0x4c;
  897. #else
  898. c[0x2c] = 0x74;
  899. c[0x2d] = 0x12;
  900. c[0x2e] = 0x71;
  901. c[0x2f] = 0x13;
  902. c[0x34] = 0xdc;
  903. c[0x3c] = 10;
  904. c[0xdc] = 0x00;
  905. #endif
  906. c[0x3d] = 1;
  907. c[0x3e] = 0x0c;
  908. c[0x3f] = 0x80;
  909. s = &d->es1370;
  910. s->pci_dev = &d->dev;
  911. pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
  912. register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
  913. qemu_register_reset (es1370_on_reset, s);
  914. AUD_register_card (audio, "es1370", &s->card);
  915. es1370_reset (s);
  916. return 0;
  917. }