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cs4231a.c 20 KB

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  1. /*
  2. * QEMU Crystal CS4231 audio chip emulation
  3. *
  4. * Copyright (c) 2006 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "audiodev.h"
  26. #include "audio/audio.h"
  27. #include "isa.h"
  28. #include "qemu-timer.h"
  29. /*
  30. Missing features:
  31. ADC
  32. Loopback
  33. Timer
  34. ADPCM
  35. More...
  36. */
  37. /* #define DEBUG */
  38. /* #define DEBUG_XLAW */
  39. static struct {
  40. int irq;
  41. int dma;
  42. int port;
  43. int aci_counter;
  44. } conf = {9, 3, 0x534, 1};
  45. #ifdef DEBUG
  46. #define dolog(...) AUD_log ("cs4231a", __VA_ARGS__)
  47. #else
  48. #define dolog(...)
  49. #endif
  50. #define lwarn(...) AUD_log ("cs4231a", "warning: " __VA_ARGS__)
  51. #define lerr(...) AUD_log ("cs4231a", "error: " __VA_ARGS__)
  52. #define CS_REGS 16
  53. #define CS_DREGS 32
  54. typedef struct CSState {
  55. QEMUSoundCard card;
  56. qemu_irq *pic;
  57. uint32_t regs[CS_REGS];
  58. uint8_t dregs[CS_DREGS];
  59. int irq;
  60. int dma;
  61. int port;
  62. int shift;
  63. int dma_running;
  64. int audio_free;
  65. int transferred;
  66. int aci_counter;
  67. SWVoiceOut *voice;
  68. int16_t *tab;
  69. } CSState;
  70. #define IO_READ_PROTO(name) \
  71. static uint32_t name (void *opaque, uint32_t addr)
  72. #define IO_WRITE_PROTO(name) \
  73. static void name (void *opaque, uint32_t addr, uint32_t val)
  74. #define GET_SADDR(addr) (addr & 3)
  75. #define MODE2 (1 << 6)
  76. #define MCE (1 << 6)
  77. #define PMCE (1 << 4)
  78. #define CMCE (1 << 5)
  79. #define TE (1 << 6)
  80. #define PEN (1 << 0)
  81. #define INT (1 << 0)
  82. #define IEN (1 << 1)
  83. #define PPIO (1 << 6)
  84. #define PI (1 << 4)
  85. #define CI (1 << 5)
  86. #define TI (1 << 6)
  87. enum {
  88. Index_Address,
  89. Index_Data,
  90. Status,
  91. PIO_Data
  92. };
  93. enum {
  94. Left_ADC_Input_Control,
  95. Right_ADC_Input_Control,
  96. Left_AUX1_Input_Control,
  97. Right_AUX1_Input_Control,
  98. Left_AUX2_Input_Control,
  99. Right_AUX2_Input_Control,
  100. Left_DAC_Output_Control,
  101. Right_DAC_Output_Control,
  102. FS_And_Playback_Data_Format,
  103. Interface_Configuration,
  104. Pin_Control,
  105. Error_Status_And_Initialization,
  106. MODE_And_ID,
  107. Loopback_Control,
  108. Playback_Upper_Base_Count,
  109. Playback_Lower_Base_Count,
  110. Alternate_Feature_Enable_I,
  111. Alternate_Feature_Enable_II,
  112. Left_Line_Input_Control,
  113. Right_Line_Input_Control,
  114. Timer_Low_Base,
  115. Timer_High_Base,
  116. RESERVED,
  117. Alternate_Feature_Enable_III,
  118. Alternate_Feature_Status,
  119. Version_Chip_ID,
  120. Mono_Input_And_Output_Control,
  121. RESERVED_2,
  122. Capture_Data_Format,
  123. RESERVED_3,
  124. Capture_Upper_Base_Count,
  125. Capture_Lower_Base_Count
  126. };
  127. static int freqs[2][8] = {
  128. { 8000, 16000, 27420, 32000, -1, -1, 48000, 9000 },
  129. { 5510, 11025, 18900, 22050, 37800, 44100, 33075, 6620 }
  130. };
  131. /* Tables courtesy http://hazelware.luggle.com/tutorials/mulawcompression.html */
  132. static int16_t MuLawDecompressTable[256] =
  133. {
  134. -32124,-31100,-30076,-29052,-28028,-27004,-25980,-24956,
  135. -23932,-22908,-21884,-20860,-19836,-18812,-17788,-16764,
  136. -15996,-15484,-14972,-14460,-13948,-13436,-12924,-12412,
  137. -11900,-11388,-10876,-10364, -9852, -9340, -8828, -8316,
  138. -7932, -7676, -7420, -7164, -6908, -6652, -6396, -6140,
  139. -5884, -5628, -5372, -5116, -4860, -4604, -4348, -4092,
  140. -3900, -3772, -3644, -3516, -3388, -3260, -3132, -3004,
  141. -2876, -2748, -2620, -2492, -2364, -2236, -2108, -1980,
  142. -1884, -1820, -1756, -1692, -1628, -1564, -1500, -1436,
  143. -1372, -1308, -1244, -1180, -1116, -1052, -988, -924,
  144. -876, -844, -812, -780, -748, -716, -684, -652,
  145. -620, -588, -556, -524, -492, -460, -428, -396,
  146. -372, -356, -340, -324, -308, -292, -276, -260,
  147. -244, -228, -212, -196, -180, -164, -148, -132,
  148. -120, -112, -104, -96, -88, -80, -72, -64,
  149. -56, -48, -40, -32, -24, -16, -8, 0,
  150. 32124, 31100, 30076, 29052, 28028, 27004, 25980, 24956,
  151. 23932, 22908, 21884, 20860, 19836, 18812, 17788, 16764,
  152. 15996, 15484, 14972, 14460, 13948, 13436, 12924, 12412,
  153. 11900, 11388, 10876, 10364, 9852, 9340, 8828, 8316,
  154. 7932, 7676, 7420, 7164, 6908, 6652, 6396, 6140,
  155. 5884, 5628, 5372, 5116, 4860, 4604, 4348, 4092,
  156. 3900, 3772, 3644, 3516, 3388, 3260, 3132, 3004,
  157. 2876, 2748, 2620, 2492, 2364, 2236, 2108, 1980,
  158. 1884, 1820, 1756, 1692, 1628, 1564, 1500, 1436,
  159. 1372, 1308, 1244, 1180, 1116, 1052, 988, 924,
  160. 876, 844, 812, 780, 748, 716, 684, 652,
  161. 620, 588, 556, 524, 492, 460, 428, 396,
  162. 372, 356, 340, 324, 308, 292, 276, 260,
  163. 244, 228, 212, 196, 180, 164, 148, 132,
  164. 120, 112, 104, 96, 88, 80, 72, 64,
  165. 56, 48, 40, 32, 24, 16, 8, 0
  166. };
  167. static int16_t ALawDecompressTable[256] =
  168. {
  169. -5504, -5248, -6016, -5760, -4480, -4224, -4992, -4736,
  170. -7552, -7296, -8064, -7808, -6528, -6272, -7040, -6784,
  171. -2752, -2624, -3008, -2880, -2240, -2112, -2496, -2368,
  172. -3776, -3648, -4032, -3904, -3264, -3136, -3520, -3392,
  173. -22016,-20992,-24064,-23040,-17920,-16896,-19968,-18944,
  174. -30208,-29184,-32256,-31232,-26112,-25088,-28160,-27136,
  175. -11008,-10496,-12032,-11520,-8960, -8448, -9984, -9472,
  176. -15104,-14592,-16128,-15616,-13056,-12544,-14080,-13568,
  177. -344, -328, -376, -360, -280, -264, -312, -296,
  178. -472, -456, -504, -488, -408, -392, -440, -424,
  179. -88, -72, -120, -104, -24, -8, -56, -40,
  180. -216, -200, -248, -232, -152, -136, -184, -168,
  181. -1376, -1312, -1504, -1440, -1120, -1056, -1248, -1184,
  182. -1888, -1824, -2016, -1952, -1632, -1568, -1760, -1696,
  183. -688, -656, -752, -720, -560, -528, -624, -592,
  184. -944, -912, -1008, -976, -816, -784, -880, -848,
  185. 5504, 5248, 6016, 5760, 4480, 4224, 4992, 4736,
  186. 7552, 7296, 8064, 7808, 6528, 6272, 7040, 6784,
  187. 2752, 2624, 3008, 2880, 2240, 2112, 2496, 2368,
  188. 3776, 3648, 4032, 3904, 3264, 3136, 3520, 3392,
  189. 22016, 20992, 24064, 23040, 17920, 16896, 19968, 18944,
  190. 30208, 29184, 32256, 31232, 26112, 25088, 28160, 27136,
  191. 11008, 10496, 12032, 11520, 8960, 8448, 9984, 9472,
  192. 15104, 14592, 16128, 15616, 13056, 12544, 14080, 13568,
  193. 344, 328, 376, 360, 280, 264, 312, 296,
  194. 472, 456, 504, 488, 408, 392, 440, 424,
  195. 88, 72, 120, 104, 24, 8, 56, 40,
  196. 216, 200, 248, 232, 152, 136, 184, 168,
  197. 1376, 1312, 1504, 1440, 1120, 1056, 1248, 1184,
  198. 1888, 1824, 2016, 1952, 1632, 1568, 1760, 1696,
  199. 688, 656, 752, 720, 560, 528, 624, 592,
  200. 944, 912, 1008, 976, 816, 784, 880, 848
  201. };
  202. static void cs_reset(void *opaque)
  203. {
  204. CSState *s = opaque;
  205. s->regs[Index_Address] = 0x40;
  206. s->regs[Index_Data] = 0x00;
  207. s->regs[Status] = 0x00;
  208. s->regs[PIO_Data] = 0x00;
  209. s->dregs[Left_ADC_Input_Control] = 0x00;
  210. s->dregs[Right_ADC_Input_Control] = 0x00;
  211. s->dregs[Left_AUX1_Input_Control] = 0x88;
  212. s->dregs[Right_AUX1_Input_Control] = 0x88;
  213. s->dregs[Left_AUX2_Input_Control] = 0x88;
  214. s->dregs[Right_AUX2_Input_Control] = 0x88;
  215. s->dregs[Left_DAC_Output_Control] = 0x80;
  216. s->dregs[Right_DAC_Output_Control] = 0x80;
  217. s->dregs[FS_And_Playback_Data_Format] = 0x00;
  218. s->dregs[Interface_Configuration] = 0x08;
  219. s->dregs[Pin_Control] = 0x00;
  220. s->dregs[Error_Status_And_Initialization] = 0x00;
  221. s->dregs[MODE_And_ID] = 0x8a;
  222. s->dregs[Loopback_Control] = 0x00;
  223. s->dregs[Playback_Upper_Base_Count] = 0x00;
  224. s->dregs[Playback_Lower_Base_Count] = 0x00;
  225. s->dregs[Alternate_Feature_Enable_I] = 0x00;
  226. s->dregs[Alternate_Feature_Enable_II] = 0x00;
  227. s->dregs[Left_Line_Input_Control] = 0x88;
  228. s->dregs[Right_Line_Input_Control] = 0x88;
  229. s->dregs[Timer_Low_Base] = 0x00;
  230. s->dregs[Timer_High_Base] = 0x00;
  231. s->dregs[RESERVED] = 0x00;
  232. s->dregs[Alternate_Feature_Enable_III] = 0x00;
  233. s->dregs[Alternate_Feature_Status] = 0x00;
  234. s->dregs[Version_Chip_ID] = 0xa0;
  235. s->dregs[Mono_Input_And_Output_Control] = 0xa0;
  236. s->dregs[RESERVED_2] = 0x00;
  237. s->dregs[Capture_Data_Format] = 0x00;
  238. s->dregs[RESERVED_3] = 0x00;
  239. s->dregs[Capture_Upper_Base_Count] = 0x00;
  240. s->dregs[Capture_Lower_Base_Count] = 0x00;
  241. }
  242. static void cs_audio_callback (void *opaque, int free)
  243. {
  244. CSState *s = opaque;
  245. s->audio_free = free;
  246. }
  247. static void cs_reset_voices (CSState *s, uint32_t val)
  248. {
  249. int xtal;
  250. struct audsettings as;
  251. #ifdef DEBUG_XLAW
  252. if (val == 0 || val == 32)
  253. val = (1 << 4) | (1 << 5);
  254. #endif
  255. xtal = val & 1;
  256. as.freq = freqs[xtal][(val >> 1) & 7];
  257. if (as.freq == -1) {
  258. lerr ("unsupported frequency (val=%#x)\n", val);
  259. goto error;
  260. }
  261. as.nchannels = (val & (1 << 4)) ? 2 : 1;
  262. as.endianness = 0;
  263. s->tab = NULL;
  264. switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) {
  265. case 0:
  266. as.fmt = AUD_FMT_U8;
  267. s->shift = as.nchannels == 2;
  268. break;
  269. case 1:
  270. s->tab = MuLawDecompressTable;
  271. goto x_law;
  272. case 3:
  273. s->tab = ALawDecompressTable;
  274. x_law:
  275. as.fmt = AUD_FMT_S16;
  276. as.endianness = AUDIO_HOST_ENDIANNESS;
  277. s->shift = as.nchannels == 2;
  278. break;
  279. case 6:
  280. as.endianness = 1;
  281. case 2:
  282. as.fmt = AUD_FMT_S16;
  283. s->shift = as.nchannels;
  284. break;
  285. case 7:
  286. case 4:
  287. lerr ("attempt to use reserved format value (%#x)\n", val);
  288. goto error;
  289. case 5:
  290. lerr ("ADPCM 4 bit IMA compatible format is not supported\n");
  291. goto error;
  292. }
  293. s->voice = AUD_open_out (
  294. &s->card,
  295. s->voice,
  296. "cs4231a",
  297. s,
  298. cs_audio_callback,
  299. &as
  300. );
  301. if (s->dregs[Interface_Configuration] & PEN) {
  302. if (!s->dma_running) {
  303. DMA_hold_DREQ (s->dma);
  304. AUD_set_active_out (s->voice, 1);
  305. s->transferred = 0;
  306. }
  307. s->dma_running = 1;
  308. }
  309. else {
  310. if (s->dma_running) {
  311. DMA_release_DREQ (s->dma);
  312. AUD_set_active_out (s->voice, 0);
  313. }
  314. s->dma_running = 0;
  315. }
  316. return;
  317. error:
  318. if (s->dma_running) {
  319. DMA_release_DREQ (s->dma);
  320. AUD_set_active_out (s->voice, 0);
  321. }
  322. }
  323. IO_READ_PROTO (cs_read)
  324. {
  325. CSState *s = opaque;
  326. uint32_t saddr, iaddr, ret;
  327. saddr = GET_SADDR (addr);
  328. iaddr = ~0U;
  329. switch (saddr) {
  330. case Index_Address:
  331. ret = s->regs[saddr] & ~0x80;
  332. break;
  333. case Index_Data:
  334. if (!(s->dregs[MODE_And_ID] & MODE2))
  335. iaddr = s->regs[Index_Address] & 0x0f;
  336. else
  337. iaddr = s->regs[Index_Address] & 0x1f;
  338. ret = s->dregs[iaddr];
  339. if (iaddr == Error_Status_And_Initialization) {
  340. /* keep SEAL happy */
  341. if (s->aci_counter) {
  342. ret |= 1 << 5;
  343. s->aci_counter -= 1;
  344. }
  345. }
  346. break;
  347. default:
  348. ret = s->regs[saddr];
  349. break;
  350. }
  351. dolog ("read %d:%d -> %d\n", saddr, iaddr, ret);
  352. return ret;
  353. }
  354. IO_WRITE_PROTO (cs_write)
  355. {
  356. CSState *s = opaque;
  357. uint32_t saddr, iaddr;
  358. saddr = GET_SADDR (addr);
  359. switch (saddr) {
  360. case Index_Address:
  361. if (!(s->regs[Index_Address] & MCE) && (val & MCE)
  362. && (s->dregs[Interface_Configuration] & (3 << 3)))
  363. s->aci_counter = conf.aci_counter;
  364. s->regs[Index_Address] = val & ~(1 << 7);
  365. break;
  366. case Index_Data:
  367. if (!(s->dregs[MODE_And_ID] & MODE2))
  368. iaddr = s->regs[Index_Address] & 0x0f;
  369. else
  370. iaddr = s->regs[Index_Address] & 0x1f;
  371. switch (iaddr) {
  372. case RESERVED:
  373. case RESERVED_2:
  374. case RESERVED_3:
  375. lwarn ("attempt to write %#x to reserved indirect register %d\n",
  376. val, iaddr);
  377. break;
  378. case FS_And_Playback_Data_Format:
  379. if (s->regs[Index_Address] & MCE) {
  380. cs_reset_voices (s, val);
  381. }
  382. else {
  383. if (s->dregs[Alternate_Feature_Status] & PMCE) {
  384. val = (val & ~0x0f) | (s->dregs[iaddr] & 0x0f);
  385. cs_reset_voices (s, val);
  386. }
  387. else {
  388. lwarn ("[P]MCE(%#x, %#x) is not set, val=%#x\n",
  389. s->regs[Index_Address],
  390. s->dregs[Alternate_Feature_Status],
  391. val);
  392. break;
  393. }
  394. }
  395. s->dregs[iaddr] = val;
  396. break;
  397. case Interface_Configuration:
  398. val &= ~(1 << 5); /* D5 is reserved */
  399. s->dregs[iaddr] = val;
  400. if (val & PPIO) {
  401. lwarn ("PIO is not supported (%#x)\n", val);
  402. break;
  403. }
  404. if (val & PEN) {
  405. if (!s->dma_running) {
  406. cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
  407. }
  408. }
  409. else {
  410. if (s->dma_running) {
  411. DMA_release_DREQ (s->dma);
  412. AUD_set_active_out (s->voice, 0);
  413. s->dma_running = 0;
  414. }
  415. }
  416. break;
  417. case Error_Status_And_Initialization:
  418. lwarn ("attempt to write to read only register %d\n", iaddr);
  419. break;
  420. case MODE_And_ID:
  421. dolog ("val=%#x\n", val);
  422. if (val & MODE2)
  423. s->dregs[iaddr] |= MODE2;
  424. else
  425. s->dregs[iaddr] &= ~MODE2;
  426. break;
  427. case Alternate_Feature_Enable_I:
  428. if (val & TE)
  429. lerr ("timer is not yet supported\n");
  430. s->dregs[iaddr] = val;
  431. break;
  432. case Alternate_Feature_Status:
  433. if ((s->dregs[iaddr] & PI) && !(val & PI)) {
  434. /* XXX: TI CI */
  435. qemu_irq_lower (s->pic[s->irq]);
  436. s->regs[Status] &= ~INT;
  437. }
  438. s->dregs[iaddr] = val;
  439. break;
  440. case Version_Chip_ID:
  441. lwarn ("write to Version_Chip_ID register %#x\n", val);
  442. s->dregs[iaddr] = val;
  443. break;
  444. default:
  445. s->dregs[iaddr] = val;
  446. break;
  447. }
  448. dolog ("written value %#x to indirect register %d\n", val, iaddr);
  449. break;
  450. case Status:
  451. if (s->regs[Status] & INT) {
  452. qemu_irq_lower (s->pic[s->irq]);
  453. }
  454. s->regs[Status] &= ~INT;
  455. s->dregs[Alternate_Feature_Status] &= ~(PI | CI | TI);
  456. break;
  457. case PIO_Data:
  458. lwarn ("attempt to write value %#x to PIO register\n", val);
  459. break;
  460. }
  461. }
  462. static int cs_write_audio (CSState *s, int nchan, int dma_pos,
  463. int dma_len, int len)
  464. {
  465. int temp, net;
  466. uint8_t tmpbuf[4096];
  467. temp = len;
  468. net = 0;
  469. while (temp) {
  470. int left = dma_len - dma_pos;
  471. int copied;
  472. size_t to_copy;
  473. to_copy = audio_MIN (temp, left);
  474. if (to_copy > sizeof (tmpbuf)) {
  475. to_copy = sizeof (tmpbuf);
  476. }
  477. copied = DMA_read_memory (nchan, tmpbuf, dma_pos, to_copy);
  478. if (s->tab) {
  479. int i;
  480. int16_t linbuf[4096];
  481. for (i = 0; i < copied; ++i)
  482. linbuf[i] = s->tab[tmpbuf[i]];
  483. copied = AUD_write (s->voice, linbuf, copied << 1);
  484. copied >>= 1;
  485. }
  486. else {
  487. copied = AUD_write (s->voice, tmpbuf, copied);
  488. }
  489. temp -= copied;
  490. dma_pos = (dma_pos + copied) % dma_len;
  491. net += copied;
  492. if (!copied) {
  493. break;
  494. }
  495. }
  496. return net;
  497. }
  498. static int cs_dma_read (void *opaque, int nchan, int dma_pos, int dma_len)
  499. {
  500. CSState *s = opaque;
  501. int copy, written;
  502. int till = -1;
  503. copy = s->voice ? (s->audio_free >> (s->tab != NULL)) : dma_len;
  504. if (s->dregs[Pin_Control] & IEN) {
  505. till = (s->dregs[Playback_Lower_Base_Count]
  506. | (s->dregs[Playback_Upper_Base_Count] << 8)) << s->shift;
  507. till -= s->transferred;
  508. copy = audio_MIN (till, copy);
  509. }
  510. if ((copy <= 0) || (dma_len <= 0)) {
  511. return dma_pos;
  512. }
  513. written = cs_write_audio (s, nchan, dma_pos, dma_len, copy);
  514. dma_pos = (dma_pos + written) % dma_len;
  515. s->audio_free -= (written << (s->tab != NULL));
  516. if (written == till) {
  517. s->regs[Status] |= INT;
  518. s->dregs[Alternate_Feature_Status] |= PI;
  519. s->transferred = 0;
  520. qemu_irq_raise (s->pic[s->irq]);
  521. }
  522. else {
  523. s->transferred += written;
  524. }
  525. return dma_pos;
  526. }
  527. static void cs_save(QEMUFile *f, void *opaque)
  528. {
  529. CSState *s = opaque;
  530. unsigned int i;
  531. uint32_t val;
  532. for (i = 0; i < CS_REGS; i++)
  533. qemu_put_be32s(f, &s->regs[i]);
  534. qemu_put_buffer(f, s->dregs, CS_DREGS);
  535. val = s->dma_running; qemu_put_be32s(f, &val);
  536. val = s->audio_free; qemu_put_be32s(f, &val);
  537. val = s->transferred; qemu_put_be32s(f, &val);
  538. val = s->aci_counter; qemu_put_be32s(f, &val);
  539. }
  540. static int cs_load(QEMUFile *f, void *opaque, int version_id)
  541. {
  542. CSState *s = opaque;
  543. unsigned int i;
  544. uint32_t val, dma_running;
  545. if (version_id > 1)
  546. return -EINVAL;
  547. for (i = 0; i < CS_REGS; i++)
  548. qemu_get_be32s(f, &s->regs[i]);
  549. qemu_get_buffer(f, s->dregs, CS_DREGS);
  550. qemu_get_be32s(f, &dma_running);
  551. qemu_get_be32s(f, &val); s->audio_free = val;
  552. qemu_get_be32s(f, &val); s->transferred = val;
  553. qemu_get_be32s(f, &val); s->aci_counter = val;
  554. if (dma_running && (s->dregs[Interface_Configuration] & PEN))
  555. cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
  556. return 0;
  557. }
  558. int cs4231a_init (AudioState *audio, qemu_irq *pic)
  559. {
  560. int i;
  561. CSState *s;
  562. if (!audio) {
  563. lerr ("No audio state\n");
  564. return -1;
  565. }
  566. s = qemu_mallocz (sizeof (*s));
  567. s->pic = pic;
  568. s->irq = conf.irq;
  569. s->dma = conf.dma;
  570. s->port = conf.port;
  571. for (i = 0; i < 4; i++) {
  572. register_ioport_write (s->port + i, 1, 1, cs_write, s);
  573. register_ioport_read (s->port + i, 1, 1, cs_read, s);
  574. }
  575. DMA_register_channel (s->dma, cs_dma_read, s);
  576. register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);
  577. qemu_register_reset (cs_reset, s);
  578. cs_reset (s);
  579. AUD_register_card (audio,"cs4231a", &s->card);
  580. return 0;
  581. }