cs4231.c 4.5 KB

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  1. /*
  2. * QEMU Crystal CS4231 audio chip emulation
  3. *
  4. * Copyright (c) 2006 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "sun4m.h"
  26. /* debug CS4231 */
  27. //#define DEBUG_CS
  28. /*
  29. * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  30. */
  31. #define CS_SIZE 0x40
  32. #define CS_REGS 16
  33. #define CS_DREGS 32
  34. #define CS_MAXDREG (CS_DREGS - 1)
  35. typedef struct CSState {
  36. uint32_t regs[CS_REGS];
  37. uint8_t dregs[CS_DREGS];
  38. void *intctl;
  39. } CSState;
  40. #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  41. #define CS_VER 0xa0
  42. #define CS_CDC_VER 0x8a
  43. #ifdef DEBUG_CS
  44. #define DPRINTF(fmt, args...) \
  45. do { printf("CS: " fmt , ##args); } while (0)
  46. #else
  47. #define DPRINTF(fmt, args...)
  48. #endif
  49. static void cs_reset(void *opaque)
  50. {
  51. CSState *s = opaque;
  52. memset(s->regs, 0, CS_REGS * 4);
  53. memset(s->dregs, 0, CS_DREGS);
  54. s->dregs[12] = CS_CDC_VER;
  55. s->dregs[25] = CS_VER;
  56. }
  57. static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
  58. {
  59. CSState *s = opaque;
  60. uint32_t saddr, ret;
  61. saddr = addr >> 2;
  62. switch (saddr) {
  63. case 1:
  64. switch (CS_RAP(s)) {
  65. case 3: // Write only
  66. ret = 0;
  67. break;
  68. default:
  69. ret = s->dregs[CS_RAP(s)];
  70. break;
  71. }
  72. DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
  73. break;
  74. default:
  75. ret = s->regs[saddr];
  76. DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
  77. break;
  78. }
  79. return ret;
  80. }
  81. static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  82. {
  83. CSState *s = opaque;
  84. uint32_t saddr;
  85. saddr = addr >> 2;
  86. DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
  87. switch (saddr) {
  88. case 1:
  89. DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
  90. s->dregs[CS_RAP(s)], val);
  91. switch(CS_RAP(s)) {
  92. case 11:
  93. case 25: // Read only
  94. break;
  95. case 12:
  96. val &= 0x40;
  97. val |= CS_CDC_VER; // Codec version
  98. s->dregs[CS_RAP(s)] = val;
  99. break;
  100. default:
  101. s->dregs[CS_RAP(s)] = val;
  102. break;
  103. }
  104. break;
  105. case 2: // Read only
  106. break;
  107. case 4:
  108. if (val & 1)
  109. cs_reset(s);
  110. val &= 0x7f;
  111. s->regs[saddr] = val;
  112. break;
  113. default:
  114. s->regs[saddr] = val;
  115. break;
  116. }
  117. }
  118. static CPUReadMemoryFunc *cs_mem_read[3] = {
  119. cs_mem_readl,
  120. cs_mem_readl,
  121. cs_mem_readl,
  122. };
  123. static CPUWriteMemoryFunc *cs_mem_write[3] = {
  124. cs_mem_writel,
  125. cs_mem_writel,
  126. cs_mem_writel,
  127. };
  128. static void cs_save(QEMUFile *f, void *opaque)
  129. {
  130. CSState *s = opaque;
  131. unsigned int i;
  132. for (i = 0; i < CS_REGS; i++)
  133. qemu_put_be32s(f, &s->regs[i]);
  134. qemu_put_buffer(f, s->dregs, CS_DREGS);
  135. }
  136. static int cs_load(QEMUFile *f, void *opaque, int version_id)
  137. {
  138. CSState *s = opaque;
  139. unsigned int i;
  140. if (version_id > 1)
  141. return -EINVAL;
  142. for (i = 0; i < CS_REGS; i++)
  143. qemu_get_be32s(f, &s->regs[i]);
  144. qemu_get_buffer(f, s->dregs, CS_DREGS);
  145. return 0;
  146. }
  147. void cs_init(target_phys_addr_t base, int irq, void *intctl)
  148. {
  149. int cs_io_memory;
  150. CSState *s;
  151. s = qemu_mallocz(sizeof(CSState));
  152. cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
  153. cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
  154. register_savevm("cs4231", base, 1, cs_save, cs_load, s);
  155. qemu_register_reset(cs_reset, s);
  156. cs_reset(s);
  157. }