virtio-pci.c 67 KB

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  1. /*
  2. * Virtio PCI Bindings
  3. *
  4. * Copyright IBM, Corp. 2007
  5. * Copyright (c) 2009 CodeSourcery
  6. *
  7. * Authors:
  8. * Anthony Liguori <aliguori@us.ibm.com>
  9. * Paul Brook <paul@codesourcery.com>
  10. *
  11. * This work is licensed under the terms of the GNU GPL, version 2. See
  12. * the COPYING file in the top-level directory.
  13. *
  14. * Contributions after 2012-01-13 are licensed under the terms of the
  15. * GNU GPL, version 2 or (at your option) any later version.
  16. */
  17. #include "qemu/osdep.h"
  18. #include "exec/memop.h"
  19. #include "standard-headers/linux/virtio_pci.h"
  20. #include "hw/virtio/virtio.h"
  21. #include "migration/qemu-file-types.h"
  22. #include "hw/pci/pci.h"
  23. #include "hw/pci/pci_bus.h"
  24. #include "hw/qdev-properties.h"
  25. #include "qapi/error.h"
  26. #include "qemu/error-report.h"
  27. #include "qemu/module.h"
  28. #include "hw/pci/msi.h"
  29. #include "hw/pci/msix.h"
  30. #include "hw/loader.h"
  31. #include "sysemu/kvm.h"
  32. #include "virtio-pci.h"
  33. #include "qemu/range.h"
  34. #include "hw/virtio/virtio-bus.h"
  35. #include "qapi/visitor.h"
  36. #define VIRTIO_PCI_REGION_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_present(dev))
  37. #undef VIRTIO_PCI_CONFIG
  38. /* The remaining space is defined by each driver as the per-driver
  39. * configuration space */
  40. #define VIRTIO_PCI_CONFIG_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_enabled(dev))
  41. static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
  42. VirtIOPCIProxy *dev);
  43. static void virtio_pci_reset(DeviceState *qdev);
  44. /* virtio device */
  45. /* DeviceState to VirtIOPCIProxy. For use off data-path. TODO: use QOM. */
  46. static inline VirtIOPCIProxy *to_virtio_pci_proxy(DeviceState *d)
  47. {
  48. return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
  49. }
  50. /* DeviceState to VirtIOPCIProxy. Note: used on datapath,
  51. * be careful and test performance if you change this.
  52. */
  53. static inline VirtIOPCIProxy *to_virtio_pci_proxy_fast(DeviceState *d)
  54. {
  55. return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
  56. }
  57. static void virtio_pci_notify(DeviceState *d, uint16_t vector)
  58. {
  59. VirtIOPCIProxy *proxy = to_virtio_pci_proxy_fast(d);
  60. if (msix_enabled(&proxy->pci_dev))
  61. msix_notify(&proxy->pci_dev, vector);
  62. else {
  63. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  64. pci_set_irq(&proxy->pci_dev, atomic_read(&vdev->isr) & 1);
  65. }
  66. }
  67. static void virtio_pci_save_config(DeviceState *d, QEMUFile *f)
  68. {
  69. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  70. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  71. pci_device_save(&proxy->pci_dev, f);
  72. msix_save(&proxy->pci_dev, f);
  73. if (msix_present(&proxy->pci_dev))
  74. qemu_put_be16(f, vdev->config_vector);
  75. }
  76. static const VMStateDescription vmstate_virtio_pci_modern_queue_state = {
  77. .name = "virtio_pci/modern_queue_state",
  78. .version_id = 1,
  79. .minimum_version_id = 1,
  80. .fields = (VMStateField[]) {
  81. VMSTATE_UINT16(num, VirtIOPCIQueue),
  82. VMSTATE_UNUSED(1), /* enabled was stored as be16 */
  83. VMSTATE_BOOL(enabled, VirtIOPCIQueue),
  84. VMSTATE_UINT32_ARRAY(desc, VirtIOPCIQueue, 2),
  85. VMSTATE_UINT32_ARRAY(avail, VirtIOPCIQueue, 2),
  86. VMSTATE_UINT32_ARRAY(used, VirtIOPCIQueue, 2),
  87. VMSTATE_END_OF_LIST()
  88. }
  89. };
  90. static bool virtio_pci_modern_state_needed(void *opaque)
  91. {
  92. VirtIOPCIProxy *proxy = opaque;
  93. return virtio_pci_modern(proxy);
  94. }
  95. static const VMStateDescription vmstate_virtio_pci_modern_state_sub = {
  96. .name = "virtio_pci/modern_state",
  97. .version_id = 1,
  98. .minimum_version_id = 1,
  99. .needed = &virtio_pci_modern_state_needed,
  100. .fields = (VMStateField[]) {
  101. VMSTATE_UINT32(dfselect, VirtIOPCIProxy),
  102. VMSTATE_UINT32(gfselect, VirtIOPCIProxy),
  103. VMSTATE_UINT32_ARRAY(guest_features, VirtIOPCIProxy, 2),
  104. VMSTATE_STRUCT_ARRAY(vqs, VirtIOPCIProxy, VIRTIO_QUEUE_MAX, 0,
  105. vmstate_virtio_pci_modern_queue_state,
  106. VirtIOPCIQueue),
  107. VMSTATE_END_OF_LIST()
  108. }
  109. };
  110. static const VMStateDescription vmstate_virtio_pci = {
  111. .name = "virtio_pci",
  112. .version_id = 1,
  113. .minimum_version_id = 1,
  114. .minimum_version_id_old = 1,
  115. .fields = (VMStateField[]) {
  116. VMSTATE_END_OF_LIST()
  117. },
  118. .subsections = (const VMStateDescription*[]) {
  119. &vmstate_virtio_pci_modern_state_sub,
  120. NULL
  121. }
  122. };
  123. static bool virtio_pci_has_extra_state(DeviceState *d)
  124. {
  125. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  126. return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
  127. }
  128. static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
  129. {
  130. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  131. vmstate_save_state(f, &vmstate_virtio_pci, proxy, NULL);
  132. }
  133. static int virtio_pci_load_extra_state(DeviceState *d, QEMUFile *f)
  134. {
  135. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  136. return vmstate_load_state(f, &vmstate_virtio_pci, proxy, 1);
  137. }
  138. static void virtio_pci_save_queue(DeviceState *d, int n, QEMUFile *f)
  139. {
  140. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  141. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  142. if (msix_present(&proxy->pci_dev))
  143. qemu_put_be16(f, virtio_queue_vector(vdev, n));
  144. }
  145. static int virtio_pci_load_config(DeviceState *d, QEMUFile *f)
  146. {
  147. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  148. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  149. int ret;
  150. ret = pci_device_load(&proxy->pci_dev, f);
  151. if (ret) {
  152. return ret;
  153. }
  154. msix_unuse_all_vectors(&proxy->pci_dev);
  155. msix_load(&proxy->pci_dev, f);
  156. if (msix_present(&proxy->pci_dev)) {
  157. qemu_get_be16s(f, &vdev->config_vector);
  158. } else {
  159. vdev->config_vector = VIRTIO_NO_VECTOR;
  160. }
  161. if (vdev->config_vector != VIRTIO_NO_VECTOR) {
  162. return msix_vector_use(&proxy->pci_dev, vdev->config_vector);
  163. }
  164. return 0;
  165. }
  166. static int virtio_pci_load_queue(DeviceState *d, int n, QEMUFile *f)
  167. {
  168. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  169. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  170. uint16_t vector;
  171. if (msix_present(&proxy->pci_dev)) {
  172. qemu_get_be16s(f, &vector);
  173. } else {
  174. vector = VIRTIO_NO_VECTOR;
  175. }
  176. virtio_queue_set_vector(vdev, n, vector);
  177. if (vector != VIRTIO_NO_VECTOR) {
  178. return msix_vector_use(&proxy->pci_dev, vector);
  179. }
  180. return 0;
  181. }
  182. static bool virtio_pci_ioeventfd_enabled(DeviceState *d)
  183. {
  184. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  185. return (proxy->flags & VIRTIO_PCI_FLAG_USE_IOEVENTFD) != 0;
  186. }
  187. #define QEMU_VIRTIO_PCI_QUEUE_MEM_MULT 0x1000
  188. static inline int virtio_pci_queue_mem_mult(struct VirtIOPCIProxy *proxy)
  189. {
  190. return (proxy->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ) ?
  191. QEMU_VIRTIO_PCI_QUEUE_MEM_MULT : 4;
  192. }
  193. static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier,
  194. int n, bool assign)
  195. {
  196. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  197. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  198. VirtQueue *vq = virtio_get_queue(vdev, n);
  199. bool legacy = virtio_pci_legacy(proxy);
  200. bool modern = virtio_pci_modern(proxy);
  201. bool fast_mmio = kvm_ioeventfd_any_length_enabled();
  202. bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
  203. MemoryRegion *modern_mr = &proxy->notify.mr;
  204. MemoryRegion *modern_notify_mr = &proxy->notify_pio.mr;
  205. MemoryRegion *legacy_mr = &proxy->bar;
  206. hwaddr modern_addr = virtio_pci_queue_mem_mult(proxy) *
  207. virtio_get_queue_index(vq);
  208. hwaddr legacy_addr = VIRTIO_PCI_QUEUE_NOTIFY;
  209. if (assign) {
  210. if (modern) {
  211. if (fast_mmio) {
  212. memory_region_add_eventfd(modern_mr, modern_addr, 0,
  213. false, n, notifier);
  214. } else {
  215. memory_region_add_eventfd(modern_mr, modern_addr, 2,
  216. false, n, notifier);
  217. }
  218. if (modern_pio) {
  219. memory_region_add_eventfd(modern_notify_mr, 0, 2,
  220. true, n, notifier);
  221. }
  222. }
  223. if (legacy) {
  224. memory_region_add_eventfd(legacy_mr, legacy_addr, 2,
  225. true, n, notifier);
  226. }
  227. } else {
  228. if (modern) {
  229. if (fast_mmio) {
  230. memory_region_del_eventfd(modern_mr, modern_addr, 0,
  231. false, n, notifier);
  232. } else {
  233. memory_region_del_eventfd(modern_mr, modern_addr, 2,
  234. false, n, notifier);
  235. }
  236. if (modern_pio) {
  237. memory_region_del_eventfd(modern_notify_mr, 0, 2,
  238. true, n, notifier);
  239. }
  240. }
  241. if (legacy) {
  242. memory_region_del_eventfd(legacy_mr, legacy_addr, 2,
  243. true, n, notifier);
  244. }
  245. }
  246. return 0;
  247. }
  248. static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy)
  249. {
  250. virtio_bus_start_ioeventfd(&proxy->bus);
  251. }
  252. static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy)
  253. {
  254. virtio_bus_stop_ioeventfd(&proxy->bus);
  255. }
  256. static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
  257. {
  258. VirtIOPCIProxy *proxy = opaque;
  259. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  260. hwaddr pa;
  261. switch (addr) {
  262. case VIRTIO_PCI_GUEST_FEATURES:
  263. /* Guest does not negotiate properly? We have to assume nothing. */
  264. if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
  265. val = virtio_bus_get_vdev_bad_features(&proxy->bus);
  266. }
  267. virtio_set_features(vdev, val);
  268. break;
  269. case VIRTIO_PCI_QUEUE_PFN:
  270. pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
  271. if (pa == 0) {
  272. virtio_pci_reset(DEVICE(proxy));
  273. }
  274. else
  275. virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
  276. break;
  277. case VIRTIO_PCI_QUEUE_SEL:
  278. if (val < VIRTIO_QUEUE_MAX)
  279. vdev->queue_sel = val;
  280. break;
  281. case VIRTIO_PCI_QUEUE_NOTIFY:
  282. if (val < VIRTIO_QUEUE_MAX) {
  283. virtio_queue_notify(vdev, val);
  284. }
  285. break;
  286. case VIRTIO_PCI_STATUS:
  287. if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
  288. virtio_pci_stop_ioeventfd(proxy);
  289. }
  290. virtio_set_status(vdev, val & 0xFF);
  291. if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
  292. virtio_pci_start_ioeventfd(proxy);
  293. }
  294. if (vdev->status == 0) {
  295. virtio_pci_reset(DEVICE(proxy));
  296. }
  297. /* Linux before 2.6.34 drives the device without enabling
  298. the PCI device bus master bit. Enable it automatically
  299. for the guest. This is a PCI spec violation but so is
  300. initiating DMA with bus master bit clear. */
  301. if (val == (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER)) {
  302. pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
  303. proxy->pci_dev.config[PCI_COMMAND] |
  304. PCI_COMMAND_MASTER, 1);
  305. }
  306. break;
  307. case VIRTIO_MSI_CONFIG_VECTOR:
  308. msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
  309. /* Make it possible for guest to discover an error took place. */
  310. if (msix_vector_use(&proxy->pci_dev, val) < 0)
  311. val = VIRTIO_NO_VECTOR;
  312. vdev->config_vector = val;
  313. break;
  314. case VIRTIO_MSI_QUEUE_VECTOR:
  315. msix_vector_unuse(&proxy->pci_dev,
  316. virtio_queue_vector(vdev, vdev->queue_sel));
  317. /* Make it possible for guest to discover an error took place. */
  318. if (msix_vector_use(&proxy->pci_dev, val) < 0)
  319. val = VIRTIO_NO_VECTOR;
  320. virtio_queue_set_vector(vdev, vdev->queue_sel, val);
  321. break;
  322. default:
  323. error_report("%s: unexpected address 0x%x value 0x%x",
  324. __func__, addr, val);
  325. break;
  326. }
  327. }
  328. static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
  329. {
  330. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  331. uint32_t ret = 0xFFFFFFFF;
  332. switch (addr) {
  333. case VIRTIO_PCI_HOST_FEATURES:
  334. ret = vdev->host_features;
  335. break;
  336. case VIRTIO_PCI_GUEST_FEATURES:
  337. ret = vdev->guest_features;
  338. break;
  339. case VIRTIO_PCI_QUEUE_PFN:
  340. ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
  341. >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
  342. break;
  343. case VIRTIO_PCI_QUEUE_NUM:
  344. ret = virtio_queue_get_num(vdev, vdev->queue_sel);
  345. break;
  346. case VIRTIO_PCI_QUEUE_SEL:
  347. ret = vdev->queue_sel;
  348. break;
  349. case VIRTIO_PCI_STATUS:
  350. ret = vdev->status;
  351. break;
  352. case VIRTIO_PCI_ISR:
  353. /* reading from the ISR also clears it. */
  354. ret = atomic_xchg(&vdev->isr, 0);
  355. pci_irq_deassert(&proxy->pci_dev);
  356. break;
  357. case VIRTIO_MSI_CONFIG_VECTOR:
  358. ret = vdev->config_vector;
  359. break;
  360. case VIRTIO_MSI_QUEUE_VECTOR:
  361. ret = virtio_queue_vector(vdev, vdev->queue_sel);
  362. break;
  363. default:
  364. break;
  365. }
  366. return ret;
  367. }
  368. static uint64_t virtio_pci_config_read(void *opaque, hwaddr addr,
  369. unsigned size)
  370. {
  371. VirtIOPCIProxy *proxy = opaque;
  372. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  373. uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
  374. uint64_t val = 0;
  375. if (addr < config) {
  376. return virtio_ioport_read(proxy, addr);
  377. }
  378. addr -= config;
  379. switch (size) {
  380. case 1:
  381. val = virtio_config_readb(vdev, addr);
  382. break;
  383. case 2:
  384. val = virtio_config_readw(vdev, addr);
  385. if (virtio_is_big_endian(vdev)) {
  386. val = bswap16(val);
  387. }
  388. break;
  389. case 4:
  390. val = virtio_config_readl(vdev, addr);
  391. if (virtio_is_big_endian(vdev)) {
  392. val = bswap32(val);
  393. }
  394. break;
  395. }
  396. return val;
  397. }
  398. static void virtio_pci_config_write(void *opaque, hwaddr addr,
  399. uint64_t val, unsigned size)
  400. {
  401. VirtIOPCIProxy *proxy = opaque;
  402. uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
  403. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  404. if (addr < config) {
  405. virtio_ioport_write(proxy, addr, val);
  406. return;
  407. }
  408. addr -= config;
  409. /*
  410. * Virtio-PCI is odd. Ioports are LE but config space is target native
  411. * endian.
  412. */
  413. switch (size) {
  414. case 1:
  415. virtio_config_writeb(vdev, addr, val);
  416. break;
  417. case 2:
  418. if (virtio_is_big_endian(vdev)) {
  419. val = bswap16(val);
  420. }
  421. virtio_config_writew(vdev, addr, val);
  422. break;
  423. case 4:
  424. if (virtio_is_big_endian(vdev)) {
  425. val = bswap32(val);
  426. }
  427. virtio_config_writel(vdev, addr, val);
  428. break;
  429. }
  430. }
  431. static const MemoryRegionOps virtio_pci_config_ops = {
  432. .read = virtio_pci_config_read,
  433. .write = virtio_pci_config_write,
  434. .impl = {
  435. .min_access_size = 1,
  436. .max_access_size = 4,
  437. },
  438. .endianness = DEVICE_LITTLE_ENDIAN,
  439. };
  440. static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy,
  441. hwaddr *off, int len)
  442. {
  443. int i;
  444. VirtIOPCIRegion *reg;
  445. for (i = 0; i < ARRAY_SIZE(proxy->regs); ++i) {
  446. reg = &proxy->regs[i];
  447. if (*off >= reg->offset &&
  448. *off + len <= reg->offset + reg->size) {
  449. *off -= reg->offset;
  450. return &reg->mr;
  451. }
  452. }
  453. return NULL;
  454. }
  455. /* Below are generic functions to do memcpy from/to an address space,
  456. * without byteswaps, with input validation.
  457. *
  458. * As regular address_space_* APIs all do some kind of byteswap at least for
  459. * some host/target combinations, we are forced to explicitly convert to a
  460. * known-endianness integer value.
  461. * It doesn't really matter which endian format to go through, so the code
  462. * below selects the endian that causes the least amount of work on the given
  463. * host.
  464. *
  465. * Note: host pointer must be aligned.
  466. */
  467. static
  468. void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
  469. const uint8_t *buf, int len)
  470. {
  471. uint64_t val;
  472. MemoryRegion *mr;
  473. /* address_space_* APIs assume an aligned address.
  474. * As address is under guest control, handle illegal values.
  475. */
  476. addr &= ~(len - 1);
  477. mr = virtio_address_space_lookup(proxy, &addr, len);
  478. if (!mr) {
  479. return;
  480. }
  481. /* Make sure caller aligned buf properly */
  482. assert(!(((uintptr_t)buf) & (len - 1)));
  483. switch (len) {
  484. case 1:
  485. val = pci_get_byte(buf);
  486. break;
  487. case 2:
  488. val = pci_get_word(buf);
  489. break;
  490. case 4:
  491. val = pci_get_long(buf);
  492. break;
  493. default:
  494. /* As length is under guest control, handle illegal values. */
  495. return;
  496. }
  497. memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
  498. MEMTXATTRS_UNSPECIFIED);
  499. }
  500. static void
  501. virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
  502. uint8_t *buf, int len)
  503. {
  504. uint64_t val;
  505. MemoryRegion *mr;
  506. /* address_space_* APIs assume an aligned address.
  507. * As address is under guest control, handle illegal values.
  508. */
  509. addr &= ~(len - 1);
  510. mr = virtio_address_space_lookup(proxy, &addr, len);
  511. if (!mr) {
  512. return;
  513. }
  514. /* Make sure caller aligned buf properly */
  515. assert(!(((uintptr_t)buf) & (len - 1)));
  516. memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
  517. MEMTXATTRS_UNSPECIFIED);
  518. switch (len) {
  519. case 1:
  520. pci_set_byte(buf, val);
  521. break;
  522. case 2:
  523. pci_set_word(buf, val);
  524. break;
  525. case 4:
  526. pci_set_long(buf, val);
  527. break;
  528. default:
  529. /* As length is under guest control, handle illegal values. */
  530. break;
  531. }
  532. }
  533. static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
  534. uint32_t val, int len)
  535. {
  536. VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
  537. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  538. struct virtio_pci_cfg_cap *cfg;
  539. pci_default_write_config(pci_dev, address, val, len);
  540. if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
  541. pcie_cap_flr_write_config(pci_dev, address, val, len);
  542. }
  543. if (range_covers_byte(address, len, PCI_COMMAND)) {
  544. if (!(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
  545. virtio_set_disabled(vdev, true);
  546. virtio_pci_stop_ioeventfd(proxy);
  547. virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK);
  548. } else {
  549. virtio_set_disabled(vdev, false);
  550. }
  551. }
  552. if (proxy->config_cap &&
  553. ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
  554. pci_cfg_data),
  555. sizeof cfg->pci_cfg_data)) {
  556. uint32_t off;
  557. uint32_t len;
  558. cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
  559. off = le32_to_cpu(cfg->cap.offset);
  560. len = le32_to_cpu(cfg->cap.length);
  561. if (len == 1 || len == 2 || len == 4) {
  562. assert(len <= sizeof cfg->pci_cfg_data);
  563. virtio_address_space_write(proxy, off, cfg->pci_cfg_data, len);
  564. }
  565. }
  566. }
  567. static uint32_t virtio_read_config(PCIDevice *pci_dev,
  568. uint32_t address, int len)
  569. {
  570. VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
  571. struct virtio_pci_cfg_cap *cfg;
  572. if (proxy->config_cap &&
  573. ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
  574. pci_cfg_data),
  575. sizeof cfg->pci_cfg_data)) {
  576. uint32_t off;
  577. uint32_t len;
  578. cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
  579. off = le32_to_cpu(cfg->cap.offset);
  580. len = le32_to_cpu(cfg->cap.length);
  581. if (len == 1 || len == 2 || len == 4) {
  582. assert(len <= sizeof cfg->pci_cfg_data);
  583. virtio_address_space_read(proxy, off, cfg->pci_cfg_data, len);
  584. }
  585. }
  586. return pci_default_read_config(pci_dev, address, len);
  587. }
  588. static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
  589. unsigned int queue_no,
  590. unsigned int vector)
  591. {
  592. VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
  593. int ret;
  594. if (irqfd->users == 0) {
  595. ret = kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_dev);
  596. if (ret < 0) {
  597. return ret;
  598. }
  599. irqfd->virq = ret;
  600. }
  601. irqfd->users++;
  602. return 0;
  603. }
  604. static void kvm_virtio_pci_vq_vector_release(VirtIOPCIProxy *proxy,
  605. unsigned int vector)
  606. {
  607. VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
  608. if (--irqfd->users == 0) {
  609. kvm_irqchip_release_virq(kvm_state, irqfd->virq);
  610. }
  611. }
  612. static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy,
  613. unsigned int queue_no,
  614. unsigned int vector)
  615. {
  616. VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
  617. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  618. VirtQueue *vq = virtio_get_queue(vdev, queue_no);
  619. EventNotifier *n = virtio_queue_get_guest_notifier(vq);
  620. return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq);
  621. }
  622. static void kvm_virtio_pci_irqfd_release(VirtIOPCIProxy *proxy,
  623. unsigned int queue_no,
  624. unsigned int vector)
  625. {
  626. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  627. VirtQueue *vq = virtio_get_queue(vdev, queue_no);
  628. EventNotifier *n = virtio_queue_get_guest_notifier(vq);
  629. VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
  630. int ret;
  631. ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, irqfd->virq);
  632. assert(ret == 0);
  633. }
  634. static int kvm_virtio_pci_vector_use(VirtIOPCIProxy *proxy, int nvqs)
  635. {
  636. PCIDevice *dev = &proxy->pci_dev;
  637. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  638. VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
  639. unsigned int vector;
  640. int ret, queue_no;
  641. for (queue_no = 0; queue_no < nvqs; queue_no++) {
  642. if (!virtio_queue_get_num(vdev, queue_no)) {
  643. break;
  644. }
  645. vector = virtio_queue_vector(vdev, queue_no);
  646. if (vector >= msix_nr_vectors_allocated(dev)) {
  647. continue;
  648. }
  649. ret = kvm_virtio_pci_vq_vector_use(proxy, queue_no, vector);
  650. if (ret < 0) {
  651. goto undo;
  652. }
  653. /* If guest supports masking, set up irqfd now.
  654. * Otherwise, delay until unmasked in the frontend.
  655. */
  656. if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
  657. ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
  658. if (ret < 0) {
  659. kvm_virtio_pci_vq_vector_release(proxy, vector);
  660. goto undo;
  661. }
  662. }
  663. }
  664. return 0;
  665. undo:
  666. while (--queue_no >= 0) {
  667. vector = virtio_queue_vector(vdev, queue_no);
  668. if (vector >= msix_nr_vectors_allocated(dev)) {
  669. continue;
  670. }
  671. if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
  672. kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
  673. }
  674. kvm_virtio_pci_vq_vector_release(proxy, vector);
  675. }
  676. return ret;
  677. }
  678. static void kvm_virtio_pci_vector_release(VirtIOPCIProxy *proxy, int nvqs)
  679. {
  680. PCIDevice *dev = &proxy->pci_dev;
  681. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  682. unsigned int vector;
  683. int queue_no;
  684. VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
  685. for (queue_no = 0; queue_no < nvqs; queue_no++) {
  686. if (!virtio_queue_get_num(vdev, queue_no)) {
  687. break;
  688. }
  689. vector = virtio_queue_vector(vdev, queue_no);
  690. if (vector >= msix_nr_vectors_allocated(dev)) {
  691. continue;
  692. }
  693. /* If guest supports masking, clean up irqfd now.
  694. * Otherwise, it was cleaned when masked in the frontend.
  695. */
  696. if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
  697. kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
  698. }
  699. kvm_virtio_pci_vq_vector_release(proxy, vector);
  700. }
  701. }
  702. static int virtio_pci_vq_vector_unmask(VirtIOPCIProxy *proxy,
  703. unsigned int queue_no,
  704. unsigned int vector,
  705. MSIMessage msg)
  706. {
  707. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  708. VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
  709. VirtQueue *vq = virtio_get_queue(vdev, queue_no);
  710. EventNotifier *n = virtio_queue_get_guest_notifier(vq);
  711. VirtIOIRQFD *irqfd;
  712. int ret = 0;
  713. if (proxy->vector_irqfd) {
  714. irqfd = &proxy->vector_irqfd[vector];
  715. if (irqfd->msg.data != msg.data || irqfd->msg.address != msg.address) {
  716. ret = kvm_irqchip_update_msi_route(kvm_state, irqfd->virq, msg,
  717. &proxy->pci_dev);
  718. if (ret < 0) {
  719. return ret;
  720. }
  721. kvm_irqchip_commit_routes(kvm_state);
  722. }
  723. }
  724. /* If guest supports masking, irqfd is already setup, unmask it.
  725. * Otherwise, set it up now.
  726. */
  727. if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
  728. k->guest_notifier_mask(vdev, queue_no, false);
  729. /* Test after unmasking to avoid losing events. */
  730. if (k->guest_notifier_pending &&
  731. k->guest_notifier_pending(vdev, queue_no)) {
  732. event_notifier_set(n);
  733. }
  734. } else {
  735. ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
  736. }
  737. return ret;
  738. }
  739. static void virtio_pci_vq_vector_mask(VirtIOPCIProxy *proxy,
  740. unsigned int queue_no,
  741. unsigned int vector)
  742. {
  743. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  744. VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
  745. /* If guest supports masking, keep irqfd but mask it.
  746. * Otherwise, clean it up now.
  747. */
  748. if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
  749. k->guest_notifier_mask(vdev, queue_no, true);
  750. } else {
  751. kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
  752. }
  753. }
  754. static int virtio_pci_vector_unmask(PCIDevice *dev, unsigned vector,
  755. MSIMessage msg)
  756. {
  757. VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
  758. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  759. VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
  760. int ret, index, unmasked = 0;
  761. while (vq) {
  762. index = virtio_get_queue_index(vq);
  763. if (!virtio_queue_get_num(vdev, index)) {
  764. break;
  765. }
  766. if (index < proxy->nvqs_with_notifiers) {
  767. ret = virtio_pci_vq_vector_unmask(proxy, index, vector, msg);
  768. if (ret < 0) {
  769. goto undo;
  770. }
  771. ++unmasked;
  772. }
  773. vq = virtio_vector_next_queue(vq);
  774. }
  775. return 0;
  776. undo:
  777. vq = virtio_vector_first_queue(vdev, vector);
  778. while (vq && unmasked >= 0) {
  779. index = virtio_get_queue_index(vq);
  780. if (index < proxy->nvqs_with_notifiers) {
  781. virtio_pci_vq_vector_mask(proxy, index, vector);
  782. --unmasked;
  783. }
  784. vq = virtio_vector_next_queue(vq);
  785. }
  786. return ret;
  787. }
  788. static void virtio_pci_vector_mask(PCIDevice *dev, unsigned vector)
  789. {
  790. VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
  791. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  792. VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
  793. int index;
  794. while (vq) {
  795. index = virtio_get_queue_index(vq);
  796. if (!virtio_queue_get_num(vdev, index)) {
  797. break;
  798. }
  799. if (index < proxy->nvqs_with_notifiers) {
  800. virtio_pci_vq_vector_mask(proxy, index, vector);
  801. }
  802. vq = virtio_vector_next_queue(vq);
  803. }
  804. }
  805. static void virtio_pci_vector_poll(PCIDevice *dev,
  806. unsigned int vector_start,
  807. unsigned int vector_end)
  808. {
  809. VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
  810. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  811. VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
  812. int queue_no;
  813. unsigned int vector;
  814. EventNotifier *notifier;
  815. VirtQueue *vq;
  816. for (queue_no = 0; queue_no < proxy->nvqs_with_notifiers; queue_no++) {
  817. if (!virtio_queue_get_num(vdev, queue_no)) {
  818. break;
  819. }
  820. vector = virtio_queue_vector(vdev, queue_no);
  821. if (vector < vector_start || vector >= vector_end ||
  822. !msix_is_masked(dev, vector)) {
  823. continue;
  824. }
  825. vq = virtio_get_queue(vdev, queue_no);
  826. notifier = virtio_queue_get_guest_notifier(vq);
  827. if (k->guest_notifier_pending) {
  828. if (k->guest_notifier_pending(vdev, queue_no)) {
  829. msix_set_pending(dev, vector);
  830. }
  831. } else if (event_notifier_test_and_clear(notifier)) {
  832. msix_set_pending(dev, vector);
  833. }
  834. }
  835. }
  836. static int virtio_pci_set_guest_notifier(DeviceState *d, int n, bool assign,
  837. bool with_irqfd)
  838. {
  839. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  840. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  841. VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
  842. VirtQueue *vq = virtio_get_queue(vdev, n);
  843. EventNotifier *notifier = virtio_queue_get_guest_notifier(vq);
  844. if (assign) {
  845. int r = event_notifier_init(notifier, 0);
  846. if (r < 0) {
  847. return r;
  848. }
  849. virtio_queue_set_guest_notifier_fd_handler(vq, true, with_irqfd);
  850. } else {
  851. virtio_queue_set_guest_notifier_fd_handler(vq, false, with_irqfd);
  852. event_notifier_cleanup(notifier);
  853. }
  854. if (!msix_enabled(&proxy->pci_dev) &&
  855. vdev->use_guest_notifier_mask &&
  856. vdc->guest_notifier_mask) {
  857. vdc->guest_notifier_mask(vdev, n, !assign);
  858. }
  859. return 0;
  860. }
  861. static bool virtio_pci_query_guest_notifiers(DeviceState *d)
  862. {
  863. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  864. return msix_enabled(&proxy->pci_dev);
  865. }
  866. static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign)
  867. {
  868. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  869. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  870. VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
  871. int r, n;
  872. bool with_irqfd = msix_enabled(&proxy->pci_dev) &&
  873. kvm_msi_via_irqfd_enabled();
  874. nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX);
  875. /* When deassigning, pass a consistent nvqs value
  876. * to avoid leaking notifiers.
  877. */
  878. assert(assign || nvqs == proxy->nvqs_with_notifiers);
  879. proxy->nvqs_with_notifiers = nvqs;
  880. /* Must unset vector notifier while guest notifier is still assigned */
  881. if ((proxy->vector_irqfd || k->guest_notifier_mask) && !assign) {
  882. msix_unset_vector_notifiers(&proxy->pci_dev);
  883. if (proxy->vector_irqfd) {
  884. kvm_virtio_pci_vector_release(proxy, nvqs);
  885. g_free(proxy->vector_irqfd);
  886. proxy->vector_irqfd = NULL;
  887. }
  888. }
  889. for (n = 0; n < nvqs; n++) {
  890. if (!virtio_queue_get_num(vdev, n)) {
  891. break;
  892. }
  893. r = virtio_pci_set_guest_notifier(d, n, assign, with_irqfd);
  894. if (r < 0) {
  895. goto assign_error;
  896. }
  897. }
  898. /* Must set vector notifier after guest notifier has been assigned */
  899. if ((with_irqfd || k->guest_notifier_mask) && assign) {
  900. if (with_irqfd) {
  901. proxy->vector_irqfd =
  902. g_malloc0(sizeof(*proxy->vector_irqfd) *
  903. msix_nr_vectors_allocated(&proxy->pci_dev));
  904. r = kvm_virtio_pci_vector_use(proxy, nvqs);
  905. if (r < 0) {
  906. goto assign_error;
  907. }
  908. }
  909. r = msix_set_vector_notifiers(&proxy->pci_dev,
  910. virtio_pci_vector_unmask,
  911. virtio_pci_vector_mask,
  912. virtio_pci_vector_poll);
  913. if (r < 0) {
  914. goto notifiers_error;
  915. }
  916. }
  917. return 0;
  918. notifiers_error:
  919. if (with_irqfd) {
  920. assert(assign);
  921. kvm_virtio_pci_vector_release(proxy, nvqs);
  922. }
  923. assign_error:
  924. /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */
  925. assert(assign);
  926. while (--n >= 0) {
  927. virtio_pci_set_guest_notifier(d, n, !assign, with_irqfd);
  928. }
  929. return r;
  930. }
  931. static int virtio_pci_set_host_notifier_mr(DeviceState *d, int n,
  932. MemoryRegion *mr, bool assign)
  933. {
  934. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  935. int offset;
  936. if (n >= VIRTIO_QUEUE_MAX || !virtio_pci_modern(proxy) ||
  937. virtio_pci_queue_mem_mult(proxy) != memory_region_size(mr)) {
  938. return -1;
  939. }
  940. if (assign) {
  941. offset = virtio_pci_queue_mem_mult(proxy) * n;
  942. memory_region_add_subregion_overlap(&proxy->notify.mr, offset, mr, 1);
  943. } else {
  944. memory_region_del_subregion(&proxy->notify.mr, mr);
  945. }
  946. return 0;
  947. }
  948. static void virtio_pci_vmstate_change(DeviceState *d, bool running)
  949. {
  950. VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
  951. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  952. if (running) {
  953. /* Old QEMU versions did not set bus master enable on status write.
  954. * Detect DRIVER set and enable it.
  955. */
  956. if ((proxy->flags & VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION) &&
  957. (vdev->status & VIRTIO_CONFIG_S_DRIVER) &&
  958. !(proxy->pci_dev.config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
  959. pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
  960. proxy->pci_dev.config[PCI_COMMAND] |
  961. PCI_COMMAND_MASTER, 1);
  962. }
  963. virtio_pci_start_ioeventfd(proxy);
  964. } else {
  965. virtio_pci_stop_ioeventfd(proxy);
  966. }
  967. }
  968. /*
  969. * virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
  970. */
  971. static int virtio_pci_query_nvectors(DeviceState *d)
  972. {
  973. VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  974. return proxy->nvectors;
  975. }
  976. static AddressSpace *virtio_pci_get_dma_as(DeviceState *d)
  977. {
  978. VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  979. PCIDevice *dev = &proxy->pci_dev;
  980. return pci_get_address_space(dev);
  981. }
  982. static bool virtio_pci_queue_enabled(DeviceState *d, int n)
  983. {
  984. VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  985. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  986. if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
  987. return proxy->vqs[n].enabled;
  988. }
  989. return virtio_queue_enabled_legacy(vdev, n);
  990. }
  991. static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
  992. struct virtio_pci_cap *cap)
  993. {
  994. PCIDevice *dev = &proxy->pci_dev;
  995. int offset;
  996. offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
  997. cap->cap_len, &error_abort);
  998. assert(cap->cap_len >= sizeof *cap);
  999. memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
  1000. cap->cap_len - PCI_CAP_FLAGS);
  1001. return offset;
  1002. }
  1003. static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr,
  1004. unsigned size)
  1005. {
  1006. VirtIOPCIProxy *proxy = opaque;
  1007. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1008. uint32_t val = 0;
  1009. int i;
  1010. switch (addr) {
  1011. case VIRTIO_PCI_COMMON_DFSELECT:
  1012. val = proxy->dfselect;
  1013. break;
  1014. case VIRTIO_PCI_COMMON_DF:
  1015. if (proxy->dfselect <= 1) {
  1016. VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
  1017. val = (vdev->host_features & ~vdc->legacy_features) >>
  1018. (32 * proxy->dfselect);
  1019. }
  1020. break;
  1021. case VIRTIO_PCI_COMMON_GFSELECT:
  1022. val = proxy->gfselect;
  1023. break;
  1024. case VIRTIO_PCI_COMMON_GF:
  1025. if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
  1026. val = proxy->guest_features[proxy->gfselect];
  1027. }
  1028. break;
  1029. case VIRTIO_PCI_COMMON_MSIX:
  1030. val = vdev->config_vector;
  1031. break;
  1032. case VIRTIO_PCI_COMMON_NUMQ:
  1033. for (i = 0; i < VIRTIO_QUEUE_MAX; ++i) {
  1034. if (virtio_queue_get_num(vdev, i)) {
  1035. val = i + 1;
  1036. }
  1037. }
  1038. break;
  1039. case VIRTIO_PCI_COMMON_STATUS:
  1040. val = vdev->status;
  1041. break;
  1042. case VIRTIO_PCI_COMMON_CFGGENERATION:
  1043. val = vdev->generation;
  1044. break;
  1045. case VIRTIO_PCI_COMMON_Q_SELECT:
  1046. val = vdev->queue_sel;
  1047. break;
  1048. case VIRTIO_PCI_COMMON_Q_SIZE:
  1049. val = virtio_queue_get_num(vdev, vdev->queue_sel);
  1050. break;
  1051. case VIRTIO_PCI_COMMON_Q_MSIX:
  1052. val = virtio_queue_vector(vdev, vdev->queue_sel);
  1053. break;
  1054. case VIRTIO_PCI_COMMON_Q_ENABLE:
  1055. val = proxy->vqs[vdev->queue_sel].enabled;
  1056. break;
  1057. case VIRTIO_PCI_COMMON_Q_NOFF:
  1058. /* Simply map queues in order */
  1059. val = vdev->queue_sel;
  1060. break;
  1061. case VIRTIO_PCI_COMMON_Q_DESCLO:
  1062. val = proxy->vqs[vdev->queue_sel].desc[0];
  1063. break;
  1064. case VIRTIO_PCI_COMMON_Q_DESCHI:
  1065. val = proxy->vqs[vdev->queue_sel].desc[1];
  1066. break;
  1067. case VIRTIO_PCI_COMMON_Q_AVAILLO:
  1068. val = proxy->vqs[vdev->queue_sel].avail[0];
  1069. break;
  1070. case VIRTIO_PCI_COMMON_Q_AVAILHI:
  1071. val = proxy->vqs[vdev->queue_sel].avail[1];
  1072. break;
  1073. case VIRTIO_PCI_COMMON_Q_USEDLO:
  1074. val = proxy->vqs[vdev->queue_sel].used[0];
  1075. break;
  1076. case VIRTIO_PCI_COMMON_Q_USEDHI:
  1077. val = proxy->vqs[vdev->queue_sel].used[1];
  1078. break;
  1079. default:
  1080. val = 0;
  1081. }
  1082. return val;
  1083. }
  1084. static void virtio_pci_common_write(void *opaque, hwaddr addr,
  1085. uint64_t val, unsigned size)
  1086. {
  1087. VirtIOPCIProxy *proxy = opaque;
  1088. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1089. switch (addr) {
  1090. case VIRTIO_PCI_COMMON_DFSELECT:
  1091. proxy->dfselect = val;
  1092. break;
  1093. case VIRTIO_PCI_COMMON_GFSELECT:
  1094. proxy->gfselect = val;
  1095. break;
  1096. case VIRTIO_PCI_COMMON_GF:
  1097. if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
  1098. proxy->guest_features[proxy->gfselect] = val;
  1099. virtio_set_features(vdev,
  1100. (((uint64_t)proxy->guest_features[1]) << 32) |
  1101. proxy->guest_features[0]);
  1102. }
  1103. break;
  1104. case VIRTIO_PCI_COMMON_MSIX:
  1105. msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
  1106. /* Make it possible for guest to discover an error took place. */
  1107. if (msix_vector_use(&proxy->pci_dev, val) < 0) {
  1108. val = VIRTIO_NO_VECTOR;
  1109. }
  1110. vdev->config_vector = val;
  1111. break;
  1112. case VIRTIO_PCI_COMMON_STATUS:
  1113. if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
  1114. virtio_pci_stop_ioeventfd(proxy);
  1115. }
  1116. virtio_set_status(vdev, val & 0xFF);
  1117. if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
  1118. virtio_pci_start_ioeventfd(proxy);
  1119. }
  1120. if (vdev->status == 0) {
  1121. virtio_pci_reset(DEVICE(proxy));
  1122. }
  1123. break;
  1124. case VIRTIO_PCI_COMMON_Q_SELECT:
  1125. if (val < VIRTIO_QUEUE_MAX) {
  1126. vdev->queue_sel = val;
  1127. }
  1128. break;
  1129. case VIRTIO_PCI_COMMON_Q_SIZE:
  1130. proxy->vqs[vdev->queue_sel].num = val;
  1131. virtio_queue_set_num(vdev, vdev->queue_sel,
  1132. proxy->vqs[vdev->queue_sel].num);
  1133. break;
  1134. case VIRTIO_PCI_COMMON_Q_MSIX:
  1135. msix_vector_unuse(&proxy->pci_dev,
  1136. virtio_queue_vector(vdev, vdev->queue_sel));
  1137. /* Make it possible for guest to discover an error took place. */
  1138. if (msix_vector_use(&proxy->pci_dev, val) < 0) {
  1139. val = VIRTIO_NO_VECTOR;
  1140. }
  1141. virtio_queue_set_vector(vdev, vdev->queue_sel, val);
  1142. break;
  1143. case VIRTIO_PCI_COMMON_Q_ENABLE:
  1144. if (val == 1) {
  1145. virtio_queue_set_num(vdev, vdev->queue_sel,
  1146. proxy->vqs[vdev->queue_sel].num);
  1147. virtio_queue_set_rings(vdev, vdev->queue_sel,
  1148. ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 |
  1149. proxy->vqs[vdev->queue_sel].desc[0],
  1150. ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 |
  1151. proxy->vqs[vdev->queue_sel].avail[0],
  1152. ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 |
  1153. proxy->vqs[vdev->queue_sel].used[0]);
  1154. proxy->vqs[vdev->queue_sel].enabled = 1;
  1155. } else {
  1156. virtio_error(vdev, "wrong value for queue_enable %"PRIx64, val);
  1157. }
  1158. break;
  1159. case VIRTIO_PCI_COMMON_Q_DESCLO:
  1160. proxy->vqs[vdev->queue_sel].desc[0] = val;
  1161. break;
  1162. case VIRTIO_PCI_COMMON_Q_DESCHI:
  1163. proxy->vqs[vdev->queue_sel].desc[1] = val;
  1164. break;
  1165. case VIRTIO_PCI_COMMON_Q_AVAILLO:
  1166. proxy->vqs[vdev->queue_sel].avail[0] = val;
  1167. break;
  1168. case VIRTIO_PCI_COMMON_Q_AVAILHI:
  1169. proxy->vqs[vdev->queue_sel].avail[1] = val;
  1170. break;
  1171. case VIRTIO_PCI_COMMON_Q_USEDLO:
  1172. proxy->vqs[vdev->queue_sel].used[0] = val;
  1173. break;
  1174. case VIRTIO_PCI_COMMON_Q_USEDHI:
  1175. proxy->vqs[vdev->queue_sel].used[1] = val;
  1176. break;
  1177. default:
  1178. break;
  1179. }
  1180. }
  1181. static uint64_t virtio_pci_notify_read(void *opaque, hwaddr addr,
  1182. unsigned size)
  1183. {
  1184. return 0;
  1185. }
  1186. static void virtio_pci_notify_write(void *opaque, hwaddr addr,
  1187. uint64_t val, unsigned size)
  1188. {
  1189. VirtIOPCIProxy *proxy = opaque;
  1190. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1191. unsigned queue = addr / virtio_pci_queue_mem_mult(proxy);
  1192. if (vdev != NULL && queue < VIRTIO_QUEUE_MAX) {
  1193. virtio_queue_notify(vdev, queue);
  1194. }
  1195. }
  1196. static void virtio_pci_notify_write_pio(void *opaque, hwaddr addr,
  1197. uint64_t val, unsigned size)
  1198. {
  1199. VirtIOPCIProxy *proxy = opaque;
  1200. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1201. unsigned queue = val;
  1202. if (vdev != NULL && queue < VIRTIO_QUEUE_MAX) {
  1203. virtio_queue_notify(vdev, queue);
  1204. }
  1205. }
  1206. static uint64_t virtio_pci_isr_read(void *opaque, hwaddr addr,
  1207. unsigned size)
  1208. {
  1209. VirtIOPCIProxy *proxy = opaque;
  1210. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1211. uint64_t val = atomic_xchg(&vdev->isr, 0);
  1212. pci_irq_deassert(&proxy->pci_dev);
  1213. return val;
  1214. }
  1215. static void virtio_pci_isr_write(void *opaque, hwaddr addr,
  1216. uint64_t val, unsigned size)
  1217. {
  1218. }
  1219. static uint64_t virtio_pci_device_read(void *opaque, hwaddr addr,
  1220. unsigned size)
  1221. {
  1222. VirtIOPCIProxy *proxy = opaque;
  1223. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1224. uint64_t val = 0;
  1225. if (vdev == NULL) {
  1226. return val;
  1227. }
  1228. switch (size) {
  1229. case 1:
  1230. val = virtio_config_modern_readb(vdev, addr);
  1231. break;
  1232. case 2:
  1233. val = virtio_config_modern_readw(vdev, addr);
  1234. break;
  1235. case 4:
  1236. val = virtio_config_modern_readl(vdev, addr);
  1237. break;
  1238. }
  1239. return val;
  1240. }
  1241. static void virtio_pci_device_write(void *opaque, hwaddr addr,
  1242. uint64_t val, unsigned size)
  1243. {
  1244. VirtIOPCIProxy *proxy = opaque;
  1245. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1246. if (vdev == NULL) {
  1247. return;
  1248. }
  1249. switch (size) {
  1250. case 1:
  1251. virtio_config_modern_writeb(vdev, addr, val);
  1252. break;
  1253. case 2:
  1254. virtio_config_modern_writew(vdev, addr, val);
  1255. break;
  1256. case 4:
  1257. virtio_config_modern_writel(vdev, addr, val);
  1258. break;
  1259. }
  1260. }
  1261. static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy)
  1262. {
  1263. static const MemoryRegionOps common_ops = {
  1264. .read = virtio_pci_common_read,
  1265. .write = virtio_pci_common_write,
  1266. .impl = {
  1267. .min_access_size = 1,
  1268. .max_access_size = 4,
  1269. },
  1270. .endianness = DEVICE_LITTLE_ENDIAN,
  1271. };
  1272. static const MemoryRegionOps isr_ops = {
  1273. .read = virtio_pci_isr_read,
  1274. .write = virtio_pci_isr_write,
  1275. .impl = {
  1276. .min_access_size = 1,
  1277. .max_access_size = 4,
  1278. },
  1279. .endianness = DEVICE_LITTLE_ENDIAN,
  1280. };
  1281. static const MemoryRegionOps device_ops = {
  1282. .read = virtio_pci_device_read,
  1283. .write = virtio_pci_device_write,
  1284. .impl = {
  1285. .min_access_size = 1,
  1286. .max_access_size = 4,
  1287. },
  1288. .endianness = DEVICE_LITTLE_ENDIAN,
  1289. };
  1290. static const MemoryRegionOps notify_ops = {
  1291. .read = virtio_pci_notify_read,
  1292. .write = virtio_pci_notify_write,
  1293. .impl = {
  1294. .min_access_size = 1,
  1295. .max_access_size = 4,
  1296. },
  1297. .endianness = DEVICE_LITTLE_ENDIAN,
  1298. };
  1299. static const MemoryRegionOps notify_pio_ops = {
  1300. .read = virtio_pci_notify_read,
  1301. .write = virtio_pci_notify_write_pio,
  1302. .impl = {
  1303. .min_access_size = 1,
  1304. .max_access_size = 4,
  1305. },
  1306. .endianness = DEVICE_LITTLE_ENDIAN,
  1307. };
  1308. memory_region_init_io(&proxy->common.mr, OBJECT(proxy),
  1309. &common_ops,
  1310. proxy,
  1311. "virtio-pci-common",
  1312. proxy->common.size);
  1313. memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),
  1314. &isr_ops,
  1315. proxy,
  1316. "virtio-pci-isr",
  1317. proxy->isr.size);
  1318. memory_region_init_io(&proxy->device.mr, OBJECT(proxy),
  1319. &device_ops,
  1320. proxy,
  1321. "virtio-pci-device",
  1322. proxy->device.size);
  1323. memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),
  1324. &notify_ops,
  1325. proxy,
  1326. "virtio-pci-notify",
  1327. proxy->notify.size);
  1328. memory_region_init_io(&proxy->notify_pio.mr, OBJECT(proxy),
  1329. &notify_pio_ops,
  1330. proxy,
  1331. "virtio-pci-notify-pio",
  1332. proxy->notify_pio.size);
  1333. }
  1334. static void virtio_pci_modern_region_map(VirtIOPCIProxy *proxy,
  1335. VirtIOPCIRegion *region,
  1336. struct virtio_pci_cap *cap,
  1337. MemoryRegion *mr,
  1338. uint8_t bar)
  1339. {
  1340. memory_region_add_subregion(mr, region->offset, &region->mr);
  1341. cap->cfg_type = region->type;
  1342. cap->bar = bar;
  1343. cap->offset = cpu_to_le32(region->offset);
  1344. cap->length = cpu_to_le32(region->size);
  1345. virtio_pci_add_mem_cap(proxy, cap);
  1346. }
  1347. static void virtio_pci_modern_mem_region_map(VirtIOPCIProxy *proxy,
  1348. VirtIOPCIRegion *region,
  1349. struct virtio_pci_cap *cap)
  1350. {
  1351. virtio_pci_modern_region_map(proxy, region, cap,
  1352. &proxy->modern_bar, proxy->modern_mem_bar_idx);
  1353. }
  1354. static void virtio_pci_modern_io_region_map(VirtIOPCIProxy *proxy,
  1355. VirtIOPCIRegion *region,
  1356. struct virtio_pci_cap *cap)
  1357. {
  1358. virtio_pci_modern_region_map(proxy, region, cap,
  1359. &proxy->io_bar, proxy->modern_io_bar_idx);
  1360. }
  1361. static void virtio_pci_modern_mem_region_unmap(VirtIOPCIProxy *proxy,
  1362. VirtIOPCIRegion *region)
  1363. {
  1364. memory_region_del_subregion(&proxy->modern_bar,
  1365. &region->mr);
  1366. }
  1367. static void virtio_pci_modern_io_region_unmap(VirtIOPCIProxy *proxy,
  1368. VirtIOPCIRegion *region)
  1369. {
  1370. memory_region_del_subregion(&proxy->io_bar,
  1371. &region->mr);
  1372. }
  1373. static void virtio_pci_pre_plugged(DeviceState *d, Error **errp)
  1374. {
  1375. VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  1376. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1377. if (virtio_pci_modern(proxy)) {
  1378. virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1);
  1379. }
  1380. virtio_add_feature(&vdev->host_features, VIRTIO_F_BAD_FEATURE);
  1381. }
  1382. /* This is called by virtio-bus just after the device is plugged. */
  1383. static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
  1384. {
  1385. VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  1386. VirtioBusState *bus = &proxy->bus;
  1387. bool legacy = virtio_pci_legacy(proxy);
  1388. bool modern;
  1389. bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
  1390. uint8_t *config;
  1391. uint32_t size;
  1392. VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  1393. /*
  1394. * Virtio capabilities present without
  1395. * VIRTIO_F_VERSION_1 confuses guests
  1396. */
  1397. if (!proxy->ignore_backend_features &&
  1398. !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) {
  1399. virtio_pci_disable_modern(proxy);
  1400. if (!legacy) {
  1401. error_setg(errp, "Device doesn't support modern mode, and legacy"
  1402. " mode is disabled");
  1403. error_append_hint(errp, "Set disable-legacy to off\n");
  1404. return;
  1405. }
  1406. }
  1407. modern = virtio_pci_modern(proxy);
  1408. config = proxy->pci_dev.config;
  1409. if (proxy->class_code) {
  1410. pci_config_set_class(config, proxy->class_code);
  1411. }
  1412. if (legacy) {
  1413. if (!virtio_legacy_allowed(vdev)) {
  1414. error_setg(errp, "device is modern-only, use disable-legacy=on");
  1415. return;
  1416. }
  1417. if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
  1418. error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by"
  1419. " neither legacy nor transitional device");
  1420. return ;
  1421. }
  1422. /*
  1423. * Legacy and transitional devices use specific subsystem IDs.
  1424. * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID)
  1425. * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default.
  1426. */
  1427. pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus));
  1428. } else {
  1429. /* pure virtio-1.0 */
  1430. pci_set_word(config + PCI_VENDOR_ID,
  1431. PCI_VENDOR_ID_REDHAT_QUMRANET);
  1432. pci_set_word(config + PCI_DEVICE_ID,
  1433. 0x1040 + virtio_bus_get_vdev_id(bus));
  1434. pci_config_set_revision(config, 1);
  1435. }
  1436. config[PCI_INTERRUPT_PIN] = 1;
  1437. if (modern) {
  1438. struct virtio_pci_cap cap = {
  1439. .cap_len = sizeof cap,
  1440. };
  1441. struct virtio_pci_notify_cap notify = {
  1442. .cap.cap_len = sizeof notify,
  1443. .notify_off_multiplier =
  1444. cpu_to_le32(virtio_pci_queue_mem_mult(proxy)),
  1445. };
  1446. struct virtio_pci_cfg_cap cfg = {
  1447. .cap.cap_len = sizeof cfg,
  1448. .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
  1449. };
  1450. struct virtio_pci_notify_cap notify_pio = {
  1451. .cap.cap_len = sizeof notify,
  1452. .notify_off_multiplier = cpu_to_le32(0x0),
  1453. };
  1454. struct virtio_pci_cfg_cap *cfg_mask;
  1455. virtio_pci_modern_regions_init(proxy);
  1456. virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap);
  1457. virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap);
  1458. virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap);
  1459. virtio_pci_modern_mem_region_map(proxy, &proxy->notify, &notify.cap);
  1460. if (modern_pio) {
  1461. memory_region_init(&proxy->io_bar, OBJECT(proxy),
  1462. "virtio-pci-io", 0x4);
  1463. pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx,
  1464. PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar);
  1465. virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio,
  1466. &notify_pio.cap);
  1467. }
  1468. pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
  1469. PCI_BASE_ADDRESS_SPACE_MEMORY |
  1470. PCI_BASE_ADDRESS_MEM_PREFETCH |
  1471. PCI_BASE_ADDRESS_MEM_TYPE_64,
  1472. &proxy->modern_bar);
  1473. proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
  1474. cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
  1475. pci_set_byte(&cfg_mask->cap.bar, ~0x0);
  1476. pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
  1477. pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
  1478. pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
  1479. }
  1480. if (proxy->nvectors) {
  1481. int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
  1482. proxy->msix_bar_idx, NULL);
  1483. if (err) {
  1484. /* Notice when a system that supports MSIx can't initialize it */
  1485. if (err != -ENOTSUP) {
  1486. warn_report("unable to init msix vectors to %" PRIu32,
  1487. proxy->nvectors);
  1488. }
  1489. proxy->nvectors = 0;
  1490. }
  1491. }
  1492. proxy->pci_dev.config_write = virtio_write_config;
  1493. proxy->pci_dev.config_read = virtio_read_config;
  1494. if (legacy) {
  1495. size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
  1496. + virtio_bus_get_vdev_config_len(bus);
  1497. size = pow2ceil(size);
  1498. memory_region_init_io(&proxy->bar, OBJECT(proxy),
  1499. &virtio_pci_config_ops,
  1500. proxy, "virtio-pci", size);
  1501. pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
  1502. PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
  1503. }
  1504. }
  1505. static void virtio_pci_device_unplugged(DeviceState *d)
  1506. {
  1507. VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  1508. bool modern = virtio_pci_modern(proxy);
  1509. bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
  1510. virtio_pci_stop_ioeventfd(proxy);
  1511. if (modern) {
  1512. virtio_pci_modern_mem_region_unmap(proxy, &proxy->common);
  1513. virtio_pci_modern_mem_region_unmap(proxy, &proxy->isr);
  1514. virtio_pci_modern_mem_region_unmap(proxy, &proxy->device);
  1515. virtio_pci_modern_mem_region_unmap(proxy, &proxy->notify);
  1516. if (modern_pio) {
  1517. virtio_pci_modern_io_region_unmap(proxy, &proxy->notify_pio);
  1518. }
  1519. }
  1520. }
  1521. static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
  1522. {
  1523. VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
  1524. VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev);
  1525. bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
  1526. !pci_bus_is_root(pci_get_bus(pci_dev));
  1527. if (kvm_enabled() && !kvm_has_many_ioeventfds()) {
  1528. proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;
  1529. }
  1530. /*
  1531. * virtio pci bar layout used by default.
  1532. * subclasses can re-arrange things if needed.
  1533. *
  1534. * region 0 -- virtio legacy io bar
  1535. * region 1 -- msi-x bar
  1536. * region 2 -- virtio modern io bar (off by default)
  1537. * region 4+5 -- virtio modern memory (64bit) bar
  1538. *
  1539. */
  1540. proxy->legacy_io_bar_idx = 0;
  1541. proxy->msix_bar_idx = 1;
  1542. proxy->modern_io_bar_idx = 2;
  1543. proxy->modern_mem_bar_idx = 4;
  1544. proxy->common.offset = 0x0;
  1545. proxy->common.size = 0x1000;
  1546. proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;
  1547. proxy->isr.offset = 0x1000;
  1548. proxy->isr.size = 0x1000;
  1549. proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;
  1550. proxy->device.offset = 0x2000;
  1551. proxy->device.size = 0x1000;
  1552. proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;
  1553. proxy->notify.offset = 0x3000;
  1554. proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;
  1555. proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
  1556. proxy->notify_pio.offset = 0x0;
  1557. proxy->notify_pio.size = 0x4;
  1558. proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
  1559. /* subclasses can enforce modern, so do this unconditionally */
  1560. memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",
  1561. /* PCI BAR regions must be powers of 2 */
  1562. pow2ceil(proxy->notify.offset + proxy->notify.size));
  1563. if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {
  1564. proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
  1565. }
  1566. if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {
  1567. error_setg(errp, "device cannot work as neither modern nor legacy mode"
  1568. " is enabled");
  1569. error_append_hint(errp, "Set either disable-modern or disable-legacy"
  1570. " to off\n");
  1571. return;
  1572. }
  1573. if (pcie_port && pci_is_express(pci_dev)) {
  1574. int pos;
  1575. pos = pcie_endpoint_cap_init(pci_dev, 0);
  1576. assert(pos > 0);
  1577. pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
  1578. PCI_PM_SIZEOF, errp);
  1579. if (pos < 0) {
  1580. return;
  1581. }
  1582. pci_dev->exp.pm_cap = pos;
  1583. /*
  1584. * Indicates that this function complies with revision 1.2 of the
  1585. * PCI Power Management Interface Specification.
  1586. */
  1587. pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
  1588. if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
  1589. /* Init error enabling flags */
  1590. pcie_cap_deverr_init(pci_dev);
  1591. }
  1592. if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
  1593. /* Init Link Control Register */
  1594. pcie_cap_lnkctl_init(pci_dev);
  1595. }
  1596. if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
  1597. /* Init Power Management Control Register */
  1598. pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
  1599. PCI_PM_CTRL_STATE_MASK);
  1600. }
  1601. if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
  1602. pcie_ats_init(pci_dev, 256);
  1603. }
  1604. if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
  1605. /* Set Function Level Reset capability bit */
  1606. pcie_cap_flr_init(pci_dev);
  1607. }
  1608. } else {
  1609. /*
  1610. * make future invocations of pci_is_express() return false
  1611. * and pci_config_size() return PCI_CONFIG_SPACE_SIZE.
  1612. */
  1613. pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;
  1614. }
  1615. virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
  1616. if (k->realize) {
  1617. k->realize(proxy, errp);
  1618. }
  1619. }
  1620. static void virtio_pci_exit(PCIDevice *pci_dev)
  1621. {
  1622. msix_uninit_exclusive_bar(pci_dev);
  1623. }
  1624. static void virtio_pci_reset(DeviceState *qdev)
  1625. {
  1626. VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
  1627. VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
  1628. PCIDevice *dev = PCI_DEVICE(qdev);
  1629. int i;
  1630. virtio_pci_stop_ioeventfd(proxy);
  1631. virtio_bus_reset(bus);
  1632. msix_unuse_all_vectors(&proxy->pci_dev);
  1633. for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
  1634. proxy->vqs[i].enabled = 0;
  1635. proxy->vqs[i].num = 0;
  1636. proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0;
  1637. proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
  1638. proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
  1639. }
  1640. if (pci_is_express(dev)) {
  1641. pcie_cap_deverr_reset(dev);
  1642. pcie_cap_lnkctl_reset(dev);
  1643. pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
  1644. }
  1645. }
  1646. static Property virtio_pci_properties[] = {
  1647. DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
  1648. VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
  1649. DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
  1650. VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
  1651. DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
  1652. VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
  1653. DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
  1654. VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
  1655. DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
  1656. VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
  1657. DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
  1658. ignore_backend_features, false),
  1659. DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
  1660. VIRTIO_PCI_FLAG_ATS_BIT, false),
  1661. DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
  1662. VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
  1663. DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
  1664. VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
  1665. DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
  1666. VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
  1667. DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
  1668. VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
  1669. DEFINE_PROP_END_OF_LIST(),
  1670. };
  1671. static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
  1672. {
  1673. VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev);
  1674. VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
  1675. PCIDevice *pci_dev = &proxy->pci_dev;
  1676. if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&
  1677. virtio_pci_modern(proxy)) {
  1678. pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
  1679. }
  1680. vpciklass->parent_dc_realize(qdev, errp);
  1681. }
  1682. static void virtio_pci_class_init(ObjectClass *klass, void *data)
  1683. {
  1684. DeviceClass *dc = DEVICE_CLASS(klass);
  1685. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1686. VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
  1687. device_class_set_props(dc, virtio_pci_properties);
  1688. k->realize = virtio_pci_realize;
  1689. k->exit = virtio_pci_exit;
  1690. k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
  1691. k->revision = VIRTIO_PCI_ABI_VERSION;
  1692. k->class_id = PCI_CLASS_OTHERS;
  1693. device_class_set_parent_realize(dc, virtio_pci_dc_realize,
  1694. &vpciklass->parent_dc_realize);
  1695. dc->reset = virtio_pci_reset;
  1696. }
  1697. static const TypeInfo virtio_pci_info = {
  1698. .name = TYPE_VIRTIO_PCI,
  1699. .parent = TYPE_PCI_DEVICE,
  1700. .instance_size = sizeof(VirtIOPCIProxy),
  1701. .class_init = virtio_pci_class_init,
  1702. .class_size = sizeof(VirtioPCIClass),
  1703. .abstract = true,
  1704. };
  1705. static Property virtio_pci_generic_properties[] = {
  1706. DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy,
  1707. ON_OFF_AUTO_AUTO),
  1708. DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false),
  1709. DEFINE_PROP_END_OF_LIST(),
  1710. };
  1711. static void virtio_pci_base_class_init(ObjectClass *klass, void *data)
  1712. {
  1713. const VirtioPCIDeviceTypeInfo *t = data;
  1714. if (t->class_init) {
  1715. t->class_init(klass, NULL);
  1716. }
  1717. }
  1718. static void virtio_pci_generic_class_init(ObjectClass *klass, void *data)
  1719. {
  1720. DeviceClass *dc = DEVICE_CLASS(klass);
  1721. device_class_set_props(dc, virtio_pci_generic_properties);
  1722. }
  1723. static void virtio_pci_transitional_instance_init(Object *obj)
  1724. {
  1725. VirtIOPCIProxy *proxy = VIRTIO_PCI(obj);
  1726. proxy->disable_legacy = ON_OFF_AUTO_OFF;
  1727. proxy->disable_modern = false;
  1728. }
  1729. static void virtio_pci_non_transitional_instance_init(Object *obj)
  1730. {
  1731. VirtIOPCIProxy *proxy = VIRTIO_PCI(obj);
  1732. proxy->disable_legacy = ON_OFF_AUTO_ON;
  1733. proxy->disable_modern = false;
  1734. }
  1735. void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t)
  1736. {
  1737. char *base_name = NULL;
  1738. TypeInfo base_type_info = {
  1739. .name = t->base_name,
  1740. .parent = t->parent ? t->parent : TYPE_VIRTIO_PCI,
  1741. .instance_size = t->instance_size,
  1742. .instance_init = t->instance_init,
  1743. .class_size = t->class_size,
  1744. .abstract = true,
  1745. .interfaces = t->interfaces,
  1746. };
  1747. TypeInfo generic_type_info = {
  1748. .name = t->generic_name,
  1749. .parent = base_type_info.name,
  1750. .class_init = virtio_pci_generic_class_init,
  1751. .interfaces = (InterfaceInfo[]) {
  1752. { INTERFACE_PCIE_DEVICE },
  1753. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1754. { }
  1755. },
  1756. };
  1757. if (!base_type_info.name) {
  1758. /* No base type -> register a single generic device type */
  1759. /* use intermediate %s-base-type to add generic device props */
  1760. base_name = g_strdup_printf("%s-base-type", t->generic_name);
  1761. base_type_info.name = base_name;
  1762. base_type_info.class_init = virtio_pci_generic_class_init;
  1763. generic_type_info.parent = base_name;
  1764. generic_type_info.class_init = virtio_pci_base_class_init;
  1765. generic_type_info.class_data = (void *)t;
  1766. assert(!t->non_transitional_name);
  1767. assert(!t->transitional_name);
  1768. } else {
  1769. base_type_info.class_init = virtio_pci_base_class_init;
  1770. base_type_info.class_data = (void *)t;
  1771. }
  1772. type_register(&base_type_info);
  1773. if (generic_type_info.name) {
  1774. type_register(&generic_type_info);
  1775. }
  1776. if (t->non_transitional_name) {
  1777. const TypeInfo non_transitional_type_info = {
  1778. .name = t->non_transitional_name,
  1779. .parent = base_type_info.name,
  1780. .instance_init = virtio_pci_non_transitional_instance_init,
  1781. .interfaces = (InterfaceInfo[]) {
  1782. { INTERFACE_PCIE_DEVICE },
  1783. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1784. { }
  1785. },
  1786. };
  1787. type_register(&non_transitional_type_info);
  1788. }
  1789. if (t->transitional_name) {
  1790. const TypeInfo transitional_type_info = {
  1791. .name = t->transitional_name,
  1792. .parent = base_type_info.name,
  1793. .instance_init = virtio_pci_transitional_instance_init,
  1794. .interfaces = (InterfaceInfo[]) {
  1795. /*
  1796. * Transitional virtio devices work only as Conventional PCI
  1797. * devices because they require PIO ports.
  1798. */
  1799. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1800. { }
  1801. },
  1802. };
  1803. type_register(&transitional_type_info);
  1804. }
  1805. g_free(base_name);
  1806. }
  1807. /* virtio-pci-bus */
  1808. static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
  1809. VirtIOPCIProxy *dev)
  1810. {
  1811. DeviceState *qdev = DEVICE(dev);
  1812. char virtio_bus_name[] = "virtio-bus";
  1813. qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
  1814. virtio_bus_name);
  1815. }
  1816. static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
  1817. {
  1818. BusClass *bus_class = BUS_CLASS(klass);
  1819. VirtioBusClass *k = VIRTIO_BUS_CLASS(klass);
  1820. bus_class->max_dev = 1;
  1821. k->notify = virtio_pci_notify;
  1822. k->save_config = virtio_pci_save_config;
  1823. k->load_config = virtio_pci_load_config;
  1824. k->save_queue = virtio_pci_save_queue;
  1825. k->load_queue = virtio_pci_load_queue;
  1826. k->save_extra_state = virtio_pci_save_extra_state;
  1827. k->load_extra_state = virtio_pci_load_extra_state;
  1828. k->has_extra_state = virtio_pci_has_extra_state;
  1829. k->query_guest_notifiers = virtio_pci_query_guest_notifiers;
  1830. k->set_guest_notifiers = virtio_pci_set_guest_notifiers;
  1831. k->set_host_notifier_mr = virtio_pci_set_host_notifier_mr;
  1832. k->vmstate_change = virtio_pci_vmstate_change;
  1833. k->pre_plugged = virtio_pci_pre_plugged;
  1834. k->device_plugged = virtio_pci_device_plugged;
  1835. k->device_unplugged = virtio_pci_device_unplugged;
  1836. k->query_nvectors = virtio_pci_query_nvectors;
  1837. k->ioeventfd_enabled = virtio_pci_ioeventfd_enabled;
  1838. k->ioeventfd_assign = virtio_pci_ioeventfd_assign;
  1839. k->get_dma_as = virtio_pci_get_dma_as;
  1840. k->queue_enabled = virtio_pci_queue_enabled;
  1841. }
  1842. static const TypeInfo virtio_pci_bus_info = {
  1843. .name = TYPE_VIRTIO_PCI_BUS,
  1844. .parent = TYPE_VIRTIO_BUS,
  1845. .instance_size = sizeof(VirtioPCIBusState),
  1846. .class_init = virtio_pci_bus_class_init,
  1847. };
  1848. static void virtio_pci_register_types(void)
  1849. {
  1850. /* Base types: */
  1851. type_register_static(&virtio_pci_bus_info);
  1852. type_register_static(&virtio_pci_info);
  1853. }
  1854. type_init(virtio_pci_register_types)