sd.c 63 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217
  1. /*
  2. * SD Memory Card emulation as defined in the "SD Memory Card Physical
  3. * layer specification, Version 2.00."
  4. *
  5. * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
  6. * Copyright (c) 2007 CodeSourcery
  7. * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. *
  13. * 1. Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in
  17. * the documentation and/or other materials provided with the
  18. * distribution.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  21. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  23. * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
  24. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  27. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  28. * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #include "qemu/osdep.h"
  33. #include "qemu/units.h"
  34. #include "qemu/cutils.h"
  35. #include "hw/irq.h"
  36. #include "hw/registerfields.h"
  37. #include "sysemu/block-backend.h"
  38. #include "hw/sd/sd.h"
  39. #include "migration/vmstate.h"
  40. #include "qapi/error.h"
  41. #include "qemu/bitmap.h"
  42. #include "hw/qdev-properties.h"
  43. #include "qemu/error-report.h"
  44. #include "qemu/timer.h"
  45. #include "qemu/log.h"
  46. #include "qemu/module.h"
  47. #include "sdmmc-internal.h"
  48. #include "trace.h"
  49. //#define DEBUG_SD 1
  50. typedef enum {
  51. sd_r0 = 0, /* no response */
  52. sd_r1, /* normal response command */
  53. sd_r2_i, /* CID register */
  54. sd_r2_s, /* CSD register */
  55. sd_r3, /* OCR register */
  56. sd_r6 = 6, /* Published RCA response */
  57. sd_r7, /* Operating voltage */
  58. sd_r1b = -1,
  59. sd_illegal = -2,
  60. } sd_rsp_type_t;
  61. enum SDCardModes {
  62. sd_inactive,
  63. sd_card_identification_mode,
  64. sd_data_transfer_mode,
  65. };
  66. enum SDCardStates {
  67. sd_inactive_state = -1,
  68. sd_idle_state = 0,
  69. sd_ready_state,
  70. sd_identification_state,
  71. sd_standby_state,
  72. sd_transfer_state,
  73. sd_sendingdata_state,
  74. sd_receivingdata_state,
  75. sd_programming_state,
  76. sd_disconnect_state,
  77. };
  78. struct SDState {
  79. DeviceState parent_obj;
  80. /* If true, created by sd_init() for a non-qdevified caller */
  81. /* TODO purge them with fire */
  82. bool me_no_qdev_me_kill_mammoth_with_rocks;
  83. /* SD Memory Card Registers */
  84. uint32_t ocr;
  85. uint8_t scr[8];
  86. uint8_t cid[16];
  87. uint8_t csd[16];
  88. uint16_t rca;
  89. uint32_t card_status;
  90. uint8_t sd_status[64];
  91. /* Configurable properties */
  92. uint8_t spec_version;
  93. BlockBackend *blk;
  94. bool spi;
  95. uint32_t mode; /* current card mode, one of SDCardModes */
  96. int32_t state; /* current card state, one of SDCardStates */
  97. uint32_t vhs;
  98. bool wp_switch;
  99. unsigned long *wp_groups;
  100. int32_t wpgrps_size;
  101. uint64_t size;
  102. uint32_t blk_len;
  103. uint32_t multi_blk_cnt;
  104. uint32_t erase_start;
  105. uint32_t erase_end;
  106. uint8_t pwd[16];
  107. uint32_t pwd_len;
  108. uint8_t function_group[6];
  109. uint8_t current_cmd;
  110. /* True if we will handle the next command as an ACMD. Note that this does
  111. * *not* track the APP_CMD status bit!
  112. */
  113. bool expecting_acmd;
  114. uint32_t blk_written;
  115. uint64_t data_start;
  116. uint32_t data_offset;
  117. uint8_t data[512];
  118. qemu_irq readonly_cb;
  119. qemu_irq inserted_cb;
  120. QEMUTimer *ocr_power_timer;
  121. const char *proto_name;
  122. bool enable;
  123. uint8_t dat_lines;
  124. bool cmd_line;
  125. };
  126. static void sd_realize(DeviceState *dev, Error **errp);
  127. static const char *sd_state_name(enum SDCardStates state)
  128. {
  129. static const char *state_name[] = {
  130. [sd_idle_state] = "idle",
  131. [sd_ready_state] = "ready",
  132. [sd_identification_state] = "identification",
  133. [sd_standby_state] = "standby",
  134. [sd_transfer_state] = "transfer",
  135. [sd_sendingdata_state] = "sendingdata",
  136. [sd_receivingdata_state] = "receivingdata",
  137. [sd_programming_state] = "programming",
  138. [sd_disconnect_state] = "disconnect",
  139. };
  140. if (state == sd_inactive_state) {
  141. return "inactive";
  142. }
  143. assert(state < ARRAY_SIZE(state_name));
  144. return state_name[state];
  145. }
  146. static const char *sd_response_name(sd_rsp_type_t rsp)
  147. {
  148. static const char *response_name[] = {
  149. [sd_r0] = "RESP#0 (no response)",
  150. [sd_r1] = "RESP#1 (normal cmd)",
  151. [sd_r2_i] = "RESP#2 (CID reg)",
  152. [sd_r2_s] = "RESP#2 (CSD reg)",
  153. [sd_r3] = "RESP#3 (OCR reg)",
  154. [sd_r6] = "RESP#6 (RCA)",
  155. [sd_r7] = "RESP#7 (operating voltage)",
  156. };
  157. if (rsp == sd_illegal) {
  158. return "ILLEGAL RESP";
  159. }
  160. if (rsp == sd_r1b) {
  161. rsp = sd_r1;
  162. }
  163. assert(rsp < ARRAY_SIZE(response_name));
  164. return response_name[rsp];
  165. }
  166. static uint8_t sd_get_dat_lines(SDState *sd)
  167. {
  168. return sd->enable ? sd->dat_lines : 0;
  169. }
  170. static bool sd_get_cmd_line(SDState *sd)
  171. {
  172. return sd->enable ? sd->cmd_line : false;
  173. }
  174. static void sd_set_voltage(SDState *sd, uint16_t millivolts)
  175. {
  176. trace_sdcard_set_voltage(millivolts);
  177. switch (millivolts) {
  178. case 3001 ... 3600: /* SD_VOLTAGE_3_3V */
  179. case 2001 ... 3000: /* SD_VOLTAGE_3_0V */
  180. break;
  181. default:
  182. qemu_log_mask(LOG_GUEST_ERROR, "SD card voltage not supported: %.3fV",
  183. millivolts / 1000.f);
  184. }
  185. }
  186. static void sd_set_mode(SDState *sd)
  187. {
  188. switch (sd->state) {
  189. case sd_inactive_state:
  190. sd->mode = sd_inactive;
  191. break;
  192. case sd_idle_state:
  193. case sd_ready_state:
  194. case sd_identification_state:
  195. sd->mode = sd_card_identification_mode;
  196. break;
  197. case sd_standby_state:
  198. case sd_transfer_state:
  199. case sd_sendingdata_state:
  200. case sd_receivingdata_state:
  201. case sd_programming_state:
  202. case sd_disconnect_state:
  203. sd->mode = sd_data_transfer_mode;
  204. break;
  205. }
  206. }
  207. static const sd_cmd_type_t sd_cmd_type[SDMMC_CMD_MAX] = {
  208. sd_bc, sd_none, sd_bcr, sd_bcr, sd_none, sd_none, sd_none, sd_ac,
  209. sd_bcr, sd_ac, sd_ac, sd_adtc, sd_ac, sd_ac, sd_none, sd_ac,
  210. /* 16 */
  211. sd_ac, sd_adtc, sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none,
  212. sd_adtc, sd_adtc, sd_adtc, sd_adtc, sd_ac, sd_ac, sd_adtc, sd_none,
  213. /* 32 */
  214. sd_ac, sd_ac, sd_none, sd_none, sd_none, sd_none, sd_ac, sd_none,
  215. sd_none, sd_none, sd_bc, sd_none, sd_none, sd_none, sd_none, sd_none,
  216. /* 48 */
  217. sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_ac,
  218. sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none,
  219. };
  220. static const int sd_cmd_class[SDMMC_CMD_MAX] = {
  221. 0, 0, 0, 0, 0, 9, 10, 0, 0, 0, 0, 1, 0, 0, 0, 0,
  222. 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6,
  223. 5, 5, 10, 10, 10, 10, 5, 9, 9, 9, 7, 7, 7, 7, 7, 7,
  224. 7, 7, 10, 7, 9, 9, 9, 8, 8, 10, 8, 8, 8, 8, 8, 8,
  225. };
  226. static uint8_t sd_crc7(void *message, size_t width)
  227. {
  228. int i, bit;
  229. uint8_t shift_reg = 0x00;
  230. uint8_t *msg = (uint8_t *) message;
  231. for (i = 0; i < width; i ++, msg ++)
  232. for (bit = 7; bit >= 0; bit --) {
  233. shift_reg <<= 1;
  234. if ((shift_reg >> 7) ^ ((*msg >> bit) & 1))
  235. shift_reg ^= 0x89;
  236. }
  237. return shift_reg;
  238. }
  239. static uint16_t sd_crc16(void *message, size_t width)
  240. {
  241. int i, bit;
  242. uint16_t shift_reg = 0x0000;
  243. uint16_t *msg = (uint16_t *) message;
  244. width <<= 1;
  245. for (i = 0; i < width; i ++, msg ++)
  246. for (bit = 15; bit >= 0; bit --) {
  247. shift_reg <<= 1;
  248. if ((shift_reg >> 15) ^ ((*msg >> bit) & 1))
  249. shift_reg ^= 0x1011;
  250. }
  251. return shift_reg;
  252. }
  253. #define OCR_POWER_DELAY_NS 500000 /* 0.5ms */
  254. FIELD(OCR, VDD_VOLTAGE_WINDOW, 0, 24)
  255. FIELD(OCR, VDD_VOLTAGE_WIN_LO, 0, 8)
  256. FIELD(OCR, DUAL_VOLTAGE_CARD, 7, 1)
  257. FIELD(OCR, VDD_VOLTAGE_WIN_HI, 8, 16)
  258. FIELD(OCR, ACCEPT_SWITCH_1V8, 24, 1) /* Only UHS-I */
  259. FIELD(OCR, UHS_II_CARD, 29, 1) /* Only UHS-II */
  260. FIELD(OCR, CARD_CAPACITY, 30, 1) /* 0:SDSC, 1:SDHC/SDXC */
  261. FIELD(OCR, CARD_POWER_UP, 31, 1)
  262. #define ACMD41_ENQUIRY_MASK 0x00ffffff
  263. #define ACMD41_R3_MASK (R_OCR_VDD_VOLTAGE_WIN_HI_MASK \
  264. | R_OCR_ACCEPT_SWITCH_1V8_MASK \
  265. | R_OCR_UHS_II_CARD_MASK \
  266. | R_OCR_CARD_CAPACITY_MASK \
  267. | R_OCR_CARD_POWER_UP_MASK)
  268. static void sd_set_ocr(SDState *sd)
  269. {
  270. /* All voltages OK */
  271. sd->ocr = R_OCR_VDD_VOLTAGE_WIN_HI_MASK;
  272. }
  273. static void sd_ocr_powerup(void *opaque)
  274. {
  275. SDState *sd = opaque;
  276. trace_sdcard_powerup();
  277. assert(!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP));
  278. /* card power-up OK */
  279. sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
  280. if (sd->size > 1 * GiB) {
  281. sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
  282. }
  283. }
  284. static void sd_set_scr(SDState *sd)
  285. {
  286. sd->scr[0] = 0 << 4; /* SCR structure version 1.0 */
  287. if (sd->spec_version == SD_PHY_SPECv1_10_VERS) {
  288. sd->scr[0] |= 1; /* Spec Version 1.10 */
  289. } else {
  290. sd->scr[0] |= 2; /* Spec Version 2.00 or Version 3.0X */
  291. }
  292. sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
  293. | 0b0101; /* 1-bit or 4-bit width bus modes */
  294. sd->scr[2] = 0x00; /* Extended Security is not supported. */
  295. if (sd->spec_version >= SD_PHY_SPECv3_01_VERS) {
  296. sd->scr[2] |= 1 << 7; /* Spec Version 3.0X */
  297. }
  298. sd->scr[3] = 0x00;
  299. /* reserved for manufacturer usage */
  300. sd->scr[4] = 0x00;
  301. sd->scr[5] = 0x00;
  302. sd->scr[6] = 0x00;
  303. sd->scr[7] = 0x00;
  304. }
  305. #define MID 0xaa
  306. #define OID "XY"
  307. #define PNM "QEMU!"
  308. #define PRV 0x01
  309. #define MDT_YR 2006
  310. #define MDT_MON 2
  311. static void sd_set_cid(SDState *sd)
  312. {
  313. sd->cid[0] = MID; /* Fake card manufacturer ID (MID) */
  314. sd->cid[1] = OID[0]; /* OEM/Application ID (OID) */
  315. sd->cid[2] = OID[1];
  316. sd->cid[3] = PNM[0]; /* Fake product name (PNM) */
  317. sd->cid[4] = PNM[1];
  318. sd->cid[5] = PNM[2];
  319. sd->cid[6] = PNM[3];
  320. sd->cid[7] = PNM[4];
  321. sd->cid[8] = PRV; /* Fake product revision (PRV) */
  322. sd->cid[9] = 0xde; /* Fake serial number (PSN) */
  323. sd->cid[10] = 0xad;
  324. sd->cid[11] = 0xbe;
  325. sd->cid[12] = 0xef;
  326. sd->cid[13] = 0x00 | /* Manufacture date (MDT) */
  327. ((MDT_YR - 2000) / 10);
  328. sd->cid[14] = ((MDT_YR % 10) << 4) | MDT_MON;
  329. sd->cid[15] = (sd_crc7(sd->cid, 15) << 1) | 1;
  330. }
  331. #define HWBLOCK_SHIFT 9 /* 512 bytes */
  332. #define SECTOR_SHIFT 5 /* 16 kilobytes */
  333. #define WPGROUP_SHIFT 7 /* 2 megs */
  334. #define CMULT_SHIFT 9 /* 512 times HWBLOCK_SIZE */
  335. #define WPGROUP_SIZE (1 << (HWBLOCK_SHIFT + SECTOR_SHIFT + WPGROUP_SHIFT))
  336. static const uint8_t sd_csd_rw_mask[16] = {
  337. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  338. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xfe,
  339. };
  340. static void sd_set_csd(SDState *sd, uint64_t size)
  341. {
  342. uint32_t csize = (size >> (CMULT_SHIFT + HWBLOCK_SHIFT)) - 1;
  343. uint32_t sectsize = (1 << (SECTOR_SHIFT + 1)) - 1;
  344. uint32_t wpsize = (1 << (WPGROUP_SHIFT + 1)) - 1;
  345. if (size <= 1 * GiB) { /* Standard Capacity SD */
  346. sd->csd[0] = 0x00; /* CSD structure */
  347. sd->csd[1] = 0x26; /* Data read access-time-1 */
  348. sd->csd[2] = 0x00; /* Data read access-time-2 */
  349. sd->csd[3] = 0x32; /* Max. data transfer rate: 25 MHz */
  350. sd->csd[4] = 0x5f; /* Card Command Classes */
  351. sd->csd[5] = 0x50 | /* Max. read data block length */
  352. HWBLOCK_SHIFT;
  353. sd->csd[6] = 0xe0 | /* Partial block for read allowed */
  354. ((csize >> 10) & 0x03);
  355. sd->csd[7] = 0x00 | /* Device size */
  356. ((csize >> 2) & 0xff);
  357. sd->csd[8] = 0x3f | /* Max. read current */
  358. ((csize << 6) & 0xc0);
  359. sd->csd[9] = 0xfc | /* Max. write current */
  360. ((CMULT_SHIFT - 2) >> 1);
  361. sd->csd[10] = 0x40 | /* Erase sector size */
  362. (((CMULT_SHIFT - 2) << 7) & 0x80) | (sectsize >> 1);
  363. sd->csd[11] = 0x00 | /* Write protect group size */
  364. ((sectsize << 7) & 0x80) | wpsize;
  365. sd->csd[12] = 0x90 | /* Write speed factor */
  366. (HWBLOCK_SHIFT >> 2);
  367. sd->csd[13] = 0x20 | /* Max. write data block length */
  368. ((HWBLOCK_SHIFT << 6) & 0xc0);
  369. sd->csd[14] = 0x00; /* File format group */
  370. } else { /* SDHC */
  371. size /= 512 * KiB;
  372. size -= 1;
  373. sd->csd[0] = 0x40;
  374. sd->csd[1] = 0x0e;
  375. sd->csd[2] = 0x00;
  376. sd->csd[3] = 0x32;
  377. sd->csd[4] = 0x5b;
  378. sd->csd[5] = 0x59;
  379. sd->csd[6] = 0x00;
  380. sd->csd[7] = (size >> 16) & 0xff;
  381. sd->csd[8] = (size >> 8) & 0xff;
  382. sd->csd[9] = (size & 0xff);
  383. sd->csd[10] = 0x7f;
  384. sd->csd[11] = 0x80;
  385. sd->csd[12] = 0x0a;
  386. sd->csd[13] = 0x40;
  387. sd->csd[14] = 0x00;
  388. }
  389. sd->csd[15] = (sd_crc7(sd->csd, 15) << 1) | 1;
  390. }
  391. static void sd_set_rca(SDState *sd)
  392. {
  393. sd->rca += 0x4567;
  394. }
  395. FIELD(CSR, AKE_SEQ_ERROR, 3, 1)
  396. FIELD(CSR, APP_CMD, 5, 1)
  397. FIELD(CSR, FX_EVENT, 6, 1)
  398. FIELD(CSR, READY_FOR_DATA, 8, 1)
  399. FIELD(CSR, CURRENT_STATE, 9, 4)
  400. FIELD(CSR, ERASE_RESET, 13, 1)
  401. FIELD(CSR, CARD_ECC_DISABLED, 14, 1)
  402. FIELD(CSR, WP_ERASE_SKIP, 15, 1)
  403. FIELD(CSR, CSD_OVERWRITE, 16, 1)
  404. FIELD(CSR, DEFERRED_RESPONSE, 17, 1)
  405. FIELD(CSR, ERROR, 19, 1)
  406. FIELD(CSR, CC_ERROR, 20, 1)
  407. FIELD(CSR, CARD_ECC_FAILED, 21, 1)
  408. FIELD(CSR, ILLEGAL_COMMAND, 22, 1)
  409. FIELD(CSR, COM_CRC_ERROR, 23, 1)
  410. FIELD(CSR, LOCK_UNLOCK_FAILED, 24, 1)
  411. FIELD(CSR, CARD_IS_LOCKED, 25, 1)
  412. FIELD(CSR, WP_VIOLATION, 26, 1)
  413. FIELD(CSR, ERASE_PARAM, 27, 1)
  414. FIELD(CSR, ERASE_SEQ_ERROR, 28, 1)
  415. FIELD(CSR, BLOCK_LEN_ERROR, 29, 1)
  416. FIELD(CSR, ADDRESS_ERROR, 30, 1)
  417. FIELD(CSR, OUT_OF_RANGE, 31, 1)
  418. /* Card status bits, split by clear condition:
  419. * A : According to the card current state
  420. * B : Always related to the previous command
  421. * C : Cleared by read
  422. */
  423. #define CARD_STATUS_A (R_CSR_READY_FOR_DATA_MASK \
  424. | R_CSR_CARD_ECC_DISABLED_MASK \
  425. | R_CSR_CARD_IS_LOCKED_MASK)
  426. #define CARD_STATUS_B (R_CSR_CURRENT_STATE_MASK \
  427. | R_CSR_ILLEGAL_COMMAND_MASK \
  428. | R_CSR_COM_CRC_ERROR_MASK)
  429. #define CARD_STATUS_C (R_CSR_AKE_SEQ_ERROR_MASK \
  430. | R_CSR_APP_CMD_MASK \
  431. | R_CSR_ERASE_RESET_MASK \
  432. | R_CSR_WP_ERASE_SKIP_MASK \
  433. | R_CSR_CSD_OVERWRITE_MASK \
  434. | R_CSR_ERROR_MASK \
  435. | R_CSR_CC_ERROR_MASK \
  436. | R_CSR_CARD_ECC_FAILED_MASK \
  437. | R_CSR_LOCK_UNLOCK_FAILED_MASK \
  438. | R_CSR_WP_VIOLATION_MASK \
  439. | R_CSR_ERASE_PARAM_MASK \
  440. | R_CSR_ERASE_SEQ_ERROR_MASK \
  441. | R_CSR_BLOCK_LEN_ERROR_MASK \
  442. | R_CSR_ADDRESS_ERROR_MASK \
  443. | R_CSR_OUT_OF_RANGE_MASK)
  444. static void sd_set_cardstatus(SDState *sd)
  445. {
  446. sd->card_status = 0x00000100;
  447. }
  448. static void sd_set_sdstatus(SDState *sd)
  449. {
  450. memset(sd->sd_status, 0, 64);
  451. }
  452. static int sd_req_crc_validate(SDRequest *req)
  453. {
  454. uint8_t buffer[5];
  455. buffer[0] = 0x40 | req->cmd;
  456. stl_be_p(&buffer[1], req->arg);
  457. return 0;
  458. return sd_crc7(buffer, 5) != req->crc; /* TODO */
  459. }
  460. static void sd_response_r1_make(SDState *sd, uint8_t *response)
  461. {
  462. stl_be_p(response, sd->card_status);
  463. /* Clear the "clear on read" status bits */
  464. sd->card_status &= ~CARD_STATUS_C;
  465. }
  466. static void sd_response_r3_make(SDState *sd, uint8_t *response)
  467. {
  468. stl_be_p(response, sd->ocr & ACMD41_R3_MASK);
  469. }
  470. static void sd_response_r6_make(SDState *sd, uint8_t *response)
  471. {
  472. uint16_t status;
  473. status = ((sd->card_status >> 8) & 0xc000) |
  474. ((sd->card_status >> 6) & 0x2000) |
  475. (sd->card_status & 0x1fff);
  476. sd->card_status &= ~(CARD_STATUS_C & 0xc81fff);
  477. stw_be_p(response + 0, sd->rca);
  478. stw_be_p(response + 2, status);
  479. }
  480. static void sd_response_r7_make(SDState *sd, uint8_t *response)
  481. {
  482. stl_be_p(response, sd->vhs);
  483. }
  484. static inline uint64_t sd_addr_to_wpnum(uint64_t addr)
  485. {
  486. return addr >> (HWBLOCK_SHIFT + SECTOR_SHIFT + WPGROUP_SHIFT);
  487. }
  488. static void sd_reset(DeviceState *dev)
  489. {
  490. SDState *sd = SD_CARD(dev);
  491. uint64_t size;
  492. uint64_t sect;
  493. trace_sdcard_reset();
  494. if (sd->blk) {
  495. blk_get_geometry(sd->blk, &sect);
  496. } else {
  497. sect = 0;
  498. }
  499. size = sect << 9;
  500. sect = sd_addr_to_wpnum(size) + 1;
  501. sd->state = sd_idle_state;
  502. sd->rca = 0x0000;
  503. sd_set_ocr(sd);
  504. sd_set_scr(sd);
  505. sd_set_cid(sd);
  506. sd_set_csd(sd, size);
  507. sd_set_cardstatus(sd);
  508. sd_set_sdstatus(sd);
  509. g_free(sd->wp_groups);
  510. sd->wp_switch = sd->blk ? blk_is_read_only(sd->blk) : false;
  511. sd->wpgrps_size = sect;
  512. sd->wp_groups = bitmap_new(sd->wpgrps_size);
  513. memset(sd->function_group, 0, sizeof(sd->function_group));
  514. sd->erase_start = 0;
  515. sd->erase_end = 0;
  516. sd->size = size;
  517. sd->blk_len = 0x200;
  518. sd->pwd_len = 0;
  519. sd->expecting_acmd = false;
  520. sd->dat_lines = 0xf;
  521. sd->cmd_line = true;
  522. sd->multi_blk_cnt = 0;
  523. }
  524. static bool sd_get_inserted(SDState *sd)
  525. {
  526. return sd->blk && blk_is_inserted(sd->blk);
  527. }
  528. static bool sd_get_readonly(SDState *sd)
  529. {
  530. return sd->wp_switch;
  531. }
  532. static void sd_cardchange(void *opaque, bool load, Error **errp)
  533. {
  534. SDState *sd = opaque;
  535. DeviceState *dev = DEVICE(sd);
  536. SDBus *sdbus;
  537. bool inserted = sd_get_inserted(sd);
  538. bool readonly = sd_get_readonly(sd);
  539. if (inserted) {
  540. trace_sdcard_inserted(readonly);
  541. sd_reset(dev);
  542. } else {
  543. trace_sdcard_ejected();
  544. }
  545. if (sd->me_no_qdev_me_kill_mammoth_with_rocks) {
  546. qemu_set_irq(sd->inserted_cb, inserted);
  547. if (inserted) {
  548. qemu_set_irq(sd->readonly_cb, readonly);
  549. }
  550. } else {
  551. sdbus = SD_BUS(qdev_get_parent_bus(dev));
  552. sdbus_set_inserted(sdbus, inserted);
  553. if (inserted) {
  554. sdbus_set_readonly(sdbus, readonly);
  555. }
  556. }
  557. }
  558. static const BlockDevOps sd_block_ops = {
  559. .change_media_cb = sd_cardchange,
  560. };
  561. static bool sd_ocr_vmstate_needed(void *opaque)
  562. {
  563. SDState *sd = opaque;
  564. /* Include the OCR state (and timer) if it is not yet powered up */
  565. return !FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP);
  566. }
  567. static const VMStateDescription sd_ocr_vmstate = {
  568. .name = "sd-card/ocr-state",
  569. .version_id = 1,
  570. .minimum_version_id = 1,
  571. .needed = sd_ocr_vmstate_needed,
  572. .fields = (VMStateField[]) {
  573. VMSTATE_UINT32(ocr, SDState),
  574. VMSTATE_TIMER_PTR(ocr_power_timer, SDState),
  575. VMSTATE_END_OF_LIST()
  576. },
  577. };
  578. static int sd_vmstate_pre_load(void *opaque)
  579. {
  580. SDState *sd = opaque;
  581. /* If the OCR state is not included (prior versions, or not
  582. * needed), then the OCR must be set as powered up. If the OCR state
  583. * is included, this will be replaced by the state restore.
  584. */
  585. sd_ocr_powerup(sd);
  586. return 0;
  587. }
  588. static const VMStateDescription sd_vmstate = {
  589. .name = "sd-card",
  590. .version_id = 1,
  591. .minimum_version_id = 1,
  592. .pre_load = sd_vmstate_pre_load,
  593. .fields = (VMStateField[]) {
  594. VMSTATE_UINT32(mode, SDState),
  595. VMSTATE_INT32(state, SDState),
  596. VMSTATE_UINT8_ARRAY(cid, SDState, 16),
  597. VMSTATE_UINT8_ARRAY(csd, SDState, 16),
  598. VMSTATE_UINT16(rca, SDState),
  599. VMSTATE_UINT32(card_status, SDState),
  600. VMSTATE_PARTIAL_BUFFER(sd_status, SDState, 1),
  601. VMSTATE_UINT32(vhs, SDState),
  602. VMSTATE_BITMAP(wp_groups, SDState, 0, wpgrps_size),
  603. VMSTATE_UINT32(blk_len, SDState),
  604. VMSTATE_UINT32(multi_blk_cnt, SDState),
  605. VMSTATE_UINT32(erase_start, SDState),
  606. VMSTATE_UINT32(erase_end, SDState),
  607. VMSTATE_UINT8_ARRAY(pwd, SDState, 16),
  608. VMSTATE_UINT32(pwd_len, SDState),
  609. VMSTATE_UINT8_ARRAY(function_group, SDState, 6),
  610. VMSTATE_UINT8(current_cmd, SDState),
  611. VMSTATE_BOOL(expecting_acmd, SDState),
  612. VMSTATE_UINT32(blk_written, SDState),
  613. VMSTATE_UINT64(data_start, SDState),
  614. VMSTATE_UINT32(data_offset, SDState),
  615. VMSTATE_UINT8_ARRAY(data, SDState, 512),
  616. VMSTATE_UNUSED_V(1, 512),
  617. VMSTATE_BOOL(enable, SDState),
  618. VMSTATE_END_OF_LIST()
  619. },
  620. .subsections = (const VMStateDescription*[]) {
  621. &sd_ocr_vmstate,
  622. NULL
  623. },
  624. };
  625. /* Legacy initialization function for use by non-qdevified callers */
  626. SDState *sd_init(BlockBackend *blk, bool is_spi)
  627. {
  628. Object *obj;
  629. DeviceState *dev;
  630. SDState *sd;
  631. Error *err = NULL;
  632. obj = object_new(TYPE_SD_CARD);
  633. dev = DEVICE(obj);
  634. if (!qdev_prop_set_drive_err(dev, "drive", blk, &err)) {
  635. error_reportf_err(err, "sd_init failed: ");
  636. return NULL;
  637. }
  638. qdev_prop_set_bit(dev, "spi", is_spi);
  639. /*
  640. * Realizing the device properly would put it into the QOM
  641. * composition tree even though it is not plugged into an
  642. * appropriate bus. That's a no-no. Hide the device from
  643. * QOM/qdev, and call its qdev realize callback directly.
  644. */
  645. object_ref(obj);
  646. object_unparent(obj);
  647. sd_realize(dev, &err);
  648. if (err) {
  649. error_reportf_err(err, "sd_init failed: ");
  650. return NULL;
  651. }
  652. sd = SD_CARD(dev);
  653. sd->me_no_qdev_me_kill_mammoth_with_rocks = true;
  654. return sd;
  655. }
  656. void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert)
  657. {
  658. sd->readonly_cb = readonly;
  659. sd->inserted_cb = insert;
  660. qemu_set_irq(readonly, sd->blk ? blk_is_read_only(sd->blk) : 0);
  661. qemu_set_irq(insert, sd->blk ? blk_is_inserted(sd->blk) : 0);
  662. }
  663. static void sd_erase(SDState *sd)
  664. {
  665. int i;
  666. uint64_t erase_start = sd->erase_start;
  667. uint64_t erase_end = sd->erase_end;
  668. trace_sdcard_erase();
  669. if (!sd->erase_start || !sd->erase_end) {
  670. sd->card_status |= ERASE_SEQ_ERROR;
  671. return;
  672. }
  673. if (FIELD_EX32(sd->ocr, OCR, CARD_CAPACITY)) {
  674. /* High capacity memory card: erase units are 512 byte blocks */
  675. erase_start *= 512;
  676. erase_end *= 512;
  677. }
  678. erase_start = sd_addr_to_wpnum(erase_start);
  679. erase_end = sd_addr_to_wpnum(erase_end);
  680. sd->erase_start = 0;
  681. sd->erase_end = 0;
  682. sd->csd[14] |= 0x40;
  683. for (i = erase_start; i <= erase_end; i++) {
  684. if (test_bit(i, sd->wp_groups)) {
  685. sd->card_status |= WP_ERASE_SKIP;
  686. }
  687. }
  688. }
  689. static uint32_t sd_wpbits(SDState *sd, uint64_t addr)
  690. {
  691. uint32_t i, wpnum;
  692. uint32_t ret = 0;
  693. wpnum = sd_addr_to_wpnum(addr);
  694. for (i = 0; i < 32; i++, wpnum++, addr += WPGROUP_SIZE) {
  695. if (addr < sd->size && test_bit(wpnum, sd->wp_groups)) {
  696. ret |= (1 << i);
  697. }
  698. }
  699. return ret;
  700. }
  701. static void sd_function_switch(SDState *sd, uint32_t arg)
  702. {
  703. int i, mode, new_func;
  704. mode = !!(arg & 0x80000000);
  705. sd->data[0] = 0x00; /* Maximum current consumption */
  706. sd->data[1] = 0x01;
  707. sd->data[2] = 0x80; /* Supported group 6 functions */
  708. sd->data[3] = 0x01;
  709. sd->data[4] = 0x80; /* Supported group 5 functions */
  710. sd->data[5] = 0x01;
  711. sd->data[6] = 0x80; /* Supported group 4 functions */
  712. sd->data[7] = 0x01;
  713. sd->data[8] = 0x80; /* Supported group 3 functions */
  714. sd->data[9] = 0x01;
  715. sd->data[10] = 0x80; /* Supported group 2 functions */
  716. sd->data[11] = 0x43;
  717. sd->data[12] = 0x80; /* Supported group 1 functions */
  718. sd->data[13] = 0x03;
  719. for (i = 0; i < 6; i ++) {
  720. new_func = (arg >> (i * 4)) & 0x0f;
  721. if (mode && new_func != 0x0f)
  722. sd->function_group[i] = new_func;
  723. sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
  724. }
  725. memset(&sd->data[17], 0, 47);
  726. stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
  727. }
  728. static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
  729. {
  730. return test_bit(sd_addr_to_wpnum(addr), sd->wp_groups);
  731. }
  732. static void sd_lock_command(SDState *sd)
  733. {
  734. int erase, lock, clr_pwd, set_pwd, pwd_len;
  735. erase = !!(sd->data[0] & 0x08);
  736. lock = sd->data[0] & 0x04;
  737. clr_pwd = sd->data[0] & 0x02;
  738. set_pwd = sd->data[0] & 0x01;
  739. if (sd->blk_len > 1)
  740. pwd_len = sd->data[1];
  741. else
  742. pwd_len = 0;
  743. if (lock) {
  744. trace_sdcard_lock();
  745. } else {
  746. trace_sdcard_unlock();
  747. }
  748. if (erase) {
  749. if (!(sd->card_status & CARD_IS_LOCKED) || sd->blk_len > 1 ||
  750. set_pwd || clr_pwd || lock || sd->wp_switch ||
  751. (sd->csd[14] & 0x20)) {
  752. sd->card_status |= LOCK_UNLOCK_FAILED;
  753. return;
  754. }
  755. bitmap_zero(sd->wp_groups, sd->wpgrps_size);
  756. sd->csd[14] &= ~0x10;
  757. sd->card_status &= ~CARD_IS_LOCKED;
  758. sd->pwd_len = 0;
  759. /* Erasing the entire card here! */
  760. fprintf(stderr, "SD: Card force-erased by CMD42\n");
  761. return;
  762. }
  763. if (sd->blk_len < 2 + pwd_len ||
  764. pwd_len <= sd->pwd_len ||
  765. pwd_len > sd->pwd_len + 16) {
  766. sd->card_status |= LOCK_UNLOCK_FAILED;
  767. return;
  768. }
  769. if (sd->pwd_len && memcmp(sd->pwd, sd->data + 2, sd->pwd_len)) {
  770. sd->card_status |= LOCK_UNLOCK_FAILED;
  771. return;
  772. }
  773. pwd_len -= sd->pwd_len;
  774. if ((pwd_len && !set_pwd) ||
  775. (clr_pwd && (set_pwd || lock)) ||
  776. (lock && !sd->pwd_len && !set_pwd) ||
  777. (!set_pwd && !clr_pwd &&
  778. (((sd->card_status & CARD_IS_LOCKED) && lock) ||
  779. (!(sd->card_status & CARD_IS_LOCKED) && !lock)))) {
  780. sd->card_status |= LOCK_UNLOCK_FAILED;
  781. return;
  782. }
  783. if (set_pwd) {
  784. memcpy(sd->pwd, sd->data + 2 + sd->pwd_len, pwd_len);
  785. sd->pwd_len = pwd_len;
  786. }
  787. if (clr_pwd) {
  788. sd->pwd_len = 0;
  789. }
  790. if (lock)
  791. sd->card_status |= CARD_IS_LOCKED;
  792. else
  793. sd->card_status &= ~CARD_IS_LOCKED;
  794. }
  795. static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
  796. {
  797. uint32_t rca = 0x0000;
  798. uint64_t addr = (sd->ocr & (1 << 30)) ? (uint64_t) req.arg << 9 : req.arg;
  799. /* CMD55 precedes an ACMD, so we are not interested in tracing it.
  800. * However there is no ACMD55, so we want to trace this particular case.
  801. */
  802. if (req.cmd != 55 || sd->expecting_acmd) {
  803. trace_sdcard_normal_command(sd->proto_name,
  804. sd_cmd_name(req.cmd), req.cmd,
  805. req.arg, sd_state_name(sd->state));
  806. }
  807. /* Not interpreting this as an app command */
  808. sd->card_status &= ~APP_CMD;
  809. if (sd_cmd_type[req.cmd] == sd_ac
  810. || sd_cmd_type[req.cmd] == sd_adtc) {
  811. rca = req.arg >> 16;
  812. }
  813. /* CMD23 (set block count) must be immediately followed by CMD18 or CMD25
  814. * if not, its effects are cancelled */
  815. if (sd->multi_blk_cnt != 0 && !(req.cmd == 18 || req.cmd == 25)) {
  816. sd->multi_blk_cnt = 0;
  817. }
  818. if (sd_cmd_class[req.cmd] == 6 && FIELD_EX32(sd->ocr, OCR, CARD_CAPACITY)) {
  819. /* Only Standard Capacity cards support class 6 commands */
  820. return sd_illegal;
  821. }
  822. switch (req.cmd) {
  823. /* Basic commands (Class 0 and Class 1) */
  824. case 0: /* CMD0: GO_IDLE_STATE */
  825. switch (sd->state) {
  826. case sd_inactive_state:
  827. return sd->spi ? sd_r1 : sd_r0;
  828. default:
  829. sd->state = sd_idle_state;
  830. sd_reset(DEVICE(sd));
  831. return sd->spi ? sd_r1 : sd_r0;
  832. }
  833. break;
  834. case 1: /* CMD1: SEND_OP_CMD */
  835. if (!sd->spi)
  836. goto bad_cmd;
  837. sd->state = sd_transfer_state;
  838. return sd_r1;
  839. case 2: /* CMD2: ALL_SEND_CID */
  840. if (sd->spi)
  841. goto bad_cmd;
  842. switch (sd->state) {
  843. case sd_ready_state:
  844. sd->state = sd_identification_state;
  845. return sd_r2_i;
  846. default:
  847. break;
  848. }
  849. break;
  850. case 3: /* CMD3: SEND_RELATIVE_ADDR */
  851. if (sd->spi)
  852. goto bad_cmd;
  853. switch (sd->state) {
  854. case sd_identification_state:
  855. case sd_standby_state:
  856. sd->state = sd_standby_state;
  857. sd_set_rca(sd);
  858. return sd_r6;
  859. default:
  860. break;
  861. }
  862. break;
  863. case 4: /* CMD4: SEND_DSR */
  864. if (sd->spi)
  865. goto bad_cmd;
  866. switch (sd->state) {
  867. case sd_standby_state:
  868. break;
  869. default:
  870. break;
  871. }
  872. break;
  873. case 5: /* CMD5: reserved for SDIO cards */
  874. return sd_illegal;
  875. case 6: /* CMD6: SWITCH_FUNCTION */
  876. switch (sd->mode) {
  877. case sd_data_transfer_mode:
  878. sd_function_switch(sd, req.arg);
  879. sd->state = sd_sendingdata_state;
  880. sd->data_start = 0;
  881. sd->data_offset = 0;
  882. return sd_r1;
  883. default:
  884. break;
  885. }
  886. break;
  887. case 7: /* CMD7: SELECT/DESELECT_CARD */
  888. if (sd->spi)
  889. goto bad_cmd;
  890. switch (sd->state) {
  891. case sd_standby_state:
  892. if (sd->rca != rca)
  893. return sd_r0;
  894. sd->state = sd_transfer_state;
  895. return sd_r1b;
  896. case sd_transfer_state:
  897. case sd_sendingdata_state:
  898. if (sd->rca == rca)
  899. break;
  900. sd->state = sd_standby_state;
  901. return sd_r1b;
  902. case sd_disconnect_state:
  903. if (sd->rca != rca)
  904. return sd_r0;
  905. sd->state = sd_programming_state;
  906. return sd_r1b;
  907. case sd_programming_state:
  908. if (sd->rca == rca)
  909. break;
  910. sd->state = sd_disconnect_state;
  911. return sd_r1b;
  912. default:
  913. break;
  914. }
  915. break;
  916. case 8: /* CMD8: SEND_IF_COND */
  917. if (sd->spec_version < SD_PHY_SPECv2_00_VERS) {
  918. break;
  919. }
  920. if (sd->state != sd_idle_state) {
  921. break;
  922. }
  923. sd->vhs = 0;
  924. /* No response if not exactly one VHS bit is set. */
  925. if (!(req.arg >> 8) || (req.arg >> (ctz32(req.arg & ~0xff) + 1))) {
  926. return sd->spi ? sd_r7 : sd_r0;
  927. }
  928. /* Accept. */
  929. sd->vhs = req.arg;
  930. return sd_r7;
  931. case 9: /* CMD9: SEND_CSD */
  932. switch (sd->state) {
  933. case sd_standby_state:
  934. if (sd->rca != rca)
  935. return sd_r0;
  936. return sd_r2_s;
  937. case sd_transfer_state:
  938. if (!sd->spi)
  939. break;
  940. sd->state = sd_sendingdata_state;
  941. memcpy(sd->data, sd->csd, 16);
  942. sd->data_start = addr;
  943. sd->data_offset = 0;
  944. return sd_r1;
  945. default:
  946. break;
  947. }
  948. break;
  949. case 10: /* CMD10: SEND_CID */
  950. switch (sd->state) {
  951. case sd_standby_state:
  952. if (sd->rca != rca)
  953. return sd_r0;
  954. return sd_r2_i;
  955. case sd_transfer_state:
  956. if (!sd->spi)
  957. break;
  958. sd->state = sd_sendingdata_state;
  959. memcpy(sd->data, sd->cid, 16);
  960. sd->data_start = addr;
  961. sd->data_offset = 0;
  962. return sd_r1;
  963. default:
  964. break;
  965. }
  966. break;
  967. case 12: /* CMD12: STOP_TRANSMISSION */
  968. switch (sd->state) {
  969. case sd_sendingdata_state:
  970. sd->state = sd_transfer_state;
  971. return sd_r1b;
  972. case sd_receivingdata_state:
  973. sd->state = sd_programming_state;
  974. /* Bzzzzzzztt .... Operation complete. */
  975. sd->state = sd_transfer_state;
  976. return sd_r1b;
  977. default:
  978. break;
  979. }
  980. break;
  981. case 13: /* CMD13: SEND_STATUS */
  982. switch (sd->mode) {
  983. case sd_data_transfer_mode:
  984. if (sd->rca != rca)
  985. return sd_r0;
  986. return sd_r1;
  987. default:
  988. break;
  989. }
  990. break;
  991. case 15: /* CMD15: GO_INACTIVE_STATE */
  992. if (sd->spi)
  993. goto bad_cmd;
  994. switch (sd->mode) {
  995. case sd_data_transfer_mode:
  996. if (sd->rca != rca)
  997. return sd_r0;
  998. sd->state = sd_inactive_state;
  999. return sd_r0;
  1000. default:
  1001. break;
  1002. }
  1003. break;
  1004. /* Block read commands (Classs 2) */
  1005. case 16: /* CMD16: SET_BLOCKLEN */
  1006. switch (sd->state) {
  1007. case sd_transfer_state:
  1008. if (req.arg > (1 << HWBLOCK_SHIFT)) {
  1009. sd->card_status |= BLOCK_LEN_ERROR;
  1010. } else {
  1011. trace_sdcard_set_blocklen(req.arg);
  1012. sd->blk_len = req.arg;
  1013. }
  1014. return sd_r1;
  1015. default:
  1016. break;
  1017. }
  1018. break;
  1019. case 17: /* CMD17: READ_SINGLE_BLOCK */
  1020. switch (sd->state) {
  1021. case sd_transfer_state:
  1022. if (addr + sd->blk_len > sd->size) {
  1023. sd->card_status |= ADDRESS_ERROR;
  1024. return sd_r1;
  1025. }
  1026. sd->state = sd_sendingdata_state;
  1027. sd->data_start = addr;
  1028. sd->data_offset = 0;
  1029. return sd_r1;
  1030. default:
  1031. break;
  1032. }
  1033. break;
  1034. case 18: /* CMD18: READ_MULTIPLE_BLOCK */
  1035. switch (sd->state) {
  1036. case sd_transfer_state:
  1037. if (addr + sd->blk_len > sd->size) {
  1038. sd->card_status |= ADDRESS_ERROR;
  1039. return sd_r1;
  1040. }
  1041. sd->state = sd_sendingdata_state;
  1042. sd->data_start = addr;
  1043. sd->data_offset = 0;
  1044. return sd_r1;
  1045. default:
  1046. break;
  1047. }
  1048. break;
  1049. case 19: /* CMD19: SEND_TUNING_BLOCK (SD) */
  1050. if (sd->spec_version < SD_PHY_SPECv3_01_VERS) {
  1051. break;
  1052. }
  1053. if (sd->state == sd_transfer_state) {
  1054. sd->state = sd_sendingdata_state;
  1055. sd->data_offset = 0;
  1056. return sd_r1;
  1057. }
  1058. break;
  1059. case 23: /* CMD23: SET_BLOCK_COUNT */
  1060. if (sd->spec_version < SD_PHY_SPECv3_01_VERS) {
  1061. break;
  1062. }
  1063. switch (sd->state) {
  1064. case sd_transfer_state:
  1065. sd->multi_blk_cnt = req.arg;
  1066. return sd_r1;
  1067. default:
  1068. break;
  1069. }
  1070. break;
  1071. /* Block write commands (Class 4) */
  1072. case 24: /* CMD24: WRITE_SINGLE_BLOCK */
  1073. switch (sd->state) {
  1074. case sd_transfer_state:
  1075. /* Writing in SPI mode not implemented. */
  1076. if (sd->spi)
  1077. break;
  1078. if (addr + sd->blk_len > sd->size) {
  1079. sd->card_status |= ADDRESS_ERROR;
  1080. return sd_r1;
  1081. }
  1082. sd->state = sd_receivingdata_state;
  1083. sd->data_start = addr;
  1084. sd->data_offset = 0;
  1085. sd->blk_written = 0;
  1086. if (sd_wp_addr(sd, sd->data_start)) {
  1087. sd->card_status |= WP_VIOLATION;
  1088. }
  1089. if (sd->csd[14] & 0x30) {
  1090. sd->card_status |= WP_VIOLATION;
  1091. }
  1092. return sd_r1;
  1093. default:
  1094. break;
  1095. }
  1096. break;
  1097. case 25: /* CMD25: WRITE_MULTIPLE_BLOCK */
  1098. switch (sd->state) {
  1099. case sd_transfer_state:
  1100. /* Writing in SPI mode not implemented. */
  1101. if (sd->spi)
  1102. break;
  1103. if (addr + sd->blk_len > sd->size) {
  1104. sd->card_status |= ADDRESS_ERROR;
  1105. return sd_r1;
  1106. }
  1107. sd->state = sd_receivingdata_state;
  1108. sd->data_start = addr;
  1109. sd->data_offset = 0;
  1110. sd->blk_written = 0;
  1111. if (sd_wp_addr(sd, sd->data_start)) {
  1112. sd->card_status |= WP_VIOLATION;
  1113. }
  1114. if (sd->csd[14] & 0x30) {
  1115. sd->card_status |= WP_VIOLATION;
  1116. }
  1117. return sd_r1;
  1118. default:
  1119. break;
  1120. }
  1121. break;
  1122. case 26: /* CMD26: PROGRAM_CID */
  1123. if (sd->spi)
  1124. goto bad_cmd;
  1125. switch (sd->state) {
  1126. case sd_transfer_state:
  1127. sd->state = sd_receivingdata_state;
  1128. sd->data_start = 0;
  1129. sd->data_offset = 0;
  1130. return sd_r1;
  1131. default:
  1132. break;
  1133. }
  1134. break;
  1135. case 27: /* CMD27: PROGRAM_CSD */
  1136. switch (sd->state) {
  1137. case sd_transfer_state:
  1138. sd->state = sd_receivingdata_state;
  1139. sd->data_start = 0;
  1140. sd->data_offset = 0;
  1141. return sd_r1;
  1142. default:
  1143. break;
  1144. }
  1145. break;
  1146. /* Write protection (Class 6) */
  1147. case 28: /* CMD28: SET_WRITE_PROT */
  1148. switch (sd->state) {
  1149. case sd_transfer_state:
  1150. if (addr >= sd->size) {
  1151. sd->card_status |= ADDRESS_ERROR;
  1152. return sd_r1b;
  1153. }
  1154. sd->state = sd_programming_state;
  1155. set_bit(sd_addr_to_wpnum(addr), sd->wp_groups);
  1156. /* Bzzzzzzztt .... Operation complete. */
  1157. sd->state = sd_transfer_state;
  1158. return sd_r1b;
  1159. default:
  1160. break;
  1161. }
  1162. break;
  1163. case 29: /* CMD29: CLR_WRITE_PROT */
  1164. switch (sd->state) {
  1165. case sd_transfer_state:
  1166. if (addr >= sd->size) {
  1167. sd->card_status |= ADDRESS_ERROR;
  1168. return sd_r1b;
  1169. }
  1170. sd->state = sd_programming_state;
  1171. clear_bit(sd_addr_to_wpnum(addr), sd->wp_groups);
  1172. /* Bzzzzzzztt .... Operation complete. */
  1173. sd->state = sd_transfer_state;
  1174. return sd_r1b;
  1175. default:
  1176. break;
  1177. }
  1178. break;
  1179. case 30: /* CMD30: SEND_WRITE_PROT */
  1180. switch (sd->state) {
  1181. case sd_transfer_state:
  1182. sd->state = sd_sendingdata_state;
  1183. *(uint32_t *) sd->data = sd_wpbits(sd, req.arg);
  1184. sd->data_start = addr;
  1185. sd->data_offset = 0;
  1186. return sd_r1b;
  1187. default:
  1188. break;
  1189. }
  1190. break;
  1191. /* Erase commands (Class 5) */
  1192. case 32: /* CMD32: ERASE_WR_BLK_START */
  1193. switch (sd->state) {
  1194. case sd_transfer_state:
  1195. sd->erase_start = req.arg;
  1196. return sd_r1;
  1197. default:
  1198. break;
  1199. }
  1200. break;
  1201. case 33: /* CMD33: ERASE_WR_BLK_END */
  1202. switch (sd->state) {
  1203. case sd_transfer_state:
  1204. sd->erase_end = req.arg;
  1205. return sd_r1;
  1206. default:
  1207. break;
  1208. }
  1209. break;
  1210. case 38: /* CMD38: ERASE */
  1211. switch (sd->state) {
  1212. case sd_transfer_state:
  1213. if (sd->csd[14] & 0x30) {
  1214. sd->card_status |= WP_VIOLATION;
  1215. return sd_r1b;
  1216. }
  1217. sd->state = sd_programming_state;
  1218. sd_erase(sd);
  1219. /* Bzzzzzzztt .... Operation complete. */
  1220. sd->state = sd_transfer_state;
  1221. return sd_r1b;
  1222. default:
  1223. break;
  1224. }
  1225. break;
  1226. /* Lock card commands (Class 7) */
  1227. case 42: /* CMD42: LOCK_UNLOCK */
  1228. switch (sd->state) {
  1229. case sd_transfer_state:
  1230. sd->state = sd_receivingdata_state;
  1231. sd->data_start = 0;
  1232. sd->data_offset = 0;
  1233. return sd_r1;
  1234. default:
  1235. break;
  1236. }
  1237. break;
  1238. case 52 ... 54:
  1239. /* CMD52, CMD53, CMD54: reserved for SDIO cards
  1240. * (see the SDIO Simplified Specification V2.0)
  1241. * Handle as illegal command but do not complain
  1242. * on stderr, as some OSes may use these in their
  1243. * probing for presence of an SDIO card.
  1244. */
  1245. return sd_illegal;
  1246. /* Application specific commands (Class 8) */
  1247. case 55: /* CMD55: APP_CMD */
  1248. switch (sd->state) {
  1249. case sd_ready_state:
  1250. case sd_identification_state:
  1251. case sd_inactive_state:
  1252. return sd_illegal;
  1253. case sd_idle_state:
  1254. if (rca) {
  1255. qemu_log_mask(LOG_GUEST_ERROR,
  1256. "SD: illegal RCA 0x%04x for APP_CMD\n", req.cmd);
  1257. }
  1258. default:
  1259. break;
  1260. }
  1261. if (!sd->spi) {
  1262. if (sd->rca != rca) {
  1263. return sd_r0;
  1264. }
  1265. }
  1266. sd->expecting_acmd = true;
  1267. sd->card_status |= APP_CMD;
  1268. return sd_r1;
  1269. case 56: /* CMD56: GEN_CMD */
  1270. switch (sd->state) {
  1271. case sd_transfer_state:
  1272. sd->data_offset = 0;
  1273. if (req.arg & 1)
  1274. sd->state = sd_sendingdata_state;
  1275. else
  1276. sd->state = sd_receivingdata_state;
  1277. return sd_r1;
  1278. default:
  1279. break;
  1280. }
  1281. break;
  1282. case 58: /* CMD58: READ_OCR (SPI) */
  1283. if (!sd->spi) {
  1284. goto bad_cmd;
  1285. }
  1286. return sd_r3;
  1287. case 59: /* CMD59: CRC_ON_OFF (SPI) */
  1288. if (!sd->spi) {
  1289. goto bad_cmd;
  1290. }
  1291. goto unimplemented_spi_cmd;
  1292. default:
  1293. bad_cmd:
  1294. qemu_log_mask(LOG_GUEST_ERROR, "SD: Unknown CMD%i\n", req.cmd);
  1295. return sd_illegal;
  1296. unimplemented_spi_cmd:
  1297. /* Commands that are recognised but not yet implemented in SPI mode. */
  1298. qemu_log_mask(LOG_UNIMP, "SD: CMD%i not implemented in SPI mode\n",
  1299. req.cmd);
  1300. return sd_illegal;
  1301. }
  1302. qemu_log_mask(LOG_GUEST_ERROR, "SD: CMD%i in a wrong state\n", req.cmd);
  1303. return sd_illegal;
  1304. }
  1305. static sd_rsp_type_t sd_app_command(SDState *sd,
  1306. SDRequest req)
  1307. {
  1308. trace_sdcard_app_command(sd->proto_name, sd_acmd_name(req.cmd),
  1309. req.cmd, req.arg, sd_state_name(sd->state));
  1310. sd->card_status |= APP_CMD;
  1311. switch (req.cmd) {
  1312. case 6: /* ACMD6: SET_BUS_WIDTH */
  1313. if (sd->spi) {
  1314. goto unimplemented_spi_cmd;
  1315. }
  1316. switch (sd->state) {
  1317. case sd_transfer_state:
  1318. sd->sd_status[0] &= 0x3f;
  1319. sd->sd_status[0] |= (req.arg & 0x03) << 6;
  1320. return sd_r1;
  1321. default:
  1322. break;
  1323. }
  1324. break;
  1325. case 13: /* ACMD13: SD_STATUS */
  1326. switch (sd->state) {
  1327. case sd_transfer_state:
  1328. sd->state = sd_sendingdata_state;
  1329. sd->data_start = 0;
  1330. sd->data_offset = 0;
  1331. return sd_r1;
  1332. default:
  1333. break;
  1334. }
  1335. break;
  1336. case 22: /* ACMD22: SEND_NUM_WR_BLOCKS */
  1337. switch (sd->state) {
  1338. case sd_transfer_state:
  1339. *(uint32_t *) sd->data = sd->blk_written;
  1340. sd->state = sd_sendingdata_state;
  1341. sd->data_start = 0;
  1342. sd->data_offset = 0;
  1343. return sd_r1;
  1344. default:
  1345. break;
  1346. }
  1347. break;
  1348. case 23: /* ACMD23: SET_WR_BLK_ERASE_COUNT */
  1349. switch (sd->state) {
  1350. case sd_transfer_state:
  1351. return sd_r1;
  1352. default:
  1353. break;
  1354. }
  1355. break;
  1356. case 41: /* ACMD41: SD_APP_OP_COND */
  1357. if (sd->spi) {
  1358. /* SEND_OP_CMD */
  1359. sd->state = sd_transfer_state;
  1360. return sd_r1;
  1361. }
  1362. if (sd->state != sd_idle_state) {
  1363. break;
  1364. }
  1365. /* If it's the first ACMD41 since reset, we need to decide
  1366. * whether to power up. If this is not an enquiry ACMD41,
  1367. * we immediately report power on and proceed below to the
  1368. * ready state, but if it is, we set a timer to model a
  1369. * delay for power up. This works around a bug in EDK2
  1370. * UEFI, which sends an initial enquiry ACMD41, but
  1371. * assumes that the card is in ready state as soon as it
  1372. * sees the power up bit set. */
  1373. if (!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP)) {
  1374. if ((req.arg & ACMD41_ENQUIRY_MASK) != 0) {
  1375. timer_del(sd->ocr_power_timer);
  1376. sd_ocr_powerup(sd);
  1377. } else {
  1378. trace_sdcard_inquiry_cmd41();
  1379. if (!timer_pending(sd->ocr_power_timer)) {
  1380. timer_mod_ns(sd->ocr_power_timer,
  1381. (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
  1382. + OCR_POWER_DELAY_NS));
  1383. }
  1384. }
  1385. }
  1386. if (FIELD_EX32(sd->ocr & req.arg, OCR, VDD_VOLTAGE_WINDOW)) {
  1387. /* We accept any voltage. 10000 V is nothing.
  1388. *
  1389. * Once we're powered up, we advance straight to ready state
  1390. * unless it's an enquiry ACMD41 (bits 23:0 == 0).
  1391. */
  1392. sd->state = sd_ready_state;
  1393. }
  1394. return sd_r3;
  1395. case 42: /* ACMD42: SET_CLR_CARD_DETECT */
  1396. switch (sd->state) {
  1397. case sd_transfer_state:
  1398. /* Bringing in the 50KOhm pull-up resistor... Done. */
  1399. return sd_r1;
  1400. default:
  1401. break;
  1402. }
  1403. break;
  1404. case 51: /* ACMD51: SEND_SCR */
  1405. switch (sd->state) {
  1406. case sd_transfer_state:
  1407. sd->state = sd_sendingdata_state;
  1408. sd->data_start = 0;
  1409. sd->data_offset = 0;
  1410. return sd_r1;
  1411. default:
  1412. break;
  1413. }
  1414. break;
  1415. case 18: /* Reserved for SD security applications */
  1416. case 25:
  1417. case 26:
  1418. case 38:
  1419. case 43 ... 49:
  1420. /* Refer to the "SD Specifications Part3 Security Specification" for
  1421. * information about the SD Security Features.
  1422. */
  1423. qemu_log_mask(LOG_UNIMP, "SD: CMD%i Security not implemented\n",
  1424. req.cmd);
  1425. return sd_illegal;
  1426. default:
  1427. /* Fall back to standard commands. */
  1428. return sd_normal_command(sd, req);
  1429. unimplemented_spi_cmd:
  1430. /* Commands that are recognised but not yet implemented in SPI mode. */
  1431. qemu_log_mask(LOG_UNIMP, "SD: CMD%i not implemented in SPI mode\n",
  1432. req.cmd);
  1433. return sd_illegal;
  1434. }
  1435. qemu_log_mask(LOG_GUEST_ERROR, "SD: ACMD%i in a wrong state\n", req.cmd);
  1436. return sd_illegal;
  1437. }
  1438. static int cmd_valid_while_locked(SDState *sd, SDRequest *req)
  1439. {
  1440. /* Valid commands in locked state:
  1441. * basic class (0)
  1442. * lock card class (7)
  1443. * CMD16
  1444. * implicitly, the ACMD prefix CMD55
  1445. * ACMD41 and ACMD42
  1446. * Anything else provokes an "illegal command" response.
  1447. */
  1448. if (sd->expecting_acmd) {
  1449. return req->cmd == 41 || req->cmd == 42;
  1450. }
  1451. if (req->cmd == 16 || req->cmd == 55) {
  1452. return 1;
  1453. }
  1454. return sd_cmd_class[req->cmd] == 0
  1455. || sd_cmd_class[req->cmd] == 7;
  1456. }
  1457. int sd_do_command(SDState *sd, SDRequest *req,
  1458. uint8_t *response) {
  1459. int last_state;
  1460. sd_rsp_type_t rtype;
  1461. int rsplen;
  1462. if (!sd->blk || !blk_is_inserted(sd->blk) || !sd->enable) {
  1463. return 0;
  1464. }
  1465. if (sd_req_crc_validate(req)) {
  1466. sd->card_status |= COM_CRC_ERROR;
  1467. rtype = sd_illegal;
  1468. goto send_response;
  1469. }
  1470. if (req->cmd >= SDMMC_CMD_MAX) {
  1471. qemu_log_mask(LOG_GUEST_ERROR, "SD: incorrect command 0x%02x\n",
  1472. req->cmd);
  1473. req->cmd &= 0x3f;
  1474. }
  1475. if (sd->card_status & CARD_IS_LOCKED) {
  1476. if (!cmd_valid_while_locked(sd, req)) {
  1477. sd->card_status |= ILLEGAL_COMMAND;
  1478. sd->expecting_acmd = false;
  1479. qemu_log_mask(LOG_GUEST_ERROR, "SD: Card is locked\n");
  1480. rtype = sd_illegal;
  1481. goto send_response;
  1482. }
  1483. }
  1484. last_state = sd->state;
  1485. sd_set_mode(sd);
  1486. if (sd->expecting_acmd) {
  1487. sd->expecting_acmd = false;
  1488. rtype = sd_app_command(sd, *req);
  1489. } else {
  1490. rtype = sd_normal_command(sd, *req);
  1491. }
  1492. if (rtype == sd_illegal) {
  1493. sd->card_status |= ILLEGAL_COMMAND;
  1494. } else {
  1495. /* Valid command, we can update the 'state before command' bits.
  1496. * (Do this now so they appear in r1 responses.)
  1497. */
  1498. sd->current_cmd = req->cmd;
  1499. sd->card_status &= ~CURRENT_STATE;
  1500. sd->card_status |= (last_state << 9);
  1501. }
  1502. send_response:
  1503. switch (rtype) {
  1504. case sd_r1:
  1505. case sd_r1b:
  1506. sd_response_r1_make(sd, response);
  1507. rsplen = 4;
  1508. break;
  1509. case sd_r2_i:
  1510. memcpy(response, sd->cid, sizeof(sd->cid));
  1511. rsplen = 16;
  1512. break;
  1513. case sd_r2_s:
  1514. memcpy(response, sd->csd, sizeof(sd->csd));
  1515. rsplen = 16;
  1516. break;
  1517. case sd_r3:
  1518. sd_response_r3_make(sd, response);
  1519. rsplen = 4;
  1520. break;
  1521. case sd_r6:
  1522. sd_response_r6_make(sd, response);
  1523. rsplen = 4;
  1524. break;
  1525. case sd_r7:
  1526. sd_response_r7_make(sd, response);
  1527. rsplen = 4;
  1528. break;
  1529. case sd_r0:
  1530. case sd_illegal:
  1531. rsplen = 0;
  1532. break;
  1533. default:
  1534. g_assert_not_reached();
  1535. }
  1536. trace_sdcard_response(sd_response_name(rtype), rsplen);
  1537. if (rtype != sd_illegal) {
  1538. /* Clear the "clear on valid command" status bits now we've
  1539. * sent any response
  1540. */
  1541. sd->card_status &= ~CARD_STATUS_B;
  1542. }
  1543. #ifdef DEBUG_SD
  1544. qemu_hexdump((const char *)response, stderr, "Response", rsplen);
  1545. #endif
  1546. return rsplen;
  1547. }
  1548. static void sd_blk_read(SDState *sd, uint64_t addr, uint32_t len)
  1549. {
  1550. trace_sdcard_read_block(addr, len);
  1551. if (!sd->blk || blk_pread(sd->blk, addr, sd->data, len) < 0) {
  1552. fprintf(stderr, "sd_blk_read: read error on host side\n");
  1553. }
  1554. }
  1555. static void sd_blk_write(SDState *sd, uint64_t addr, uint32_t len)
  1556. {
  1557. trace_sdcard_write_block(addr, len);
  1558. if (!sd->blk || blk_pwrite(sd->blk, addr, sd->data, len, 0) < 0) {
  1559. fprintf(stderr, "sd_blk_write: write error on host side\n");
  1560. }
  1561. }
  1562. #define BLK_READ_BLOCK(a, len) sd_blk_read(sd, a, len)
  1563. #define BLK_WRITE_BLOCK(a, len) sd_blk_write(sd, a, len)
  1564. #define APP_READ_BLOCK(a, len) memset(sd->data, 0xec, len)
  1565. #define APP_WRITE_BLOCK(a, len)
  1566. void sd_write_data(SDState *sd, uint8_t value)
  1567. {
  1568. int i;
  1569. if (!sd->blk || !blk_is_inserted(sd->blk) || !sd->enable)
  1570. return;
  1571. if (sd->state != sd_receivingdata_state) {
  1572. qemu_log_mask(LOG_GUEST_ERROR,
  1573. "sd_write_data: not in Receiving-Data state\n");
  1574. return;
  1575. }
  1576. if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION))
  1577. return;
  1578. trace_sdcard_write_data(sd->proto_name,
  1579. sd_acmd_name(sd->current_cmd),
  1580. sd->current_cmd, value);
  1581. switch (sd->current_cmd) {
  1582. case 24: /* CMD24: WRITE_SINGLE_BLOCK */
  1583. sd->data[sd->data_offset ++] = value;
  1584. if (sd->data_offset >= sd->blk_len) {
  1585. /* TODO: Check CRC before committing */
  1586. sd->state = sd_programming_state;
  1587. BLK_WRITE_BLOCK(sd->data_start, sd->data_offset);
  1588. sd->blk_written ++;
  1589. sd->csd[14] |= 0x40;
  1590. /* Bzzzzzzztt .... Operation complete. */
  1591. sd->state = sd_transfer_state;
  1592. }
  1593. break;
  1594. case 25: /* CMD25: WRITE_MULTIPLE_BLOCK */
  1595. if (sd->data_offset == 0) {
  1596. /* Start of the block - let's check the address is valid */
  1597. if (sd->data_start + sd->blk_len > sd->size) {
  1598. sd->card_status |= ADDRESS_ERROR;
  1599. break;
  1600. }
  1601. if (sd_wp_addr(sd, sd->data_start)) {
  1602. sd->card_status |= WP_VIOLATION;
  1603. break;
  1604. }
  1605. }
  1606. sd->data[sd->data_offset++] = value;
  1607. if (sd->data_offset >= sd->blk_len) {
  1608. /* TODO: Check CRC before committing */
  1609. sd->state = sd_programming_state;
  1610. BLK_WRITE_BLOCK(sd->data_start, sd->data_offset);
  1611. sd->blk_written++;
  1612. sd->data_start += sd->blk_len;
  1613. sd->data_offset = 0;
  1614. sd->csd[14] |= 0x40;
  1615. /* Bzzzzzzztt .... Operation complete. */
  1616. if (sd->multi_blk_cnt != 0) {
  1617. if (--sd->multi_blk_cnt == 0) {
  1618. /* Stop! */
  1619. sd->state = sd_transfer_state;
  1620. break;
  1621. }
  1622. }
  1623. sd->state = sd_receivingdata_state;
  1624. }
  1625. break;
  1626. case 26: /* CMD26: PROGRAM_CID */
  1627. sd->data[sd->data_offset ++] = value;
  1628. if (sd->data_offset >= sizeof(sd->cid)) {
  1629. /* TODO: Check CRC before committing */
  1630. sd->state = sd_programming_state;
  1631. for (i = 0; i < sizeof(sd->cid); i ++)
  1632. if ((sd->cid[i] | 0x00) != sd->data[i])
  1633. sd->card_status |= CID_CSD_OVERWRITE;
  1634. if (!(sd->card_status & CID_CSD_OVERWRITE))
  1635. for (i = 0; i < sizeof(sd->cid); i ++) {
  1636. sd->cid[i] |= 0x00;
  1637. sd->cid[i] &= sd->data[i];
  1638. }
  1639. /* Bzzzzzzztt .... Operation complete. */
  1640. sd->state = sd_transfer_state;
  1641. }
  1642. break;
  1643. case 27: /* CMD27: PROGRAM_CSD */
  1644. sd->data[sd->data_offset ++] = value;
  1645. if (sd->data_offset >= sizeof(sd->csd)) {
  1646. /* TODO: Check CRC before committing */
  1647. sd->state = sd_programming_state;
  1648. for (i = 0; i < sizeof(sd->csd); i ++)
  1649. if ((sd->csd[i] | sd_csd_rw_mask[i]) !=
  1650. (sd->data[i] | sd_csd_rw_mask[i]))
  1651. sd->card_status |= CID_CSD_OVERWRITE;
  1652. /* Copy flag (OTP) & Permanent write protect */
  1653. if (sd->csd[14] & ~sd->data[14] & 0x60)
  1654. sd->card_status |= CID_CSD_OVERWRITE;
  1655. if (!(sd->card_status & CID_CSD_OVERWRITE))
  1656. for (i = 0; i < sizeof(sd->csd); i ++) {
  1657. sd->csd[i] |= sd_csd_rw_mask[i];
  1658. sd->csd[i] &= sd->data[i];
  1659. }
  1660. /* Bzzzzzzztt .... Operation complete. */
  1661. sd->state = sd_transfer_state;
  1662. }
  1663. break;
  1664. case 42: /* CMD42: LOCK_UNLOCK */
  1665. sd->data[sd->data_offset ++] = value;
  1666. if (sd->data_offset >= sd->blk_len) {
  1667. /* TODO: Check CRC before committing */
  1668. sd->state = sd_programming_state;
  1669. sd_lock_command(sd);
  1670. /* Bzzzzzzztt .... Operation complete. */
  1671. sd->state = sd_transfer_state;
  1672. }
  1673. break;
  1674. case 56: /* CMD56: GEN_CMD */
  1675. sd->data[sd->data_offset ++] = value;
  1676. if (sd->data_offset >= sd->blk_len) {
  1677. APP_WRITE_BLOCK(sd->data_start, sd->data_offset);
  1678. sd->state = sd_transfer_state;
  1679. }
  1680. break;
  1681. default:
  1682. qemu_log_mask(LOG_GUEST_ERROR, "sd_write_data: unknown command\n");
  1683. break;
  1684. }
  1685. }
  1686. #define SD_TUNING_BLOCK_SIZE 64
  1687. static const uint8_t sd_tuning_block_pattern[SD_TUNING_BLOCK_SIZE] = {
  1688. /* See: Physical Layer Simplified Specification Version 3.01, Table 4-2 */
  1689. 0xff, 0x0f, 0xff, 0x00, 0x0f, 0xfc, 0xc3, 0xcc,
  1690. 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
  1691. 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
  1692. 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
  1693. 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
  1694. 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
  1695. 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
  1696. 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
  1697. };
  1698. uint8_t sd_read_data(SDState *sd)
  1699. {
  1700. /* TODO: Append CRCs */
  1701. uint8_t ret;
  1702. int io_len;
  1703. if (!sd->blk || !blk_is_inserted(sd->blk) || !sd->enable)
  1704. return 0x00;
  1705. if (sd->state != sd_sendingdata_state) {
  1706. qemu_log_mask(LOG_GUEST_ERROR,
  1707. "sd_read_data: not in Sending-Data state\n");
  1708. return 0x00;
  1709. }
  1710. if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION))
  1711. return 0x00;
  1712. io_len = (sd->ocr & (1 << 30)) ? 512 : sd->blk_len;
  1713. trace_sdcard_read_data(sd->proto_name,
  1714. sd_acmd_name(sd->current_cmd),
  1715. sd->current_cmd, io_len);
  1716. switch (sd->current_cmd) {
  1717. case 6: /* CMD6: SWITCH_FUNCTION */
  1718. ret = sd->data[sd->data_offset ++];
  1719. if (sd->data_offset >= 64)
  1720. sd->state = sd_transfer_state;
  1721. break;
  1722. case 9: /* CMD9: SEND_CSD */
  1723. case 10: /* CMD10: SEND_CID */
  1724. ret = sd->data[sd->data_offset ++];
  1725. if (sd->data_offset >= 16)
  1726. sd->state = sd_transfer_state;
  1727. break;
  1728. case 13: /* ACMD13: SD_STATUS */
  1729. ret = sd->sd_status[sd->data_offset ++];
  1730. if (sd->data_offset >= sizeof(sd->sd_status))
  1731. sd->state = sd_transfer_state;
  1732. break;
  1733. case 17: /* CMD17: READ_SINGLE_BLOCK */
  1734. if (sd->data_offset == 0)
  1735. BLK_READ_BLOCK(sd->data_start, io_len);
  1736. ret = sd->data[sd->data_offset ++];
  1737. if (sd->data_offset >= io_len)
  1738. sd->state = sd_transfer_state;
  1739. break;
  1740. case 18: /* CMD18: READ_MULTIPLE_BLOCK */
  1741. if (sd->data_offset == 0) {
  1742. if (sd->data_start + io_len > sd->size) {
  1743. sd->card_status |= ADDRESS_ERROR;
  1744. return 0x00;
  1745. }
  1746. BLK_READ_BLOCK(sd->data_start, io_len);
  1747. }
  1748. ret = sd->data[sd->data_offset ++];
  1749. if (sd->data_offset >= io_len) {
  1750. sd->data_start += io_len;
  1751. sd->data_offset = 0;
  1752. if (sd->multi_blk_cnt != 0) {
  1753. if (--sd->multi_blk_cnt == 0) {
  1754. /* Stop! */
  1755. sd->state = sd_transfer_state;
  1756. break;
  1757. }
  1758. }
  1759. }
  1760. break;
  1761. case 19: /* CMD19: SEND_TUNING_BLOCK (SD) */
  1762. if (sd->data_offset >= SD_TUNING_BLOCK_SIZE - 1) {
  1763. sd->state = sd_transfer_state;
  1764. }
  1765. ret = sd_tuning_block_pattern[sd->data_offset++];
  1766. break;
  1767. case 22: /* ACMD22: SEND_NUM_WR_BLOCKS */
  1768. ret = sd->data[sd->data_offset ++];
  1769. if (sd->data_offset >= 4)
  1770. sd->state = sd_transfer_state;
  1771. break;
  1772. case 30: /* CMD30: SEND_WRITE_PROT */
  1773. ret = sd->data[sd->data_offset ++];
  1774. if (sd->data_offset >= 4)
  1775. sd->state = sd_transfer_state;
  1776. break;
  1777. case 51: /* ACMD51: SEND_SCR */
  1778. ret = sd->scr[sd->data_offset ++];
  1779. if (sd->data_offset >= sizeof(sd->scr))
  1780. sd->state = sd_transfer_state;
  1781. break;
  1782. case 56: /* CMD56: GEN_CMD */
  1783. if (sd->data_offset == 0)
  1784. APP_READ_BLOCK(sd->data_start, sd->blk_len);
  1785. ret = sd->data[sd->data_offset ++];
  1786. if (sd->data_offset >= sd->blk_len)
  1787. sd->state = sd_transfer_state;
  1788. break;
  1789. default:
  1790. qemu_log_mask(LOG_GUEST_ERROR, "sd_read_data: unknown command\n");
  1791. return 0x00;
  1792. }
  1793. return ret;
  1794. }
  1795. bool sd_data_ready(SDState *sd)
  1796. {
  1797. return sd->state == sd_sendingdata_state;
  1798. }
  1799. void sd_enable(SDState *sd, bool enable)
  1800. {
  1801. sd->enable = enable;
  1802. }
  1803. static void sd_instance_init(Object *obj)
  1804. {
  1805. SDState *sd = SD_CARD(obj);
  1806. sd->enable = true;
  1807. sd->ocr_power_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sd_ocr_powerup, sd);
  1808. }
  1809. static void sd_instance_finalize(Object *obj)
  1810. {
  1811. SDState *sd = SD_CARD(obj);
  1812. timer_del(sd->ocr_power_timer);
  1813. timer_free(sd->ocr_power_timer);
  1814. }
  1815. static void sd_realize(DeviceState *dev, Error **errp)
  1816. {
  1817. SDState *sd = SD_CARD(dev);
  1818. int ret;
  1819. sd->proto_name = sd->spi ? "SPI" : "SD";
  1820. switch (sd->spec_version) {
  1821. case SD_PHY_SPECv1_10_VERS
  1822. ... SD_PHY_SPECv3_01_VERS:
  1823. break;
  1824. default:
  1825. error_setg(errp, "Invalid SD card Spec version: %u", sd->spec_version);
  1826. return;
  1827. }
  1828. if (sd->blk) {
  1829. int64_t blk_size;
  1830. if (blk_is_read_only(sd->blk)) {
  1831. error_setg(errp, "Cannot use read-only drive as SD card");
  1832. return;
  1833. }
  1834. blk_size = blk_getlength(sd->blk);
  1835. if (blk_size > 0 && !is_power_of_2(blk_size)) {
  1836. int64_t blk_size_aligned = pow2ceil(blk_size);
  1837. char *blk_size_str;
  1838. blk_size_str = size_to_str(blk_size);
  1839. error_setg(errp, "Invalid SD card size: %s", blk_size_str);
  1840. g_free(blk_size_str);
  1841. blk_size_str = size_to_str(blk_size_aligned);
  1842. error_append_hint(errp,
  1843. "SD card size has to be a power of 2, e.g. %s.\n"
  1844. "You can resize disk images with"
  1845. " 'qemu-img resize <imagefile> <new-size>'\n"
  1846. "(note that this will lose data if you make the"
  1847. " image smaller than it currently is).\n",
  1848. blk_size_str);
  1849. g_free(blk_size_str);
  1850. return;
  1851. }
  1852. ret = blk_set_perm(sd->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
  1853. BLK_PERM_ALL, errp);
  1854. if (ret < 0) {
  1855. return;
  1856. }
  1857. blk_set_dev_ops(sd->blk, &sd_block_ops, sd);
  1858. }
  1859. }
  1860. static Property sd_properties[] = {
  1861. DEFINE_PROP_UINT8("spec_version", SDState,
  1862. spec_version, SD_PHY_SPECv2_00_VERS),
  1863. DEFINE_PROP_DRIVE("drive", SDState, blk),
  1864. /* We do not model the chip select pin, so allow the board to select
  1865. * whether card should be in SSI or MMC/SD mode. It is also up to the
  1866. * board to ensure that ssi transfers only occur when the chip select
  1867. * is asserted. */
  1868. DEFINE_PROP_BOOL("spi", SDState, spi, false),
  1869. DEFINE_PROP_END_OF_LIST()
  1870. };
  1871. static void sd_class_init(ObjectClass *klass, void *data)
  1872. {
  1873. DeviceClass *dc = DEVICE_CLASS(klass);
  1874. SDCardClass *sc = SD_CARD_CLASS(klass);
  1875. dc->realize = sd_realize;
  1876. device_class_set_props(dc, sd_properties);
  1877. dc->vmsd = &sd_vmstate;
  1878. dc->reset = sd_reset;
  1879. dc->bus_type = TYPE_SD_BUS;
  1880. set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
  1881. sc->set_voltage = sd_set_voltage;
  1882. sc->get_dat_lines = sd_get_dat_lines;
  1883. sc->get_cmd_line = sd_get_cmd_line;
  1884. sc->do_command = sd_do_command;
  1885. sc->write_data = sd_write_data;
  1886. sc->read_data = sd_read_data;
  1887. sc->data_ready = sd_data_ready;
  1888. sc->enable = sd_enable;
  1889. sc->get_inserted = sd_get_inserted;
  1890. sc->get_readonly = sd_get_readonly;
  1891. }
  1892. static const TypeInfo sd_info = {
  1893. .name = TYPE_SD_CARD,
  1894. .parent = TYPE_DEVICE,
  1895. .instance_size = sizeof(SDState),
  1896. .class_size = sizeof(SDCardClass),
  1897. .class_init = sd_class_init,
  1898. .instance_init = sd_instance_init,
  1899. .instance_finalize = sd_instance_finalize,
  1900. };
  1901. static void sd_register_types(void)
  1902. {
  1903. type_register_static(&sd_info);
  1904. }
  1905. type_init(sd_register_types)