auxbus.c 8.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305
  1. /*
  2. * auxbus.c
  3. *
  4. * Copyright 2015 : GreenSocs Ltd
  5. * http://www.greensocs.com/ , email: info@greensocs.com
  6. *
  7. * Developed by :
  8. * Frederic Konrad <fred.konrad@greensocs.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation, either version 2 of the License, or
  13. * (at your option)any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, see <http://www.gnu.org/licenses/>.
  22. *
  23. */
  24. /*
  25. * This is an implementation of the AUX bus for VESA Display Port v1.1a.
  26. */
  27. #include "qemu/osdep.h"
  28. #include "qemu/units.h"
  29. #include "qemu/log.h"
  30. #include "qemu/module.h"
  31. #include "hw/misc/auxbus.h"
  32. #include "hw/i2c/i2c.h"
  33. #include "monitor/monitor.h"
  34. #include "qapi/error.h"
  35. #ifndef DEBUG_AUX
  36. #define DEBUG_AUX 0
  37. #endif
  38. #define DPRINTF(fmt, ...) do { \
  39. if (DEBUG_AUX) { \
  40. qemu_log("aux: " fmt , ## __VA_ARGS__); \
  41. } \
  42. } while (0)
  43. #define TYPE_AUXTOI2C "aux-to-i2c-bridge"
  44. #define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
  45. static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
  46. static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);
  47. /* aux-bus implementation (internal not public) */
  48. static void aux_bus_class_init(ObjectClass *klass, void *data)
  49. {
  50. BusClass *k = BUS_CLASS(klass);
  51. /* AUXSlave has an MMIO so we need to change the way we print information
  52. * in monitor.
  53. */
  54. k->print_dev = aux_slave_dev_print;
  55. }
  56. AUXBus *aux_bus_init(DeviceState *parent, const char *name)
  57. {
  58. AUXBus *bus;
  59. Object *auxtoi2c;
  60. bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
  61. auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
  62. &error_abort, NULL);
  63. bus->bridge = AUXTOI2C(auxtoi2c);
  64. /* Memory related. */
  65. bus->aux_io = g_malloc(sizeof(*bus->aux_io));
  66. memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB);
  67. address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
  68. return bus;
  69. }
  70. void aux_bus_realize(AUXBus *bus)
  71. {
  72. qdev_realize(DEVICE(bus->bridge), BUS(bus), &error_fatal);
  73. }
  74. void aux_map_slave(AUXSlave *aux_dev, hwaddr addr)
  75. {
  76. DeviceState *dev = DEVICE(aux_dev);
  77. AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
  78. memory_region_add_subregion(bus->aux_io, addr, aux_dev->mmio);
  79. }
  80. static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
  81. {
  82. return (dev == DEVICE(bus->bridge));
  83. }
  84. I2CBus *aux_get_i2c_bus(AUXBus *bus)
  85. {
  86. return aux_bridge_get_i2c_bus(bus->bridge);
  87. }
  88. AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
  89. uint8_t len, uint8_t *data)
  90. {
  91. AUXReply ret = AUX_NACK;
  92. I2CBus *i2c_bus = aux_get_i2c_bus(bus);
  93. size_t i;
  94. bool is_write = false;
  95. DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address,
  96. cmd, len);
  97. switch (cmd) {
  98. /*
  99. * Forward the request on the AUX bus..
  100. */
  101. case WRITE_AUX:
  102. case READ_AUX:
  103. is_write = cmd == READ_AUX ? false : true;
  104. for (i = 0; i < len; i++) {
  105. if (!address_space_rw(&bus->aux_addr_space, address++,
  106. MEMTXATTRS_UNSPECIFIED, data++, 1,
  107. is_write)) {
  108. ret = AUX_I2C_ACK;
  109. } else {
  110. ret = AUX_NACK;
  111. break;
  112. }
  113. }
  114. break;
  115. /*
  116. * Classic I2C transactions..
  117. */
  118. case READ_I2C:
  119. case WRITE_I2C:
  120. is_write = cmd == READ_I2C ? false : true;
  121. if (i2c_bus_busy(i2c_bus)) {
  122. i2c_end_transfer(i2c_bus);
  123. }
  124. if (i2c_start_transfer(i2c_bus, address, is_write)) {
  125. ret = AUX_I2C_NACK;
  126. break;
  127. }
  128. ret = AUX_I2C_ACK;
  129. while (len > 0) {
  130. if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
  131. ret = AUX_I2C_NACK;
  132. break;
  133. }
  134. len--;
  135. }
  136. i2c_end_transfer(i2c_bus);
  137. break;
  138. /*
  139. * I2C MOT transactions.
  140. *
  141. * Here we send a start when:
  142. * - We didn't start transaction yet.
  143. * - We had a READ and we do a WRITE.
  144. * - We changed the address.
  145. */
  146. case WRITE_I2C_MOT:
  147. case READ_I2C_MOT:
  148. is_write = cmd == READ_I2C_MOT ? false : true;
  149. ret = AUX_I2C_NACK;
  150. if (!i2c_bus_busy(i2c_bus)) {
  151. /*
  152. * No transactions started..
  153. */
  154. if (i2c_start_transfer(i2c_bus, address, is_write)) {
  155. break;
  156. }
  157. } else if ((address != bus->last_i2c_address) ||
  158. (bus->last_transaction != cmd)) {
  159. /*
  160. * Transaction started but we need to restart..
  161. */
  162. i2c_end_transfer(i2c_bus);
  163. if (i2c_start_transfer(i2c_bus, address, is_write)) {
  164. break;
  165. }
  166. }
  167. bus->last_transaction = cmd;
  168. bus->last_i2c_address = address;
  169. while (len > 0) {
  170. if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
  171. i2c_end_transfer(i2c_bus);
  172. break;
  173. }
  174. len--;
  175. }
  176. if (len == 0) {
  177. ret = AUX_I2C_ACK;
  178. }
  179. break;
  180. default:
  181. qemu_log_mask(LOG_UNIMP, "AUX cmd=%u not implemented\n", cmd);
  182. return AUX_NACK;
  183. }
  184. DPRINTF("reply: %u\n", ret);
  185. return ret;
  186. }
  187. static const TypeInfo aux_bus_info = {
  188. .name = TYPE_AUX_BUS,
  189. .parent = TYPE_BUS,
  190. .instance_size = sizeof(AUXBus),
  191. .class_init = aux_bus_class_init
  192. };
  193. /* aux-i2c implementation (internal not public) */
  194. struct AUXTOI2CState {
  195. /*< private >*/
  196. DeviceState parent_obj;
  197. /*< public >*/
  198. I2CBus *i2c_bus;
  199. };
  200. static void aux_bridge_class_init(ObjectClass *oc, void *data)
  201. {
  202. DeviceClass *dc = DEVICE_CLASS(oc);
  203. /* This device is private and is created only once for each
  204. * aux-bus in aux_bus_init(..). So don't allow the user to add one.
  205. */
  206. dc->user_creatable = false;
  207. }
  208. static void aux_bridge_init(Object *obj)
  209. {
  210. AUXTOI2CState *s = AUXTOI2C(obj);
  211. s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
  212. }
  213. static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge)
  214. {
  215. return bridge->i2c_bus;
  216. }
  217. static const TypeInfo aux_to_i2c_type_info = {
  218. .name = TYPE_AUXTOI2C,
  219. .parent = TYPE_AUX_SLAVE,
  220. .class_init = aux_bridge_class_init,
  221. .instance_size = sizeof(AUXTOI2CState),
  222. .instance_init = aux_bridge_init
  223. };
  224. /* aux-slave implementation */
  225. static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
  226. {
  227. AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
  228. AUXSlave *s;
  229. /* Don't print anything if the device is I2C "bridge". */
  230. if (aux_bus_is_bridge(bus, dev)) {
  231. return;
  232. }
  233. s = AUX_SLAVE(dev);
  234. monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
  235. indent, "",
  236. object_property_get_uint(OBJECT(s->mmio), "addr", NULL),
  237. memory_region_size(s->mmio));
  238. }
  239. void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
  240. {
  241. assert(!aux_slave->mmio);
  242. aux_slave->mmio = mmio;
  243. }
  244. static void aux_slave_class_init(ObjectClass *klass, void *data)
  245. {
  246. DeviceClass *k = DEVICE_CLASS(klass);
  247. set_bit(DEVICE_CATEGORY_MISC, k->categories);
  248. k->bus_type = TYPE_AUX_BUS;
  249. }
  250. static const TypeInfo aux_slave_type_info = {
  251. .name = TYPE_AUX_SLAVE,
  252. .parent = TYPE_DEVICE,
  253. .instance_size = sizeof(AUXSlave),
  254. .abstract = true,
  255. .class_init = aux_slave_class_init,
  256. };
  257. static void aux_register_types(void)
  258. {
  259. type_register_static(&aux_bus_info);
  260. type_register_static(&aux_slave_type_info);
  261. type_register_static(&aux_to_i2c_type_info);
  262. }
  263. type_init(aux_register_types)