jazz.c 15 KB

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  1. /*
  2. * QEMU MIPS Jazz support
  3. *
  4. * Copyright (c) 2007-2008 Hervé Poussineau
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "qemu-common.h"
  26. #include "hw/mips/mips.h"
  27. #include "hw/mips/cpudevs.h"
  28. #include "hw/intc/i8259.h"
  29. #include "hw/dma/i8257.h"
  30. #include "hw/char/serial.h"
  31. #include "hw/char/parallel.h"
  32. #include "hw/isa/isa.h"
  33. #include "hw/block/fdc.h"
  34. #include "sysemu/sysemu.h"
  35. #include "sysemu/arch_init.h"
  36. #include "hw/boards.h"
  37. #include "net/net.h"
  38. #include "hw/scsi/esp.h"
  39. #include "hw/mips/bios.h"
  40. #include "hw/loader.h"
  41. #include "hw/rtc/mc146818rtc.h"
  42. #include "hw/timer/i8254.h"
  43. #include "hw/display/vga.h"
  44. #include "hw/audio/pcspk.h"
  45. #include "hw/input/i8042.h"
  46. #include "hw/sysbus.h"
  47. #include "exec/address-spaces.h"
  48. #include "sysemu/qtest.h"
  49. #include "sysemu/reset.h"
  50. #include "qapi/error.h"
  51. #include "qemu/error-report.h"
  52. #include "qemu/help_option.h"
  53. enum jazz_model_e {
  54. JAZZ_MAGNUM,
  55. JAZZ_PICA61,
  56. };
  57. static void main_cpu_reset(void *opaque)
  58. {
  59. MIPSCPU *cpu = opaque;
  60. cpu_reset(CPU(cpu));
  61. }
  62. static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
  63. {
  64. uint8_t val;
  65. address_space_read(&address_space_memory, 0x90000071,
  66. MEMTXATTRS_UNSPECIFIED, &val, 1);
  67. return val;
  68. }
  69. static void rtc_write(void *opaque, hwaddr addr,
  70. uint64_t val, unsigned size)
  71. {
  72. uint8_t buf = val & 0xff;
  73. address_space_write(&address_space_memory, 0x90000071,
  74. MEMTXATTRS_UNSPECIFIED, &buf, 1);
  75. }
  76. static const MemoryRegionOps rtc_ops = {
  77. .read = rtc_read,
  78. .write = rtc_write,
  79. .endianness = DEVICE_NATIVE_ENDIAN,
  80. };
  81. static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
  82. unsigned size)
  83. {
  84. /*
  85. * Nothing to do. That is only to ensure that
  86. * the current DMA acknowledge cycle is completed.
  87. */
  88. return 0xff;
  89. }
  90. static void dma_dummy_write(void *opaque, hwaddr addr,
  91. uint64_t val, unsigned size)
  92. {
  93. /*
  94. * Nothing to do. That is only to ensure that
  95. * the current DMA acknowledge cycle is completed.
  96. */
  97. }
  98. static const MemoryRegionOps dma_dummy_ops = {
  99. .read = dma_dummy_read,
  100. .write = dma_dummy_write,
  101. .endianness = DEVICE_NATIVE_ENDIAN,
  102. };
  103. #define MAGNUM_BIOS_SIZE_MAX 0x7e000
  104. #define MAGNUM_BIOS_SIZE \
  105. (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
  106. static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
  107. vaddr addr, unsigned size,
  108. MMUAccessType access_type,
  109. int mmu_idx, MemTxAttrs attrs,
  110. MemTxResult response,
  111. uintptr_t retaddr);
  112. static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
  113. vaddr addr, unsigned size,
  114. MMUAccessType access_type,
  115. int mmu_idx, MemTxAttrs attrs,
  116. MemTxResult response,
  117. uintptr_t retaddr)
  118. {
  119. if (access_type != MMU_INST_FETCH) {
  120. /* ignore invalid access (ie do not raise exception) */
  121. return;
  122. }
  123. (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
  124. mmu_idx, attrs, response, retaddr);
  125. }
  126. static void mips_jazz_init(MachineState *machine,
  127. enum jazz_model_e jazz_model)
  128. {
  129. MemoryRegion *address_space = get_system_memory();
  130. char *filename;
  131. int bios_size, n;
  132. MIPSCPU *cpu;
  133. CPUClass *cc;
  134. CPUMIPSState *env;
  135. qemu_irq *i8259;
  136. rc4030_dma *dmas;
  137. IOMMUMemoryRegion *rc4030_dma_mr;
  138. MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
  139. MemoryRegion *isa_io = g_new(MemoryRegion, 1);
  140. MemoryRegion *rtc = g_new(MemoryRegion, 1);
  141. MemoryRegion *i8042 = g_new(MemoryRegion, 1);
  142. MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
  143. NICInfo *nd;
  144. DeviceState *dev, *rc4030;
  145. SysBusDevice *sysbus;
  146. ISABus *isa_bus;
  147. ISADevice *pit;
  148. DriveInfo *fds[MAX_FD];
  149. MemoryRegion *bios = g_new(MemoryRegion, 1);
  150. MemoryRegion *bios2 = g_new(MemoryRegion, 1);
  151. SysBusESPState *sysbus_esp;
  152. ESPState *esp;
  153. if (machine->ram_size > 256 * MiB) {
  154. error_report("RAM size more than 256Mb is not supported");
  155. exit(EXIT_FAILURE);
  156. }
  157. /* init CPUs */
  158. cpu = MIPS_CPU(cpu_create(machine->cpu_type));
  159. env = &cpu->env;
  160. qemu_register_reset(main_cpu_reset, cpu);
  161. /*
  162. * Chipset returns 0 in invalid reads and do not raise data exceptions.
  163. * However, we can't simply add a global memory region to catch
  164. * everything, as this would make all accesses including instruction
  165. * accesses be ignored and not raise exceptions.
  166. * So instead we hijack the do_transaction_failed method on the CPU, and
  167. * do not raise exceptions for data access.
  168. *
  169. * NOTE: this behaviour of raising exceptions for bad instruction
  170. * fetches but not bad data accesses was added in commit 54e755588cf1e9
  171. * to restore behaviour broken by c658b94f6e8c206, but it is not clear
  172. * whether the real hardware behaves this way. It is possible that
  173. * real hardware ignores bad instruction fetches as well -- if so then
  174. * we could replace this hijacking of CPU methods with a simple global
  175. * memory region that catches all memory accesses, as we do on Malta.
  176. */
  177. cc = CPU_GET_CLASS(cpu);
  178. real_do_transaction_failed = cc->do_transaction_failed;
  179. cc->do_transaction_failed = mips_jazz_do_transaction_failed;
  180. /* allocate RAM */
  181. memory_region_add_subregion(address_space, 0, machine->ram);
  182. memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
  183. &error_fatal);
  184. memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
  185. 0, MAGNUM_BIOS_SIZE);
  186. memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
  187. memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
  188. /* load the BIOS image. */
  189. if (bios_name == NULL) {
  190. bios_name = BIOS_FILENAME;
  191. }
  192. filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  193. if (filename) {
  194. bios_size = load_image_targphys(filename, 0xfff00000LL,
  195. MAGNUM_BIOS_SIZE);
  196. g_free(filename);
  197. } else {
  198. bios_size = -1;
  199. }
  200. if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
  201. error_report("Could not load MIPS bios '%s'", bios_name);
  202. exit(1);
  203. }
  204. /* Init CPU internal devices */
  205. cpu_mips_irq_init_cpu(cpu);
  206. cpu_mips_clock_init(cpu);
  207. /* Chipset */
  208. rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
  209. sysbus = SYS_BUS_DEVICE(rc4030);
  210. sysbus_connect_irq(sysbus, 0, env->irq[6]);
  211. sysbus_connect_irq(sysbus, 1, env->irq[3]);
  212. memory_region_add_subregion(address_space, 0x80000000,
  213. sysbus_mmio_get_region(sysbus, 0));
  214. memory_region_add_subregion(address_space, 0xf0000000,
  215. sysbus_mmio_get_region(sysbus, 1));
  216. memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops,
  217. NULL, "dummy_dma", 0x1000);
  218. memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
  219. /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
  220. memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
  221. memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
  222. memory_region_add_subregion(address_space, 0x90000000, isa_io);
  223. memory_region_add_subregion(address_space, 0x91000000, isa_mem);
  224. isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
  225. /* ISA devices */
  226. i8259 = i8259_init(isa_bus, env->irq[4]);
  227. isa_bus_irqs(isa_bus, i8259);
  228. i8257_dma_init(isa_bus, 0);
  229. pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
  230. pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);
  231. /* Video card */
  232. switch (jazz_model) {
  233. case JAZZ_MAGNUM:
  234. dev = qdev_new("sysbus-g364");
  235. sysbus = SYS_BUS_DEVICE(dev);
  236. sysbus_realize_and_unref(sysbus, &error_fatal);
  237. sysbus_mmio_map(sysbus, 0, 0x60080000);
  238. sysbus_mmio_map(sysbus, 1, 0x40000000);
  239. sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
  240. {
  241. /* Simple ROM, so user doesn't have to provide one */
  242. MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
  243. memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000,
  244. &error_fatal);
  245. uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
  246. memory_region_add_subregion(address_space, 0x60000000, rom_mr);
  247. rom[0] = 0x10; /* Mips G364 */
  248. }
  249. break;
  250. case JAZZ_PICA61:
  251. isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
  252. break;
  253. default:
  254. break;
  255. }
  256. /* Network controller */
  257. for (n = 0; n < nb_nics; n++) {
  258. nd = &nd_table[n];
  259. if (!nd->model) {
  260. nd->model = g_strdup("dp83932");
  261. }
  262. if (strcmp(nd->model, "dp83932") == 0) {
  263. qemu_check_nic_model(nd, "dp83932");
  264. dev = qdev_new("dp8393x");
  265. qdev_set_nic_properties(dev, nd);
  266. qdev_prop_set_uint8(dev, "it_shift", 2);
  267. object_property_set_link(OBJECT(dev), "dma_mr",
  268. OBJECT(rc4030_dma_mr), &error_abort);
  269. sysbus = SYS_BUS_DEVICE(dev);
  270. sysbus_realize_and_unref(sysbus, &error_fatal);
  271. sysbus_mmio_map(sysbus, 0, 0x80001000);
  272. sysbus_mmio_map(sysbus, 1, 0x8000b000);
  273. sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
  274. break;
  275. } else if (is_help_option(nd->model)) {
  276. error_report("Supported NICs: dp83932");
  277. exit(1);
  278. } else {
  279. error_report("Unsupported NIC: %s", nd->model);
  280. exit(1);
  281. }
  282. }
  283. /* SCSI adapter */
  284. dev = qdev_new(TYPE_ESP);
  285. sysbus_esp = ESP_STATE(dev);
  286. esp = &sysbus_esp->esp;
  287. esp->dma_memory_read = rc4030_dma_read;
  288. esp->dma_memory_write = rc4030_dma_write;
  289. esp->dma_opaque = dmas[0];
  290. sysbus_esp->it_shift = 0;
  291. /* XXX for now until rc4030 has been changed to use DMA enable signal */
  292. esp->dma_enabled = 1;
  293. sysbus = SYS_BUS_DEVICE(dev);
  294. sysbus_realize_and_unref(sysbus, &error_fatal);
  295. sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
  296. sysbus_mmio_map(sysbus, 0, 0x80002000);
  297. scsi_bus_legacy_handle_cmdline(&esp->bus);
  298. /* Floppy */
  299. for (n = 0; n < MAX_FD; n++) {
  300. fds[n] = drive_get(IF_FLOPPY, 0, n);
  301. }
  302. /* FIXME: we should enable DMA with a custom IsaDma device */
  303. fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
  304. /* Real time clock */
  305. mc146818_rtc_init(isa_bus, 1980, NULL);
  306. memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
  307. memory_region_add_subregion(address_space, 0x80004000, rtc);
  308. /* Keyboard (i8042) */
  309. i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
  310. i8042, 0x1000, 0x1);
  311. memory_region_add_subregion(address_space, 0x80005000, i8042);
  312. /* Serial ports */
  313. if (serial_hd(0)) {
  314. serial_mm_init(address_space, 0x80006000, 0,
  315. qdev_get_gpio_in(rc4030, 8), 8000000 / 16,
  316. serial_hd(0), DEVICE_NATIVE_ENDIAN);
  317. }
  318. if (serial_hd(1)) {
  319. serial_mm_init(address_space, 0x80007000, 0,
  320. qdev_get_gpio_in(rc4030, 9), 8000000 / 16,
  321. serial_hd(1), DEVICE_NATIVE_ENDIAN);
  322. }
  323. /* Parallel port */
  324. if (parallel_hds[0])
  325. parallel_mm_init(address_space, 0x80008000, 0,
  326. qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
  327. /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
  328. /* NVRAM */
  329. dev = qdev_new("ds1225y");
  330. sysbus = SYS_BUS_DEVICE(dev);
  331. sysbus_realize_and_unref(sysbus, &error_fatal);
  332. sysbus_mmio_map(sysbus, 0, 0x80009000);
  333. /* LED indicator */
  334. sysbus_create_simple("jazz-led", 0x8000f000, NULL);
  335. g_free(dmas);
  336. }
  337. static
  338. void mips_magnum_init(MachineState *machine)
  339. {
  340. mips_jazz_init(machine, JAZZ_MAGNUM);
  341. }
  342. static
  343. void mips_pica61_init(MachineState *machine)
  344. {
  345. mips_jazz_init(machine, JAZZ_PICA61);
  346. }
  347. static void mips_magnum_class_init(ObjectClass *oc, void *data)
  348. {
  349. MachineClass *mc = MACHINE_CLASS(oc);
  350. mc->desc = "MIPS Magnum";
  351. mc->init = mips_magnum_init;
  352. mc->block_default_type = IF_SCSI;
  353. mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
  354. mc->default_ram_id = "mips_jazz.ram";
  355. }
  356. static const TypeInfo mips_magnum_type = {
  357. .name = MACHINE_TYPE_NAME("magnum"),
  358. .parent = TYPE_MACHINE,
  359. .class_init = mips_magnum_class_init,
  360. };
  361. static void mips_pica61_class_init(ObjectClass *oc, void *data)
  362. {
  363. MachineClass *mc = MACHINE_CLASS(oc);
  364. mc->desc = "Acer Pica 61";
  365. mc->init = mips_pica61_init;
  366. mc->block_default_type = IF_SCSI;
  367. mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
  368. mc->default_ram_id = "mips_jazz.ram";
  369. }
  370. static const TypeInfo mips_pica61_type = {
  371. .name = MACHINE_TYPE_NAME("pica61"),
  372. .parent = TYPE_MACHINE,
  373. .class_init = mips_pica61_class_init,
  374. };
  375. static void mips_jazz_machine_init(void)
  376. {
  377. type_register_static(&mips_magnum_type);
  378. type_register_static(&mips_pica61_type);
  379. }
  380. type_init(mips_jazz_machine_init)