versatile_i2c.c 3.2 KB

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  1. /*
  2. * ARM SBCon two-wire serial bus interface (I2C bitbang)
  3. * a.k.a. ARM Versatile I2C controller
  4. *
  5. * Copyright (c) 2006-2007 CodeSourcery.
  6. * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
  7. *
  8. * This file is derived from hw/realview.c by Paul Brook
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * as published by the Free Software Foundation; either version 2
  13. * of the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  22. *
  23. */
  24. #include "qemu/osdep.h"
  25. #include "hw/i2c/arm_sbcon_i2c.h"
  26. #include "hw/registerfields.h"
  27. #include "qemu/log.h"
  28. #include "qemu/module.h"
  29. #define VERSATILE_I2C(obj) \
  30. OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
  31. typedef ArmSbconI2CState VersatileI2CState;
  32. REG32(CONTROL_GET, 0)
  33. REG32(CONTROL_SET, 0)
  34. REG32(CONTROL_CLR, 4)
  35. #define SCL BIT(0)
  36. #define SDA BIT(1)
  37. static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
  38. unsigned size)
  39. {
  40. VersatileI2CState *s = (VersatileI2CState *)opaque;
  41. switch (offset) {
  42. case A_CONTROL_SET:
  43. return (s->out & 1) | (s->in << 1);
  44. default:
  45. qemu_log_mask(LOG_GUEST_ERROR,
  46. "%s: Bad offset 0x%x\n", __func__, (int)offset);
  47. return -1;
  48. }
  49. }
  50. static void versatile_i2c_write(void *opaque, hwaddr offset,
  51. uint64_t value, unsigned size)
  52. {
  53. VersatileI2CState *s = (VersatileI2CState *)opaque;
  54. switch (offset) {
  55. case A_CONTROL_SET:
  56. s->out |= value & 3;
  57. break;
  58. case A_CONTROL_CLR:
  59. s->out &= ~value;
  60. break;
  61. default:
  62. qemu_log_mask(LOG_GUEST_ERROR,
  63. "%s: Bad offset 0x%x\n", __func__, (int)offset);
  64. }
  65. bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
  66. s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
  67. }
  68. static const MemoryRegionOps versatile_i2c_ops = {
  69. .read = versatile_i2c_read,
  70. .write = versatile_i2c_write,
  71. .endianness = DEVICE_NATIVE_ENDIAN,
  72. };
  73. static void versatile_i2c_init(Object *obj)
  74. {
  75. DeviceState *dev = DEVICE(obj);
  76. VersatileI2CState *s = VERSATILE_I2C(obj);
  77. SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  78. I2CBus *bus;
  79. bus = i2c_init_bus(dev, "i2c");
  80. bitbang_i2c_init(&s->bitbang, bus);
  81. memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
  82. "arm_sbcon_i2c", 0x1000);
  83. sysbus_init_mmio(sbd, &s->iomem);
  84. }
  85. static const TypeInfo versatile_i2c_info = {
  86. .name = TYPE_VERSATILE_I2C,
  87. .parent = TYPE_SYS_BUS_DEVICE,
  88. .instance_size = sizeof(VersatileI2CState),
  89. .instance_init = versatile_i2c_init,
  90. };
  91. static void versatile_i2c_register_types(void)
  92. {
  93. type_register_static(&versatile_i2c_info);
  94. }
  95. type_init(versatile_i2c_register_types)