serial-isa.c 5.5 KB

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  1. /*
  2. * QEMU 16550A UART emulation
  3. *
  4. * Copyright (c) 2003-2004 Fabrice Bellard
  5. * Copyright (c) 2008 Citrix Systems, Inc.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy
  8. * of this software and associated documentation files (the "Software"), to deal
  9. * in the Software without restriction, including without limitation the rights
  10. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11. * copies of the Software, and to permit persons to whom the Software is
  12. * furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. */
  25. #include "qemu/osdep.h"
  26. #include "qapi/error.h"
  27. #include "qemu/module.h"
  28. #include "sysemu/sysemu.h"
  29. #include "hw/acpi/aml-build.h"
  30. #include "hw/char/serial.h"
  31. #include "hw/isa/isa.h"
  32. #include "hw/qdev-properties.h"
  33. #include "migration/vmstate.h"
  34. #define ISA_SERIAL(obj) OBJECT_CHECK(ISASerialState, (obj), TYPE_ISA_SERIAL)
  35. typedef struct ISASerialState {
  36. ISADevice parent_obj;
  37. uint32_t index;
  38. uint32_t iobase;
  39. uint32_t isairq;
  40. SerialState state;
  41. } ISASerialState;
  42. static const int isa_serial_io[MAX_ISA_SERIAL_PORTS] = {
  43. 0x3f8, 0x2f8, 0x3e8, 0x2e8
  44. };
  45. static const int isa_serial_irq[MAX_ISA_SERIAL_PORTS] = {
  46. 4, 3, 4, 3
  47. };
  48. static void serial_isa_realizefn(DeviceState *dev, Error **errp)
  49. {
  50. static int index;
  51. ISADevice *isadev = ISA_DEVICE(dev);
  52. ISASerialState *isa = ISA_SERIAL(dev);
  53. SerialState *s = &isa->state;
  54. if (isa->index == -1) {
  55. isa->index = index;
  56. }
  57. if (isa->index >= MAX_ISA_SERIAL_PORTS) {
  58. error_setg(errp, "Max. supported number of ISA serial ports is %d.",
  59. MAX_ISA_SERIAL_PORTS);
  60. return;
  61. }
  62. if (isa->iobase == -1) {
  63. isa->iobase = isa_serial_io[isa->index];
  64. }
  65. if (isa->isairq == -1) {
  66. isa->isairq = isa_serial_irq[isa->index];
  67. }
  68. index++;
  69. isa_init_irq(isadev, &s->irq, isa->isairq);
  70. qdev_realize(DEVICE(s), NULL, errp);
  71. qdev_set_legacy_instance_id(dev, isa->iobase, 3);
  72. memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
  73. isa_register_ioport(isadev, &s->io, isa->iobase);
  74. }
  75. static void serial_isa_build_aml(ISADevice *isadev, Aml *scope)
  76. {
  77. ISASerialState *isa = ISA_SERIAL(isadev);
  78. Aml *dev;
  79. Aml *crs;
  80. crs = aml_resource_template();
  81. aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x00, 0x08));
  82. aml_append(crs, aml_irq_no_flags(isa->isairq));
  83. dev = aml_device("COM%d", isa->index + 1);
  84. aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
  85. aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1)));
  86. aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
  87. aml_append(dev, aml_name_decl("_CRS", crs));
  88. aml_append(scope, dev);
  89. }
  90. static const VMStateDescription vmstate_isa_serial = {
  91. .name = "serial",
  92. .version_id = 3,
  93. .minimum_version_id = 2,
  94. .fields = (VMStateField[]) {
  95. VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
  96. VMSTATE_END_OF_LIST()
  97. }
  98. };
  99. static Property serial_isa_properties[] = {
  100. DEFINE_PROP_UINT32("index", ISASerialState, index, -1),
  101. DEFINE_PROP_UINT32("iobase", ISASerialState, iobase, -1),
  102. DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1),
  103. DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
  104. DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0),
  105. DEFINE_PROP_END_OF_LIST(),
  106. };
  107. static void serial_isa_class_initfn(ObjectClass *klass, void *data)
  108. {
  109. DeviceClass *dc = DEVICE_CLASS(klass);
  110. ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
  111. dc->realize = serial_isa_realizefn;
  112. dc->vmsd = &vmstate_isa_serial;
  113. isa->build_aml = serial_isa_build_aml;
  114. device_class_set_props(dc, serial_isa_properties);
  115. set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
  116. }
  117. static void serial_isa_initfn(Object *o)
  118. {
  119. ISASerialState *self = ISA_SERIAL(o);
  120. object_initialize_child(o, "serial", &self->state, TYPE_SERIAL);
  121. }
  122. static const TypeInfo serial_isa_info = {
  123. .name = TYPE_ISA_SERIAL,
  124. .parent = TYPE_ISA_DEVICE,
  125. .instance_size = sizeof(ISASerialState),
  126. .instance_init = serial_isa_initfn,
  127. .class_init = serial_isa_class_initfn,
  128. };
  129. static void serial_register_types(void)
  130. {
  131. type_register_static(&serial_isa_info);
  132. }
  133. type_init(serial_register_types)
  134. static void serial_isa_init(ISABus *bus, int index, Chardev *chr)
  135. {
  136. DeviceState *dev;
  137. ISADevice *isadev;
  138. isadev = isa_new(TYPE_ISA_SERIAL);
  139. dev = DEVICE(isadev);
  140. qdev_prop_set_uint32(dev, "index", index);
  141. qdev_prop_set_chr(dev, "chardev", chr);
  142. isa_realize_and_unref(isadev, bus, &error_fatal);
  143. }
  144. void serial_hds_isa_init(ISABus *bus, int from, int to)
  145. {
  146. int i;
  147. assert(from >= 0);
  148. assert(to <= MAX_ISA_SERIAL_PORTS);
  149. for (i = from; i < to; ++i) {
  150. if (serial_hd(i)) {
  151. serial_isa_init(bus, i, serial_hd(i));
  152. }
  153. }
  154. }