spitz.c 39 KB

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  1. /*
  2. * PXA270-based Clamshell PDA platforms.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Written by Andrzej Zaborowski <balrog@zabor.org>
  6. *
  7. * This code is licensed under the GNU GPL v2.
  8. *
  9. * Contributions after 2012-01-13 are licensed under the terms of the
  10. * GNU GPL, version 2 or (at your option) any later version.
  11. */
  12. #include "qemu/osdep.h"
  13. #include "qapi/error.h"
  14. #include "hw/arm/pxa.h"
  15. #include "hw/arm/boot.h"
  16. #include "sysemu/runstate.h"
  17. #include "sysemu/sysemu.h"
  18. #include "hw/pcmcia.h"
  19. #include "hw/qdev-properties.h"
  20. #include "hw/i2c/i2c.h"
  21. #include "hw/irq.h"
  22. #include "hw/ssi/ssi.h"
  23. #include "hw/block/flash.h"
  24. #include "qemu/timer.h"
  25. #include "qemu/log.h"
  26. #include "hw/arm/sharpsl.h"
  27. #include "ui/console.h"
  28. #include "hw/audio/wm8750.h"
  29. #include "audio/audio.h"
  30. #include "hw/boards.h"
  31. #include "hw/sysbus.h"
  32. #include "hw/misc/max111x.h"
  33. #include "migration/vmstate.h"
  34. #include "exec/address-spaces.h"
  35. #include "cpu.h"
  36. enum spitz_model_e { spitz, akita, borzoi, terrier };
  37. typedef struct {
  38. MachineClass parent;
  39. enum spitz_model_e model;
  40. int arm_id;
  41. } SpitzMachineClass;
  42. typedef struct {
  43. MachineState parent;
  44. PXA2xxState *mpu;
  45. DeviceState *mux;
  46. DeviceState *lcdtg;
  47. DeviceState *ads7846;
  48. DeviceState *max1111;
  49. DeviceState *scp0;
  50. DeviceState *scp1;
  51. DeviceState *misc_gpio;
  52. } SpitzMachineState;
  53. #define TYPE_SPITZ_MACHINE "spitz-common"
  54. #define SPITZ_MACHINE(obj) \
  55. OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
  56. #define SPITZ_MACHINE_GET_CLASS(obj) \
  57. OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
  58. #define SPITZ_MACHINE_CLASS(klass) \
  59. OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
  60. #define zaurus_printf(format, ...) \
  61. fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
  62. /* Spitz Flash */
  63. #define FLASH_BASE 0x0c000000
  64. #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
  65. #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
  66. #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
  67. #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
  68. #define FLASH_ECCCLRR 0x10 /* Clear ECC */
  69. #define FLASH_FLASHIO 0x14 /* Flash I/O */
  70. #define FLASH_FLASHCTL 0x18 /* Flash Control */
  71. #define FLASHCTL_CE0 (1 << 0)
  72. #define FLASHCTL_CLE (1 << 1)
  73. #define FLASHCTL_ALE (1 << 2)
  74. #define FLASHCTL_WP (1 << 3)
  75. #define FLASHCTL_CE1 (1 << 4)
  76. #define FLASHCTL_RYBY (1 << 5)
  77. #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
  78. #define TYPE_SL_NAND "sl-nand"
  79. #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
  80. typedef struct {
  81. SysBusDevice parent_obj;
  82. MemoryRegion iomem;
  83. DeviceState *nand;
  84. uint8_t ctl;
  85. uint8_t manf_id;
  86. uint8_t chip_id;
  87. ECCState ecc;
  88. } SLNANDState;
  89. static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
  90. {
  91. SLNANDState *s = (SLNANDState *) opaque;
  92. int ryby;
  93. switch (addr) {
  94. #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  95. case FLASH_ECCLPLB:
  96. return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  97. BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  98. #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  99. case FLASH_ECCLPUB:
  100. return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  101. BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  102. case FLASH_ECCCP:
  103. return s->ecc.cp;
  104. case FLASH_ECCCNTR:
  105. return s->ecc.count & 0xff;
  106. case FLASH_FLASHCTL:
  107. nand_getpins(s->nand, &ryby);
  108. if (ryby)
  109. return s->ctl | FLASHCTL_RYBY;
  110. else
  111. return s->ctl;
  112. case FLASH_FLASHIO:
  113. if (size == 4) {
  114. return ecc_digest(&s->ecc, nand_getio(s->nand)) |
  115. (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
  116. }
  117. return ecc_digest(&s->ecc, nand_getio(s->nand));
  118. default:
  119. qemu_log_mask(LOG_GUEST_ERROR,
  120. "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
  121. addr);
  122. }
  123. return 0;
  124. }
  125. static void sl_write(void *opaque, hwaddr addr,
  126. uint64_t value, unsigned size)
  127. {
  128. SLNANDState *s = (SLNANDState *) opaque;
  129. switch (addr) {
  130. case FLASH_ECCCLRR:
  131. /* Value is ignored. */
  132. ecc_reset(&s->ecc);
  133. break;
  134. case FLASH_FLASHCTL:
  135. s->ctl = value & 0xff & ~FLASHCTL_RYBY;
  136. nand_setpins(s->nand,
  137. s->ctl & FLASHCTL_CLE,
  138. s->ctl & FLASHCTL_ALE,
  139. s->ctl & FLASHCTL_NCE,
  140. s->ctl & FLASHCTL_WP,
  141. 0);
  142. break;
  143. case FLASH_FLASHIO:
  144. nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
  145. break;
  146. default:
  147. qemu_log_mask(LOG_GUEST_ERROR,
  148. "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
  149. addr);
  150. }
  151. }
  152. enum {
  153. FLASH_128M,
  154. FLASH_1024M,
  155. };
  156. static const MemoryRegionOps sl_ops = {
  157. .read = sl_read,
  158. .write = sl_write,
  159. .endianness = DEVICE_NATIVE_ENDIAN,
  160. };
  161. static void sl_flash_register(PXA2xxState *cpu, int size)
  162. {
  163. DeviceState *dev;
  164. dev = qdev_new(TYPE_SL_NAND);
  165. qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
  166. if (size == FLASH_128M)
  167. qdev_prop_set_uint8(dev, "chip_id", 0x73);
  168. else if (size == FLASH_1024M)
  169. qdev_prop_set_uint8(dev, "chip_id", 0xf1);
  170. sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
  171. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
  172. }
  173. static void sl_nand_init(Object *obj)
  174. {
  175. SLNANDState *s = SL_NAND(obj);
  176. SysBusDevice *dev = SYS_BUS_DEVICE(obj);
  177. s->ctl = 0;
  178. memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40);
  179. sysbus_init_mmio(dev, &s->iomem);
  180. }
  181. static void sl_nand_realize(DeviceState *dev, Error **errp)
  182. {
  183. SLNANDState *s = SL_NAND(dev);
  184. DriveInfo *nand;
  185. /* FIXME use a qdev drive property instead of drive_get() */
  186. nand = drive_get(IF_MTD, 0, 0);
  187. s->nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
  188. s->manf_id, s->chip_id);
  189. }
  190. /* Spitz Keyboard */
  191. #define SPITZ_KEY_STROBE_NUM 11
  192. #define SPITZ_KEY_SENSE_NUM 7
  193. static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
  194. 12, 17, 91, 34, 36, 38, 39
  195. };
  196. static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
  197. 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
  198. };
  199. /* Eighth additional row maps the special keys */
  200. static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
  201. { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
  202. { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
  203. { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
  204. { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
  205. { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
  206. { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
  207. { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
  208. { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
  209. };
  210. #define SPITZ_GPIO_AK_INT 13 /* Remote control */
  211. #define SPITZ_GPIO_SYNC 16 /* Sync button */
  212. #define SPITZ_GPIO_ON_KEY 95 /* Power button */
  213. #define SPITZ_GPIO_SWA 97 /* Lid */
  214. #define SPITZ_GPIO_SWB 96 /* Tablet mode */
  215. /* The special buttons are mapped to unused keys */
  216. static const int spitz_gpiomap[5] = {
  217. SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
  218. SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
  219. };
  220. #define TYPE_SPITZ_KEYBOARD "spitz-keyboard"
  221. #define SPITZ_KEYBOARD(obj) \
  222. OBJECT_CHECK(SpitzKeyboardState, (obj), TYPE_SPITZ_KEYBOARD)
  223. typedef struct {
  224. SysBusDevice parent_obj;
  225. qemu_irq sense[SPITZ_KEY_SENSE_NUM];
  226. qemu_irq gpiomap[5];
  227. int keymap[0x80];
  228. uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
  229. uint16_t strobe_state;
  230. uint16_t sense_state;
  231. uint16_t pre_map[0x100];
  232. uint16_t modifiers;
  233. uint16_t imodifiers;
  234. uint8_t fifo[16];
  235. int fifopos, fifolen;
  236. QEMUTimer *kbdtimer;
  237. } SpitzKeyboardState;
  238. static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
  239. {
  240. int i;
  241. uint16_t strobe, sense = 0;
  242. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
  243. strobe = s->keyrow[i] & s->strobe_state;
  244. if (strobe) {
  245. sense |= 1 << i;
  246. if (!(s->sense_state & (1 << i)))
  247. qemu_irq_raise(s->sense[i]);
  248. } else if (s->sense_state & (1 << i))
  249. qemu_irq_lower(s->sense[i]);
  250. }
  251. s->sense_state = sense;
  252. }
  253. static void spitz_keyboard_strobe(void *opaque, int line, int level)
  254. {
  255. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  256. if (level)
  257. s->strobe_state |= 1 << line;
  258. else
  259. s->strobe_state &= ~(1 << line);
  260. spitz_keyboard_sense_update(s);
  261. }
  262. static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
  263. {
  264. int spitz_keycode = s->keymap[keycode & 0x7f];
  265. if (spitz_keycode == -1)
  266. return;
  267. /* Handle the additional keys */
  268. if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
  269. qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
  270. return;
  271. }
  272. if (keycode & 0x80)
  273. s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
  274. else
  275. s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
  276. spitz_keyboard_sense_update(s);
  277. }
  278. #define SPITZ_MOD_SHIFT (1 << 7)
  279. #define SPITZ_MOD_CTRL (1 << 8)
  280. #define SPITZ_MOD_FN (1 << 9)
  281. #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  282. static void spitz_keyboard_handler(void *opaque, int keycode)
  283. {
  284. SpitzKeyboardState *s = opaque;
  285. uint16_t code;
  286. int mapcode;
  287. switch (keycode) {
  288. case 0x2a: /* Left Shift */
  289. s->modifiers |= 1;
  290. break;
  291. case 0xaa:
  292. s->modifiers &= ~1;
  293. break;
  294. case 0x36: /* Right Shift */
  295. s->modifiers |= 2;
  296. break;
  297. case 0xb6:
  298. s->modifiers &= ~2;
  299. break;
  300. case 0x1d: /* Control */
  301. s->modifiers |= 4;
  302. break;
  303. case 0x9d:
  304. s->modifiers &= ~4;
  305. break;
  306. case 0x38: /* Alt */
  307. s->modifiers |= 8;
  308. break;
  309. case 0xb8:
  310. s->modifiers &= ~8;
  311. break;
  312. }
  313. code = s->pre_map[mapcode = ((s->modifiers & 3) ?
  314. (keycode | SPITZ_MOD_SHIFT) :
  315. (keycode & ~SPITZ_MOD_SHIFT))];
  316. if (code != mapcode) {
  317. #if 0
  318. if ((code & SPITZ_MOD_SHIFT) && !(s->modifiers & 1)) {
  319. QUEUE_KEY(0x2a | (keycode & 0x80));
  320. }
  321. if ((code & SPITZ_MOD_CTRL) && !(s->modifiers & 4)) {
  322. QUEUE_KEY(0x1d | (keycode & 0x80));
  323. }
  324. if ((code & SPITZ_MOD_FN) && !(s->modifiers & 8)) {
  325. QUEUE_KEY(0x38 | (keycode & 0x80));
  326. }
  327. if ((code & SPITZ_MOD_FN) && (s->modifiers & 1)) {
  328. QUEUE_KEY(0x2a | (~keycode & 0x80));
  329. }
  330. if ((code & SPITZ_MOD_FN) && (s->modifiers & 2)) {
  331. QUEUE_KEY(0x36 | (~keycode & 0x80));
  332. }
  333. #else
  334. if (keycode & 0x80) {
  335. if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
  336. QUEUE_KEY(0x2a | 0x80);
  337. if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
  338. QUEUE_KEY(0x1d | 0x80);
  339. if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
  340. QUEUE_KEY(0x38 | 0x80);
  341. if ((s->imodifiers & 0x10) && (s->modifiers & 1))
  342. QUEUE_KEY(0x2a);
  343. if ((s->imodifiers & 0x20) && (s->modifiers & 2))
  344. QUEUE_KEY(0x36);
  345. s->imodifiers = 0;
  346. } else {
  347. if ((code & SPITZ_MOD_SHIFT) &&
  348. !((s->modifiers | s->imodifiers) & 1)) {
  349. QUEUE_KEY(0x2a);
  350. s->imodifiers |= 1;
  351. }
  352. if ((code & SPITZ_MOD_CTRL) &&
  353. !((s->modifiers | s->imodifiers) & 4)) {
  354. QUEUE_KEY(0x1d);
  355. s->imodifiers |= 4;
  356. }
  357. if ((code & SPITZ_MOD_FN) &&
  358. !((s->modifiers | s->imodifiers) & 8)) {
  359. QUEUE_KEY(0x38);
  360. s->imodifiers |= 8;
  361. }
  362. if ((code & SPITZ_MOD_FN) && (s->modifiers & 1) &&
  363. !(s->imodifiers & 0x10)) {
  364. QUEUE_KEY(0x2a | 0x80);
  365. s->imodifiers |= 0x10;
  366. }
  367. if ((code & SPITZ_MOD_FN) && (s->modifiers & 2) &&
  368. !(s->imodifiers & 0x20)) {
  369. QUEUE_KEY(0x36 | 0x80);
  370. s->imodifiers |= 0x20;
  371. }
  372. }
  373. #endif
  374. }
  375. QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
  376. }
  377. static void spitz_keyboard_tick(void *opaque)
  378. {
  379. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  380. if (s->fifolen) {
  381. spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
  382. s->fifolen --;
  383. if (s->fifopos >= 16)
  384. s->fifopos = 0;
  385. }
  386. timer_mod(s->kbdtimer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
  387. NANOSECONDS_PER_SECOND / 32);
  388. }
  389. static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
  390. {
  391. int i;
  392. for (i = 0; i < 0x100; i ++)
  393. s->pre_map[i] = i;
  394. s->pre_map[0x02 | SPITZ_MOD_SHIFT] = 0x02 | SPITZ_MOD_SHIFT; /* exclam */
  395. s->pre_map[0x28 | SPITZ_MOD_SHIFT] = 0x03 | SPITZ_MOD_SHIFT; /* quotedbl */
  396. s->pre_map[0x04 | SPITZ_MOD_SHIFT] = 0x04 | SPITZ_MOD_SHIFT; /* # */
  397. s->pre_map[0x05 | SPITZ_MOD_SHIFT] = 0x05 | SPITZ_MOD_SHIFT; /* dollar */
  398. s->pre_map[0x06 | SPITZ_MOD_SHIFT] = 0x06 | SPITZ_MOD_SHIFT; /* percent */
  399. s->pre_map[0x08 | SPITZ_MOD_SHIFT] = 0x07 | SPITZ_MOD_SHIFT; /* ampersand */
  400. s->pre_map[0x28] = 0x08 | SPITZ_MOD_SHIFT; /* ' */
  401. s->pre_map[0x0a | SPITZ_MOD_SHIFT] = 0x09 | SPITZ_MOD_SHIFT; /* ( */
  402. s->pre_map[0x0b | SPITZ_MOD_SHIFT] = 0x0a | SPITZ_MOD_SHIFT; /* ) */
  403. s->pre_map[0x29 | SPITZ_MOD_SHIFT] = 0x0b | SPITZ_MOD_SHIFT; /* tilde */
  404. s->pre_map[0x03 | SPITZ_MOD_SHIFT] = 0x0c | SPITZ_MOD_SHIFT; /* at */
  405. s->pre_map[0xd3] = 0x0e | SPITZ_MOD_FN; /* Delete */
  406. s->pre_map[0x3a] = 0x0f | SPITZ_MOD_FN; /* Caps_Lock */
  407. s->pre_map[0x07 | SPITZ_MOD_SHIFT] = 0x11 | SPITZ_MOD_FN; /* ^ */
  408. s->pre_map[0x0d] = 0x12 | SPITZ_MOD_FN; /* equal */
  409. s->pre_map[0x0d | SPITZ_MOD_SHIFT] = 0x13 | SPITZ_MOD_FN; /* plus */
  410. s->pre_map[0x1a] = 0x14 | SPITZ_MOD_FN; /* [ */
  411. s->pre_map[0x1b] = 0x15 | SPITZ_MOD_FN; /* ] */
  412. s->pre_map[0x1a | SPITZ_MOD_SHIFT] = 0x16 | SPITZ_MOD_FN; /* { */
  413. s->pre_map[0x1b | SPITZ_MOD_SHIFT] = 0x17 | SPITZ_MOD_FN; /* } */
  414. s->pre_map[0x27] = 0x22 | SPITZ_MOD_FN; /* semicolon */
  415. s->pre_map[0x27 | SPITZ_MOD_SHIFT] = 0x23 | SPITZ_MOD_FN; /* colon */
  416. s->pre_map[0x09 | SPITZ_MOD_SHIFT] = 0x24 | SPITZ_MOD_FN; /* asterisk */
  417. s->pre_map[0x2b] = 0x25 | SPITZ_MOD_FN; /* backslash */
  418. s->pre_map[0x2b | SPITZ_MOD_SHIFT] = 0x26 | SPITZ_MOD_FN; /* bar */
  419. s->pre_map[0x0c | SPITZ_MOD_SHIFT] = 0x30 | SPITZ_MOD_FN; /* _ */
  420. s->pre_map[0x33 | SPITZ_MOD_SHIFT] = 0x33 | SPITZ_MOD_FN; /* less */
  421. s->pre_map[0x35] = 0x33 | SPITZ_MOD_SHIFT; /* slash */
  422. s->pre_map[0x34 | SPITZ_MOD_SHIFT] = 0x34 | SPITZ_MOD_FN; /* greater */
  423. s->pre_map[0x35 | SPITZ_MOD_SHIFT] = 0x34 | SPITZ_MOD_SHIFT; /* question */
  424. s->pre_map[0x49] = 0x48 | SPITZ_MOD_FN; /* Page_Up */
  425. s->pre_map[0x51] = 0x50 | SPITZ_MOD_FN; /* Page_Down */
  426. s->modifiers = 0;
  427. s->imodifiers = 0;
  428. s->fifopos = 0;
  429. s->fifolen = 0;
  430. }
  431. #undef SPITZ_MOD_SHIFT
  432. #undef SPITZ_MOD_CTRL
  433. #undef SPITZ_MOD_FN
  434. static int spitz_keyboard_post_load(void *opaque, int version_id)
  435. {
  436. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  437. /* Release all pressed keys */
  438. memset(s->keyrow, 0, sizeof(s->keyrow));
  439. spitz_keyboard_sense_update(s);
  440. s->modifiers = 0;
  441. s->imodifiers = 0;
  442. s->fifopos = 0;
  443. s->fifolen = 0;
  444. return 0;
  445. }
  446. static void spitz_keyboard_register(PXA2xxState *cpu)
  447. {
  448. int i;
  449. DeviceState *dev;
  450. SpitzKeyboardState *s;
  451. dev = sysbus_create_simple(TYPE_SPITZ_KEYBOARD, -1, NULL);
  452. s = SPITZ_KEYBOARD(dev);
  453. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
  454. qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
  455. for (i = 0; i < 5; i ++)
  456. s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
  457. if (!graphic_rotate)
  458. s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
  459. for (i = 0; i < 5; i++)
  460. qemu_set_irq(s->gpiomap[i], 0);
  461. for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
  462. qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
  463. qdev_get_gpio_in(dev, i));
  464. timer_mod(s->kbdtimer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  465. qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
  466. }
  467. static void spitz_keyboard_init(Object *obj)
  468. {
  469. DeviceState *dev = DEVICE(obj);
  470. SpitzKeyboardState *s = SPITZ_KEYBOARD(obj);
  471. int i, j;
  472. for (i = 0; i < 0x80; i ++)
  473. s->keymap[i] = -1;
  474. for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
  475. for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
  476. if (spitz_keymap[i][j] != -1)
  477. s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
  478. spitz_keyboard_pre_map(s);
  479. qdev_init_gpio_in(dev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
  480. qdev_init_gpio_out(dev, s->sense, SPITZ_KEY_SENSE_NUM);
  481. }
  482. static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
  483. {
  484. SpitzKeyboardState *s = SPITZ_KEYBOARD(dev);
  485. s->kbdtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, spitz_keyboard_tick, s);
  486. }
  487. /* LCD backlight controller */
  488. #define LCDTG_RESCTL 0x00
  489. #define LCDTG_PHACTRL 0x01
  490. #define LCDTG_DUTYCTRL 0x02
  491. #define LCDTG_POWERREG0 0x03
  492. #define LCDTG_POWERREG1 0x04
  493. #define LCDTG_GPOR3 0x05
  494. #define LCDTG_PICTRL 0x06
  495. #define LCDTG_POLCTRL 0x07
  496. #define TYPE_SPITZ_LCDTG "spitz-lcdtg"
  497. #define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
  498. typedef struct {
  499. SSISlave ssidev;
  500. uint32_t bl_intensity;
  501. uint32_t bl_power;
  502. } SpitzLCDTG;
  503. static void spitz_bl_update(SpitzLCDTG *s)
  504. {
  505. if (s->bl_power && s->bl_intensity)
  506. zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
  507. else
  508. zaurus_printf("LCD Backlight now off\n");
  509. }
  510. static inline void spitz_bl_bit5(void *opaque, int line, int level)
  511. {
  512. SpitzLCDTG *s = opaque;
  513. int prev = s->bl_intensity;
  514. if (level)
  515. s->bl_intensity &= ~0x20;
  516. else
  517. s->bl_intensity |= 0x20;
  518. if (s->bl_power && prev != s->bl_intensity)
  519. spitz_bl_update(s);
  520. }
  521. static inline void spitz_bl_power(void *opaque, int line, int level)
  522. {
  523. SpitzLCDTG *s = opaque;
  524. s->bl_power = !!level;
  525. spitz_bl_update(s);
  526. }
  527. static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
  528. {
  529. SpitzLCDTG *s = SPITZ_LCDTG(dev);
  530. int addr;
  531. addr = value >> 5;
  532. value &= 0x1f;
  533. switch (addr) {
  534. case LCDTG_RESCTL:
  535. if (value)
  536. zaurus_printf("LCD in QVGA mode\n");
  537. else
  538. zaurus_printf("LCD in VGA mode\n");
  539. break;
  540. case LCDTG_DUTYCTRL:
  541. s->bl_intensity &= ~0x1f;
  542. s->bl_intensity |= value;
  543. if (s->bl_power)
  544. spitz_bl_update(s);
  545. break;
  546. case LCDTG_POWERREG0:
  547. /* Set common voltage to M62332FP */
  548. break;
  549. }
  550. return 0;
  551. }
  552. static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
  553. {
  554. SpitzLCDTG *s = SPITZ_LCDTG(ssi);
  555. DeviceState *dev = DEVICE(s);
  556. s->bl_power = 0;
  557. s->bl_intensity = 0x20;
  558. qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
  559. qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
  560. }
  561. /* SSP devices */
  562. #define CORGI_SSP_PORT 2
  563. #define SPITZ_GPIO_LCDCON_CS 53
  564. #define SPITZ_GPIO_ADS7846_CS 14
  565. #define SPITZ_GPIO_MAX1111_CS 20
  566. #define SPITZ_GPIO_TP_INT 11
  567. #define TYPE_CORGI_SSP "corgi-ssp"
  568. #define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
  569. /* "Demux" the signal based on current chipselect */
  570. typedef struct {
  571. SSISlave ssidev;
  572. SSIBus *bus[3];
  573. uint32_t enable[3];
  574. } CorgiSSPState;
  575. static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
  576. {
  577. CorgiSSPState *s = CORGI_SSP(dev);
  578. int i;
  579. for (i = 0; i < 3; i++) {
  580. if (s->enable[i]) {
  581. return ssi_transfer(s->bus[i], value);
  582. }
  583. }
  584. return 0;
  585. }
  586. static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  587. {
  588. CorgiSSPState *s = (CorgiSSPState *)opaque;
  589. assert(line >= 0 && line < 3);
  590. s->enable[line] = !level;
  591. }
  592. #define MAX1111_BATT_VOLT 1
  593. #define MAX1111_BATT_TEMP 2
  594. #define MAX1111_ACIN_VOLT 3
  595. #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
  596. #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
  597. #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
  598. static void corgi_ssp_realize(SSISlave *d, Error **errp)
  599. {
  600. DeviceState *dev = DEVICE(d);
  601. CorgiSSPState *s = CORGI_SSP(d);
  602. qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
  603. s->bus[0] = ssi_create_bus(dev, "ssi0");
  604. s->bus[1] = ssi_create_bus(dev, "ssi1");
  605. s->bus[2] = ssi_create_bus(dev, "ssi2");
  606. }
  607. static void spitz_ssp_attach(SpitzMachineState *sms)
  608. {
  609. void *bus;
  610. sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
  611. TYPE_CORGI_SSP);
  612. bus = qdev_get_child_bus(sms->mux, "ssi0");
  613. sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
  614. bus = qdev_get_child_bus(sms->mux, "ssi1");
  615. sms->ads7846 = ssi_create_slave(bus, "ads7846");
  616. qdev_connect_gpio_out(sms->ads7846, 0,
  617. qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
  618. bus = qdev_get_child_bus(sms->mux, "ssi2");
  619. sms->max1111 = qdev_new(TYPE_MAX_1111);
  620. qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
  621. SPITZ_BATTERY_VOLT);
  622. qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
  623. qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
  624. SPITZ_CHARGEON_ACIN);
  625. ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
  626. qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
  627. qdev_get_gpio_in(sms->mux, 0));
  628. qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
  629. qdev_get_gpio_in(sms->mux, 1));
  630. qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
  631. qdev_get_gpio_in(sms->mux, 2));
  632. }
  633. /* CF Microdrive */
  634. static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
  635. {
  636. PCMCIACardState *md;
  637. DriveInfo *dinfo;
  638. dinfo = drive_get(IF_IDE, 0, 0);
  639. if (!dinfo || dinfo->media_cd)
  640. return;
  641. md = dscm1xxxx_init(dinfo);
  642. pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
  643. }
  644. /* Wm8750 and Max7310 on I2C */
  645. #define AKITA_MAX_ADDR 0x18
  646. #define SPITZ_WM_ADDRL 0x1b
  647. #define SPITZ_WM_ADDRH 0x1a
  648. #define SPITZ_GPIO_WM 5
  649. static void spitz_wm8750_addr(void *opaque, int line, int level)
  650. {
  651. I2CSlave *wm = (I2CSlave *) opaque;
  652. if (level)
  653. i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
  654. else
  655. i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
  656. }
  657. static void spitz_i2c_setup(PXA2xxState *cpu)
  658. {
  659. /* Attach the CPU on one end of our I2C bus. */
  660. I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
  661. DeviceState *wm;
  662. /* Attach a WM8750 to the bus */
  663. wm = DEVICE(i2c_slave_create_simple(bus, TYPE_WM8750, 0));
  664. spitz_wm8750_addr(wm, 0, 0);
  665. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
  666. qemu_allocate_irq(spitz_wm8750_addr, wm, 0));
  667. /* .. and to the sound interface. */
  668. cpu->i2s->opaque = wm;
  669. cpu->i2s->codec_out = wm8750_dac_dat;
  670. cpu->i2s->codec_in = wm8750_adc_dat;
  671. wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
  672. }
  673. static void spitz_akita_i2c_setup(PXA2xxState *cpu)
  674. {
  675. /* Attach a Max7310 to Akita I2C bus. */
  676. i2c_slave_create_simple(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
  677. AKITA_MAX_ADDR);
  678. }
  679. /* Other peripherals */
  680. /*
  681. * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
  682. *
  683. * QEMU interface:
  684. * + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
  685. * these currently just print messages that the line has been signalled
  686. * + named GPIO input "adc-temp-on": set to cause the battery-temperature
  687. * value to be passed to the max111x ADC
  688. * + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
  689. */
  690. #define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
  691. #define SPITZ_MISC_GPIO(obj) \
  692. OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
  693. typedef struct SpitzMiscGPIOState {
  694. SysBusDevice parent_obj;
  695. qemu_irq adc_value;
  696. } SpitzMiscGPIOState;
  697. static void spitz_misc_charging(void *opaque, int n, int level)
  698. {
  699. zaurus_printf("Charging %s.\n", level ? "off" : "on");
  700. }
  701. static void spitz_misc_discharging(void *opaque, int n, int level)
  702. {
  703. zaurus_printf("Discharging %s.\n", level ? "off" : "on");
  704. }
  705. static void spitz_misc_green_led(void *opaque, int n, int level)
  706. {
  707. zaurus_printf("Green LED %s.\n", level ? "off" : "on");
  708. }
  709. static void spitz_misc_orange_led(void *opaque, int n, int level)
  710. {
  711. zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
  712. }
  713. static void spitz_misc_adc_temp(void *opaque, int n, int level)
  714. {
  715. SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
  716. int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
  717. qemu_set_irq(s->adc_value, batt_temp);
  718. }
  719. static void spitz_misc_gpio_init(Object *obj)
  720. {
  721. SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
  722. DeviceState *dev = DEVICE(obj);
  723. qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
  724. qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
  725. qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
  726. qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
  727. qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
  728. qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
  729. }
  730. #define SPITZ_SCP_LED_GREEN 1
  731. #define SPITZ_SCP_JK_B 2
  732. #define SPITZ_SCP_CHRG_ON 3
  733. #define SPITZ_SCP_MUTE_L 4
  734. #define SPITZ_SCP_MUTE_R 5
  735. #define SPITZ_SCP_CF_POWER 6
  736. #define SPITZ_SCP_LED_ORANGE 7
  737. #define SPITZ_SCP_JK_A 8
  738. #define SPITZ_SCP_ADC_TEMP_ON 9
  739. #define SPITZ_SCP2_IR_ON 1
  740. #define SPITZ_SCP2_AKIN_PULLUP 2
  741. #define SPITZ_SCP2_BACKLIGHT_CONT 7
  742. #define SPITZ_SCP2_BACKLIGHT_ON 8
  743. #define SPITZ_SCP2_MIC_BIAS 9
  744. static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
  745. {
  746. DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
  747. sms->misc_gpio = miscdev;
  748. qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
  749. qdev_get_gpio_in_named(miscdev, "charging", 0));
  750. qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
  751. qdev_get_gpio_in_named(miscdev, "discharging", 0));
  752. qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
  753. qdev_get_gpio_in_named(miscdev, "green-led", 0));
  754. qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
  755. qdev_get_gpio_in_named(miscdev, "orange-led", 0));
  756. qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
  757. qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
  758. qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
  759. qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
  760. if (sms->scp1) {
  761. qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
  762. qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
  763. qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
  764. qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
  765. }
  766. }
  767. #define SPITZ_GPIO_HSYNC 22
  768. #define SPITZ_GPIO_SD_DETECT 9
  769. #define SPITZ_GPIO_SD_WP 81
  770. #define SPITZ_GPIO_ON_RESET 89
  771. #define SPITZ_GPIO_BAT_COVER 90
  772. #define SPITZ_GPIO_CF1_IRQ 105
  773. #define SPITZ_GPIO_CF1_CD 94
  774. #define SPITZ_GPIO_CF2_IRQ 106
  775. #define SPITZ_GPIO_CF2_CD 93
  776. static int spitz_hsync;
  777. static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
  778. {
  779. PXA2xxState *cpu = (PXA2xxState *) opaque;
  780. qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
  781. spitz_hsync ^= 1;
  782. }
  783. static void spitz_reset(void *opaque, int line, int level)
  784. {
  785. if (level) {
  786. qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  787. }
  788. }
  789. static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  790. {
  791. qemu_irq lcd_hsync;
  792. qemu_irq reset;
  793. /*
  794. * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
  795. * read to satisfy broken guests that poll-wait for hsync.
  796. * Simulating a real hsync event would be less practical and
  797. * wouldn't guarantee that a guest ever exits the loop.
  798. */
  799. spitz_hsync = 0;
  800. lcd_hsync = qemu_allocate_irq(spitz_lcd_hsync_handler, cpu, 0);
  801. pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
  802. pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
  803. /* MMC/SD host */
  804. pxa2xx_mmci_handlers(cpu->mmc,
  805. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
  806. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
  807. /* Battery lock always closed */
  808. qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
  809. /* Handle reset */
  810. reset = qemu_allocate_irq(spitz_reset, cpu, 0);
  811. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, reset);
  812. /* PCMCIA signals: card's IRQ and Card-Detect */
  813. if (slots >= 1)
  814. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
  815. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
  816. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
  817. if (slots >= 2)
  818. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
  819. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
  820. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
  821. }
  822. /* Board init. */
  823. #define SPITZ_RAM 0x04000000
  824. #define SPITZ_ROM 0x00800000
  825. static struct arm_boot_info spitz_binfo = {
  826. .loader_start = PXA2XX_SDRAM_BASE,
  827. .ram_size = 0x04000000,
  828. };
  829. static void spitz_common_init(MachineState *machine)
  830. {
  831. SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
  832. SpitzMachineState *sms = SPITZ_MACHINE(machine);
  833. enum spitz_model_e model = smc->model;
  834. PXA2xxState *mpu;
  835. MemoryRegion *address_space_mem = get_system_memory();
  836. MemoryRegion *rom = g_new(MemoryRegion, 1);
  837. /* Setup CPU & memory */
  838. mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
  839. machine->cpu_type);
  840. sms->mpu = mpu;
  841. sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
  842. memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
  843. memory_region_add_subregion(address_space_mem, 0, rom);
  844. /* Setup peripherals */
  845. spitz_keyboard_register(mpu);
  846. spitz_ssp_attach(sms);
  847. sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
  848. if (model != akita) {
  849. sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
  850. } else {
  851. sms->scp1 = NULL;
  852. }
  853. spitz_scoop_gpio_setup(sms);
  854. spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
  855. spitz_i2c_setup(mpu);
  856. if (model == akita)
  857. spitz_akita_i2c_setup(mpu);
  858. if (model == terrier)
  859. /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
  860. spitz_microdrive_attach(mpu, 1);
  861. else if (model != akita)
  862. /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
  863. spitz_microdrive_attach(mpu, 0);
  864. spitz_binfo.board_id = smc->arm_id;
  865. arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
  866. sl_bootparam_write(SL_PXA_PARAM_BASE);
  867. }
  868. static void spitz_common_class_init(ObjectClass *oc, void *data)
  869. {
  870. MachineClass *mc = MACHINE_CLASS(oc);
  871. mc->block_default_type = IF_IDE;
  872. mc->ignore_memory_transaction_failures = true;
  873. mc->init = spitz_common_init;
  874. }
  875. static const TypeInfo spitz_common_info = {
  876. .name = TYPE_SPITZ_MACHINE,
  877. .parent = TYPE_MACHINE,
  878. .abstract = true,
  879. .instance_size = sizeof(SpitzMachineState),
  880. .class_size = sizeof(SpitzMachineClass),
  881. .class_init = spitz_common_class_init,
  882. };
  883. static void akitapda_class_init(ObjectClass *oc, void *data)
  884. {
  885. MachineClass *mc = MACHINE_CLASS(oc);
  886. SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
  887. mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
  888. mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
  889. smc->model = akita;
  890. smc->arm_id = 0x2e8;
  891. }
  892. static const TypeInfo akitapda_type = {
  893. .name = MACHINE_TYPE_NAME("akita"),
  894. .parent = TYPE_SPITZ_MACHINE,
  895. .class_init = akitapda_class_init,
  896. };
  897. static void spitzpda_class_init(ObjectClass *oc, void *data)
  898. {
  899. MachineClass *mc = MACHINE_CLASS(oc);
  900. SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
  901. mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
  902. mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
  903. smc->model = spitz;
  904. smc->arm_id = 0x2c9;
  905. }
  906. static const TypeInfo spitzpda_type = {
  907. .name = MACHINE_TYPE_NAME("spitz"),
  908. .parent = TYPE_SPITZ_MACHINE,
  909. .class_init = spitzpda_class_init,
  910. };
  911. static void borzoipda_class_init(ObjectClass *oc, void *data)
  912. {
  913. MachineClass *mc = MACHINE_CLASS(oc);
  914. SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
  915. mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
  916. mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
  917. smc->model = borzoi;
  918. smc->arm_id = 0x33f;
  919. }
  920. static const TypeInfo borzoipda_type = {
  921. .name = MACHINE_TYPE_NAME("borzoi"),
  922. .parent = TYPE_SPITZ_MACHINE,
  923. .class_init = borzoipda_class_init,
  924. };
  925. static void terrierpda_class_init(ObjectClass *oc, void *data)
  926. {
  927. MachineClass *mc = MACHINE_CLASS(oc);
  928. SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
  929. mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
  930. mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
  931. smc->model = terrier;
  932. smc->arm_id = 0x33f;
  933. }
  934. static const TypeInfo terrierpda_type = {
  935. .name = MACHINE_TYPE_NAME("terrier"),
  936. .parent = TYPE_SPITZ_MACHINE,
  937. .class_init = terrierpda_class_init,
  938. };
  939. static void spitz_machine_init(void)
  940. {
  941. type_register_static(&spitz_common_info);
  942. type_register_static(&akitapda_type);
  943. type_register_static(&spitzpda_type);
  944. type_register_static(&borzoipda_type);
  945. type_register_static(&terrierpda_type);
  946. }
  947. type_init(spitz_machine_init)
  948. static bool is_version_0(void *opaque, int version_id)
  949. {
  950. return version_id == 0;
  951. }
  952. static VMStateDescription vmstate_sl_nand_info = {
  953. .name = "sl-nand",
  954. .version_id = 0,
  955. .minimum_version_id = 0,
  956. .fields = (VMStateField[]) {
  957. VMSTATE_UINT8(ctl, SLNANDState),
  958. VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
  959. VMSTATE_END_OF_LIST(),
  960. },
  961. };
  962. static Property sl_nand_properties[] = {
  963. DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
  964. DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
  965. DEFINE_PROP_END_OF_LIST(),
  966. };
  967. static void sl_nand_class_init(ObjectClass *klass, void *data)
  968. {
  969. DeviceClass *dc = DEVICE_CLASS(klass);
  970. dc->vmsd = &vmstate_sl_nand_info;
  971. device_class_set_props(dc, sl_nand_properties);
  972. dc->realize = sl_nand_realize;
  973. /* Reason: init() method uses drive_get() */
  974. dc->user_creatable = false;
  975. }
  976. static const TypeInfo sl_nand_info = {
  977. .name = TYPE_SL_NAND,
  978. .parent = TYPE_SYS_BUS_DEVICE,
  979. .instance_size = sizeof(SLNANDState),
  980. .instance_init = sl_nand_init,
  981. .class_init = sl_nand_class_init,
  982. };
  983. static VMStateDescription vmstate_spitz_kbd = {
  984. .name = "spitz-keyboard",
  985. .version_id = 1,
  986. .minimum_version_id = 0,
  987. .post_load = spitz_keyboard_post_load,
  988. .fields = (VMStateField[]) {
  989. VMSTATE_UINT16(sense_state, SpitzKeyboardState),
  990. VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
  991. VMSTATE_UNUSED_TEST(is_version_0, 5),
  992. VMSTATE_END_OF_LIST(),
  993. },
  994. };
  995. static void spitz_keyboard_class_init(ObjectClass *klass, void *data)
  996. {
  997. DeviceClass *dc = DEVICE_CLASS(klass);
  998. dc->vmsd = &vmstate_spitz_kbd;
  999. dc->realize = spitz_keyboard_realize;
  1000. }
  1001. static const TypeInfo spitz_keyboard_info = {
  1002. .name = TYPE_SPITZ_KEYBOARD,
  1003. .parent = TYPE_SYS_BUS_DEVICE,
  1004. .instance_size = sizeof(SpitzKeyboardState),
  1005. .instance_init = spitz_keyboard_init,
  1006. .class_init = spitz_keyboard_class_init,
  1007. };
  1008. static const VMStateDescription vmstate_corgi_ssp_regs = {
  1009. .name = "corgi-ssp",
  1010. .version_id = 2,
  1011. .minimum_version_id = 2,
  1012. .fields = (VMStateField[]) {
  1013. VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
  1014. VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
  1015. VMSTATE_END_OF_LIST(),
  1016. }
  1017. };
  1018. static void corgi_ssp_class_init(ObjectClass *klass, void *data)
  1019. {
  1020. DeviceClass *dc = DEVICE_CLASS(klass);
  1021. SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
  1022. k->realize = corgi_ssp_realize;
  1023. k->transfer = corgi_ssp_transfer;
  1024. dc->vmsd = &vmstate_corgi_ssp_regs;
  1025. }
  1026. static const TypeInfo corgi_ssp_info = {
  1027. .name = TYPE_CORGI_SSP,
  1028. .parent = TYPE_SSI_SLAVE,
  1029. .instance_size = sizeof(CorgiSSPState),
  1030. .class_init = corgi_ssp_class_init,
  1031. };
  1032. static const VMStateDescription vmstate_spitz_lcdtg_regs = {
  1033. .name = "spitz-lcdtg",
  1034. .version_id = 1,
  1035. .minimum_version_id = 1,
  1036. .fields = (VMStateField[]) {
  1037. VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
  1038. VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
  1039. VMSTATE_UINT32(bl_power, SpitzLCDTG),
  1040. VMSTATE_END_OF_LIST(),
  1041. }
  1042. };
  1043. static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
  1044. {
  1045. DeviceClass *dc = DEVICE_CLASS(klass);
  1046. SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
  1047. k->realize = spitz_lcdtg_realize;
  1048. k->transfer = spitz_lcdtg_transfer;
  1049. dc->vmsd = &vmstate_spitz_lcdtg_regs;
  1050. }
  1051. static const TypeInfo spitz_lcdtg_info = {
  1052. .name = TYPE_SPITZ_LCDTG,
  1053. .parent = TYPE_SSI_SLAVE,
  1054. .instance_size = sizeof(SpitzLCDTG),
  1055. .class_init = spitz_lcdtg_class_init,
  1056. };
  1057. static const TypeInfo spitz_misc_gpio_info = {
  1058. .name = TYPE_SPITZ_MISC_GPIO,
  1059. .parent = TYPE_SYS_BUS_DEVICE,
  1060. .instance_size = sizeof(SpitzMiscGPIOState),
  1061. .instance_init = spitz_misc_gpio_init,
  1062. /*
  1063. * No class_init required: device has no internal state so does not
  1064. * need to set up reset or vmstate, and does not have a realize method.
  1065. */
  1066. };
  1067. static void spitz_register_types(void)
  1068. {
  1069. type_register_static(&corgi_ssp_info);
  1070. type_register_static(&spitz_lcdtg_info);
  1071. type_register_static(&spitz_keyboard_info);
  1072. type_register_static(&sl_nand_info);
  1073. type_register_static(&spitz_misc_gpio_info);
  1074. }
  1075. type_init(spitz_register_types)