pxa2xx_gpio.c 10 KB

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  1. /*
  2. * Intel XScale PXA255/270 GPIO controller emulation.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Written by Andrzej Zaborowski <balrog@zabor.org>
  6. *
  7. * This code is licensed under the GPL.
  8. */
  9. #include "qemu/osdep.h"
  10. #include "cpu.h"
  11. #include "hw/irq.h"
  12. #include "hw/qdev-properties.h"
  13. #include "hw/sysbus.h"
  14. #include "migration/vmstate.h"
  15. #include "hw/arm/pxa.h"
  16. #include "qapi/error.h"
  17. #include "qemu/log.h"
  18. #include "qemu/module.h"
  19. #define PXA2XX_GPIO_BANKS 4
  20. #define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
  21. #define PXA2XX_GPIO(obj) \
  22. OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
  23. typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
  24. struct PXA2xxGPIOInfo {
  25. /*< private >*/
  26. SysBusDevice parent_obj;
  27. /*< public >*/
  28. MemoryRegion iomem;
  29. qemu_irq irq0, irq1, irqX;
  30. int lines;
  31. int ncpu;
  32. ARMCPU *cpu;
  33. /* XXX: GNU C vectors are more suitable */
  34. uint32_t ilevel[PXA2XX_GPIO_BANKS];
  35. uint32_t olevel[PXA2XX_GPIO_BANKS];
  36. uint32_t dir[PXA2XX_GPIO_BANKS];
  37. uint32_t rising[PXA2XX_GPIO_BANKS];
  38. uint32_t falling[PXA2XX_GPIO_BANKS];
  39. uint32_t status[PXA2XX_GPIO_BANKS];
  40. uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
  41. uint32_t prev_level[PXA2XX_GPIO_BANKS];
  42. qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
  43. qemu_irq read_notify;
  44. };
  45. static struct {
  46. enum {
  47. GPIO_NONE,
  48. GPLR,
  49. GPSR,
  50. GPCR,
  51. GPDR,
  52. GRER,
  53. GFER,
  54. GEDR,
  55. GAFR_L,
  56. GAFR_U,
  57. } reg;
  58. int bank;
  59. } pxa2xx_gpio_regs[0x200] = {
  60. [0 ... 0x1ff] = { GPIO_NONE, 0 },
  61. #define PXA2XX_REG(reg, a0, a1, a2, a3) \
  62. [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
  63. PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
  64. PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
  65. PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
  66. PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
  67. PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
  68. PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
  69. PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
  70. PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
  71. PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
  72. };
  73. static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
  74. {
  75. if (s->status[0] & (1 << 0))
  76. qemu_irq_raise(s->irq0);
  77. else
  78. qemu_irq_lower(s->irq0);
  79. if (s->status[0] & (1 << 1))
  80. qemu_irq_raise(s->irq1);
  81. else
  82. qemu_irq_lower(s->irq1);
  83. if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
  84. qemu_irq_raise(s->irqX);
  85. else
  86. qemu_irq_lower(s->irqX);
  87. }
  88. /* Bitmap of pins used as standby and sleep wake-up sources. */
  89. static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
  90. 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
  91. };
  92. static void pxa2xx_gpio_set(void *opaque, int line, int level)
  93. {
  94. PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
  95. CPUState *cpu = CPU(s->cpu);
  96. int bank;
  97. uint32_t mask;
  98. if (line >= s->lines) {
  99. printf("%s: No GPIO pin %i\n", __func__, line);
  100. return;
  101. }
  102. bank = line >> 5;
  103. mask = 1U << (line & 31);
  104. if (level) {
  105. s->status[bank] |= s->rising[bank] & mask &
  106. ~s->ilevel[bank] & ~s->dir[bank];
  107. s->ilevel[bank] |= mask;
  108. } else {
  109. s->status[bank] |= s->falling[bank] & mask &
  110. s->ilevel[bank] & ~s->dir[bank];
  111. s->ilevel[bank] &= ~mask;
  112. }
  113. if (s->status[bank] & mask)
  114. pxa2xx_gpio_irq_update(s);
  115. /* Wake-up GPIOs */
  116. if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
  117. cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
  118. }
  119. }
  120. static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
  121. uint32_t level, diff;
  122. int i, bit, line;
  123. for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
  124. level = s->olevel[i] & s->dir[i];
  125. for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
  126. bit = ctz32(diff);
  127. line = bit + 32 * i;
  128. qemu_set_irq(s->handler[line], (level >> bit) & 1);
  129. }
  130. s->prev_level[i] = level;
  131. }
  132. }
  133. static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
  134. unsigned size)
  135. {
  136. PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
  137. uint32_t ret;
  138. int bank;
  139. if (offset >= 0x200)
  140. return 0;
  141. bank = pxa2xx_gpio_regs[offset].bank;
  142. switch (pxa2xx_gpio_regs[offset].reg) {
  143. case GPDR: /* GPIO Pin-Direction registers */
  144. return s->dir[bank];
  145. case GPSR: /* GPIO Pin-Output Set registers */
  146. qemu_log_mask(LOG_GUEST_ERROR,
  147. "pxa2xx GPIO: read from write only register GPSR\n");
  148. return 0;
  149. case GPCR: /* GPIO Pin-Output Clear registers */
  150. qemu_log_mask(LOG_GUEST_ERROR,
  151. "pxa2xx GPIO: read from write only register GPCR\n");
  152. return 0;
  153. case GRER: /* GPIO Rising-Edge Detect Enable registers */
  154. return s->rising[bank];
  155. case GFER: /* GPIO Falling-Edge Detect Enable registers */
  156. return s->falling[bank];
  157. case GAFR_L: /* GPIO Alternate Function registers */
  158. return s->gafr[bank * 2];
  159. case GAFR_U: /* GPIO Alternate Function registers */
  160. return s->gafr[bank * 2 + 1];
  161. case GPLR: /* GPIO Pin-Level registers */
  162. ret = (s->olevel[bank] & s->dir[bank]) |
  163. (s->ilevel[bank] & ~s->dir[bank]);
  164. qemu_irq_raise(s->read_notify);
  165. return ret;
  166. case GEDR: /* GPIO Edge Detect Status registers */
  167. return s->status[bank];
  168. default:
  169. qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
  170. __func__, offset);
  171. }
  172. return 0;
  173. }
  174. static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
  175. uint64_t value, unsigned size)
  176. {
  177. PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
  178. int bank;
  179. if (offset >= 0x200)
  180. return;
  181. bank = pxa2xx_gpio_regs[offset].bank;
  182. switch (pxa2xx_gpio_regs[offset].reg) {
  183. case GPDR: /* GPIO Pin-Direction registers */
  184. s->dir[bank] = value;
  185. pxa2xx_gpio_handler_update(s);
  186. break;
  187. case GPSR: /* GPIO Pin-Output Set registers */
  188. s->olevel[bank] |= value;
  189. pxa2xx_gpio_handler_update(s);
  190. break;
  191. case GPCR: /* GPIO Pin-Output Clear registers */
  192. s->olevel[bank] &= ~value;
  193. pxa2xx_gpio_handler_update(s);
  194. break;
  195. case GRER: /* GPIO Rising-Edge Detect Enable registers */
  196. s->rising[bank] = value;
  197. break;
  198. case GFER: /* GPIO Falling-Edge Detect Enable registers */
  199. s->falling[bank] = value;
  200. break;
  201. case GAFR_L: /* GPIO Alternate Function registers */
  202. s->gafr[bank * 2] = value;
  203. break;
  204. case GAFR_U: /* GPIO Alternate Function registers */
  205. s->gafr[bank * 2 + 1] = value;
  206. break;
  207. case GEDR: /* GPIO Edge Detect Status registers */
  208. s->status[bank] &= ~value;
  209. pxa2xx_gpio_irq_update(s);
  210. break;
  211. default:
  212. qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
  213. __func__, offset);
  214. }
  215. }
  216. static const MemoryRegionOps pxa_gpio_ops = {
  217. .read = pxa2xx_gpio_read,
  218. .write = pxa2xx_gpio_write,
  219. .endianness = DEVICE_NATIVE_ENDIAN,
  220. };
  221. DeviceState *pxa2xx_gpio_init(hwaddr base,
  222. ARMCPU *cpu, DeviceState *pic, int lines)
  223. {
  224. CPUState *cs = CPU(cpu);
  225. DeviceState *dev;
  226. dev = qdev_new(TYPE_PXA2XX_GPIO);
  227. qdev_prop_set_int32(dev, "lines", lines);
  228. qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
  229. sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
  230. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
  231. sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
  232. qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
  233. sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
  234. qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
  235. sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
  236. qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
  237. return dev;
  238. }
  239. static void pxa2xx_gpio_initfn(Object *obj)
  240. {
  241. SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  242. DeviceState *dev = DEVICE(sbd);
  243. PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
  244. memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
  245. s, "pxa2xx-gpio", 0x1000);
  246. sysbus_init_mmio(sbd, &s->iomem);
  247. sysbus_init_irq(sbd, &s->irq0);
  248. sysbus_init_irq(sbd, &s->irq1);
  249. sysbus_init_irq(sbd, &s->irqX);
  250. }
  251. static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
  252. {
  253. PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
  254. s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
  255. qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
  256. qdev_init_gpio_out(dev, s->handler, s->lines);
  257. }
  258. /*
  259. * Registers a callback to notify on GPLR reads. This normally
  260. * shouldn't be needed but it is used for the hack on Spitz machines.
  261. */
  262. void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
  263. {
  264. PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
  265. s->read_notify = handler;
  266. }
  267. static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
  268. .name = "pxa2xx-gpio",
  269. .version_id = 1,
  270. .minimum_version_id = 1,
  271. .fields = (VMStateField[]) {
  272. VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  273. VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  274. VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  275. VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  276. VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  277. VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  278. VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
  279. VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
  280. VMSTATE_END_OF_LIST(),
  281. },
  282. };
  283. static Property pxa2xx_gpio_properties[] = {
  284. DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
  285. DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
  286. DEFINE_PROP_END_OF_LIST(),
  287. };
  288. static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
  289. {
  290. DeviceClass *dc = DEVICE_CLASS(klass);
  291. dc->desc = "PXA2xx GPIO controller";
  292. device_class_set_props(dc, pxa2xx_gpio_properties);
  293. dc->vmsd = &vmstate_pxa2xx_gpio_regs;
  294. dc->realize = pxa2xx_gpio_realize;
  295. }
  296. static const TypeInfo pxa2xx_gpio_info = {
  297. .name = TYPE_PXA2XX_GPIO,
  298. .parent = TYPE_SYS_BUS_DEVICE,
  299. .instance_size = sizeof(PXA2xxGPIOInfo),
  300. .instance_init = pxa2xx_gpio_initfn,
  301. .class_init = pxa2xx_gpio_class_init,
  302. };
  303. static void pxa2xx_gpio_register_types(void)
  304. {
  305. type_register_static(&pxa2xx_gpio_info);
  306. }
  307. type_init(pxa2xx_gpio_register_types)