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hcd-ohci-pci.c 4.5 KB

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  1. /*
  2. * QEMU USB OHCI Emulation
  3. * Copyright (c) 2004 Gianni Tedesco
  4. * Copyright (c) 2006 CodeSourcery
  5. * Copyright (c) 2006 Openedhand Ltd.
  6. *
  7. * This library is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU Lesser General Public
  9. * License as published by the Free Software Foundation; either
  10. * version 2.1 of the License, or (at your option) any later version.
  11. *
  12. * This library is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * Lesser General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU Lesser General Public
  18. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include "qemu/osdep.h"
  21. #include "qapi/error.h"
  22. #include "qemu/timer.h"
  23. #include "hw/usb.h"
  24. #include "migration/vmstate.h"
  25. #include "hw/pci/pci.h"
  26. #include "hw/sysbus.h"
  27. #include "hw/qdev-dma.h"
  28. #include "hw/qdev-properties.h"
  29. #include "trace.h"
  30. #include "hcd-ohci.h"
  31. #define TYPE_PCI_OHCI "pci-ohci"
  32. #define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI)
  33. typedef struct {
  34. /*< private >*/
  35. PCIDevice parent_obj;
  36. /*< public >*/
  37. OHCIState state;
  38. char *masterbus;
  39. uint32_t num_ports;
  40. uint32_t firstport;
  41. } OHCIPCIState;
  42. /**
  43. * A typical PCI OHCI will additionally set PERR in its configspace to
  44. * signal that it got an error.
  45. */
  46. static void ohci_pci_die(struct OHCIState *ohci)
  47. {
  48. OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state);
  49. ohci_sysbus_die(ohci);
  50. pci_set_word(dev->parent_obj.config + PCI_STATUS,
  51. PCI_STATUS_DETECTED_PARITY);
  52. }
  53. static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp)
  54. {
  55. Error *err = NULL;
  56. OHCIPCIState *ohci = PCI_OHCI(dev);
  57. dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */
  58. dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
  59. usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0,
  60. ohci->masterbus, ohci->firstport,
  61. pci_get_address_space(dev), ohci_pci_die, &err);
  62. if (err) {
  63. error_propagate(errp, err);
  64. return;
  65. }
  66. ohci->state.irq = pci_allocate_irq(dev);
  67. pci_register_bar(dev, 0, 0, &ohci->state.mem);
  68. }
  69. static void usb_ohci_exit(PCIDevice *dev)
  70. {
  71. OHCIPCIState *ohci = PCI_OHCI(dev);
  72. OHCIState *s = &ohci->state;
  73. trace_usb_ohci_exit(s->name);
  74. ohci_bus_stop(s);
  75. if (s->async_td) {
  76. usb_cancel_packet(&s->usb_packet);
  77. s->async_td = 0;
  78. }
  79. ohci_stop_endpoints(s);
  80. if (!ohci->masterbus) {
  81. usb_bus_release(&s->bus);
  82. }
  83. timer_del(s->eof_timer);
  84. timer_free(s->eof_timer);
  85. }
  86. static void usb_ohci_reset_pci(DeviceState *d)
  87. {
  88. PCIDevice *dev = PCI_DEVICE(d);
  89. OHCIPCIState *ohci = PCI_OHCI(dev);
  90. OHCIState *s = &ohci->state;
  91. ohci_hard_reset(s);
  92. }
  93. static Property ohci_pci_properties[] = {
  94. DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
  95. DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
  96. DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
  97. DEFINE_PROP_END_OF_LIST(),
  98. };
  99. static const VMStateDescription vmstate_ohci = {
  100. .name = "ohci",
  101. .version_id = 1,
  102. .minimum_version_id = 1,
  103. .fields = (VMStateField[]) {
  104. VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState),
  105. VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState),
  106. VMSTATE_END_OF_LIST()
  107. }
  108. };
  109. static void ohci_pci_class_init(ObjectClass *klass, void *data)
  110. {
  111. DeviceClass *dc = DEVICE_CLASS(klass);
  112. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  113. k->realize = usb_ohci_realize_pci;
  114. k->exit = usb_ohci_exit;
  115. k->vendor_id = PCI_VENDOR_ID_APPLE;
  116. k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
  117. k->class_id = PCI_CLASS_SERIAL_USB;
  118. set_bit(DEVICE_CATEGORY_USB, dc->categories);
  119. dc->desc = "Apple USB Controller";
  120. dc->props = ohci_pci_properties;
  121. dc->hotpluggable = false;
  122. dc->vmsd = &vmstate_ohci;
  123. dc->reset = usb_ohci_reset_pci;
  124. }
  125. static const TypeInfo ohci_pci_info = {
  126. .name = TYPE_PCI_OHCI,
  127. .parent = TYPE_PCI_DEVICE,
  128. .instance_size = sizeof(OHCIPCIState),
  129. .class_init = ohci_pci_class_init,
  130. .interfaces = (InterfaceInfo[]) {
  131. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  132. { },
  133. },
  134. };
  135. static void ohci_pci_register_types(void)
  136. {
  137. type_register_static(&ohci_pci_info);
  138. }
  139. type_init(ohci_pci_register_types)