sun4m_iommu.c 14 KB

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  1. /*
  2. * QEMU Sun4m iommu emulation
  3. *
  4. * Copyright (c) 2003-2005 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "hw/irq.h"
  26. #include "hw/qdev-properties.h"
  27. #include "hw/sparc/sun4m_iommu.h"
  28. #include "hw/sysbus.h"
  29. #include "migration/vmstate.h"
  30. #include "qemu/module.h"
  31. #include "exec/address-spaces.h"
  32. #include "trace.h"
  33. /*
  34. * I/O MMU used by Sun4m systems
  35. *
  36. * Chipset docs:
  37. * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  38. * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  39. */
  40. #define IOMMU_CTRL (0x0000 >> 2)
  41. #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
  42. #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
  43. #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
  44. #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
  45. #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
  46. #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
  47. #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
  48. #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
  49. #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
  50. #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
  51. #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
  52. #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
  53. #define IOMMU_CTRL_MASK 0x0000001d
  54. #define IOMMU_BASE (0x0004 >> 2)
  55. #define IOMMU_BASE_MASK 0x07fffc00
  56. #define IOMMU_TLBFLUSH (0x0014 >> 2)
  57. #define IOMMU_TLBFLUSH_MASK 0xffffffff
  58. #define IOMMU_PGFLUSH (0x0018 >> 2)
  59. #define IOMMU_PGFLUSH_MASK 0xffffffff
  60. #define IOMMU_AFSR (0x1000 >> 2)
  61. #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
  62. #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
  63. transaction */
  64. #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
  65. 12.8 us. */
  66. #define IOMMU_AFSR_BE 0x10000000 /* Write access received error
  67. acknowledge */
  68. #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
  69. #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
  70. #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
  71. hardware */
  72. #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
  73. #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
  74. #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
  75. #define IOMMU_AFSR_MASK 0xff0fffff
  76. #define IOMMU_AFAR (0x1004 >> 2)
  77. #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
  78. #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
  79. #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
  80. #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
  81. #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
  82. #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
  83. #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
  84. #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
  85. #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
  86. #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
  87. #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
  88. #define IOMMU_AER_MASK 0x801f000f
  89. #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
  90. #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
  91. #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
  92. #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
  93. #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
  94. bypass enabled */
  95. #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
  96. #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
  97. #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
  98. produced by this device as pure
  99. physical. */
  100. #define IOMMU_SBCFG_MASK 0x00010003
  101. #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
  102. #define IOMMU_ARBEN_MASK 0x001f0000
  103. #define IOMMU_MID 0x00000008
  104. #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
  105. #define IOMMU_MASK_ID_MASK 0x00ffffff
  106. #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
  107. #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
  108. /* The format of an iopte in the page tables */
  109. #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
  110. #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
  111. Viking/MXCC) */
  112. #define IOPTE_WRITE 0x00000004 /* Writable */
  113. #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
  114. #define IOPTE_WAZ 0x00000001 /* Write as zeros */
  115. #define IOMMU_PAGE_SHIFT 12
  116. #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
  117. #define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1))
  118. static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
  119. unsigned size)
  120. {
  121. IOMMUState *s = opaque;
  122. hwaddr saddr;
  123. uint32_t ret;
  124. saddr = addr >> 2;
  125. switch (saddr) {
  126. default:
  127. ret = s->regs[saddr];
  128. break;
  129. case IOMMU_AFAR:
  130. case IOMMU_AFSR:
  131. ret = s->regs[saddr];
  132. qemu_irq_lower(s->irq);
  133. break;
  134. }
  135. trace_sun4m_iommu_mem_readl(saddr, ret);
  136. return ret;
  137. }
  138. static void iommu_mem_write(void *opaque, hwaddr addr,
  139. uint64_t val, unsigned size)
  140. {
  141. IOMMUState *s = opaque;
  142. hwaddr saddr;
  143. saddr = addr >> 2;
  144. trace_sun4m_iommu_mem_writel(saddr, val);
  145. switch (saddr) {
  146. case IOMMU_CTRL:
  147. switch (val & IOMMU_CTRL_RNGE) {
  148. case IOMMU_RNGE_16MB:
  149. s->iostart = 0xffffffffff000000ULL;
  150. break;
  151. case IOMMU_RNGE_32MB:
  152. s->iostart = 0xfffffffffe000000ULL;
  153. break;
  154. case IOMMU_RNGE_64MB:
  155. s->iostart = 0xfffffffffc000000ULL;
  156. break;
  157. case IOMMU_RNGE_128MB:
  158. s->iostart = 0xfffffffff8000000ULL;
  159. break;
  160. case IOMMU_RNGE_256MB:
  161. s->iostart = 0xfffffffff0000000ULL;
  162. break;
  163. case IOMMU_RNGE_512MB:
  164. s->iostart = 0xffffffffe0000000ULL;
  165. break;
  166. case IOMMU_RNGE_1GB:
  167. s->iostart = 0xffffffffc0000000ULL;
  168. break;
  169. default:
  170. case IOMMU_RNGE_2GB:
  171. s->iostart = 0xffffffff80000000ULL;
  172. break;
  173. }
  174. trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
  175. s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
  176. break;
  177. case IOMMU_BASE:
  178. s->regs[saddr] = val & IOMMU_BASE_MASK;
  179. break;
  180. case IOMMU_TLBFLUSH:
  181. trace_sun4m_iommu_mem_writel_tlbflush(val);
  182. s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
  183. break;
  184. case IOMMU_PGFLUSH:
  185. trace_sun4m_iommu_mem_writel_pgflush(val);
  186. s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
  187. break;
  188. case IOMMU_AFAR:
  189. s->regs[saddr] = val;
  190. qemu_irq_lower(s->irq);
  191. break;
  192. case IOMMU_AER:
  193. s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
  194. break;
  195. case IOMMU_AFSR:
  196. s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
  197. qemu_irq_lower(s->irq);
  198. break;
  199. case IOMMU_SBCFG0:
  200. case IOMMU_SBCFG1:
  201. case IOMMU_SBCFG2:
  202. case IOMMU_SBCFG3:
  203. s->regs[saddr] = val & IOMMU_SBCFG_MASK;
  204. break;
  205. case IOMMU_ARBEN:
  206. /* XXX implement SBus probing: fault when reading unmapped
  207. addresses, fault cause and address stored to MMU/IOMMU */
  208. s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
  209. break;
  210. case IOMMU_MASK_ID:
  211. s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
  212. break;
  213. default:
  214. s->regs[saddr] = val;
  215. break;
  216. }
  217. }
  218. static const MemoryRegionOps iommu_mem_ops = {
  219. .read = iommu_mem_read,
  220. .write = iommu_mem_write,
  221. .endianness = DEVICE_NATIVE_ENDIAN,
  222. .valid = {
  223. .min_access_size = 4,
  224. .max_access_size = 4,
  225. },
  226. };
  227. static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
  228. {
  229. uint32_t ret;
  230. hwaddr iopte;
  231. hwaddr pa = addr;
  232. iopte = s->regs[IOMMU_BASE] << 4;
  233. addr &= ~s->iostart;
  234. iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
  235. ret = address_space_ldl_be(&address_space_memory, iopte,
  236. MEMTXATTRS_UNSPECIFIED, NULL);
  237. trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
  238. return ret;
  239. }
  240. static hwaddr iommu_translate_pa(hwaddr addr,
  241. uint32_t pte)
  242. {
  243. hwaddr pa;
  244. pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
  245. trace_sun4m_iommu_translate_pa(addr, pa, pte);
  246. return pa;
  247. }
  248. static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
  249. int is_write)
  250. {
  251. trace_sun4m_iommu_bad_addr(addr);
  252. s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
  253. IOMMU_AFSR_FAV;
  254. if (!is_write) {
  255. s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
  256. }
  257. s->regs[IOMMU_AFAR] = addr;
  258. qemu_irq_raise(s->irq);
  259. }
  260. /* Called from RCU critical section */
  261. static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
  262. hwaddr addr,
  263. IOMMUAccessFlags flags,
  264. int iommu_idx)
  265. {
  266. IOMMUState *is = container_of(iommu, IOMMUState, iommu);
  267. hwaddr page, pa;
  268. int is_write = (flags & IOMMU_WO) ? 1 : 0;
  269. uint32_t pte;
  270. IOMMUTLBEntry ret = {
  271. .target_as = &address_space_memory,
  272. .iova = 0,
  273. .translated_addr = 0,
  274. .addr_mask = ~(hwaddr)0,
  275. .perm = IOMMU_NONE,
  276. };
  277. page = addr & IOMMU_PAGE_MASK;
  278. pte = iommu_page_get_flags(is, page);
  279. if (!(pte & IOPTE_VALID)) {
  280. iommu_bad_addr(is, page, is_write);
  281. return ret;
  282. }
  283. pa = iommu_translate_pa(addr, pte);
  284. if (is_write && !(pte & IOPTE_WRITE)) {
  285. iommu_bad_addr(is, page, is_write);
  286. return ret;
  287. }
  288. if (pte & IOPTE_WRITE) {
  289. ret.perm = IOMMU_RW;
  290. } else {
  291. ret.perm = IOMMU_RO;
  292. }
  293. ret.iova = page;
  294. ret.translated_addr = pa;
  295. ret.addr_mask = ~IOMMU_PAGE_MASK;
  296. return ret;
  297. }
  298. static const VMStateDescription vmstate_iommu = {
  299. .name = "iommu",
  300. .version_id = 2,
  301. .minimum_version_id = 2,
  302. .fields = (VMStateField[]) {
  303. VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
  304. VMSTATE_UINT64(iostart, IOMMUState),
  305. VMSTATE_END_OF_LIST()
  306. }
  307. };
  308. static void iommu_reset(DeviceState *d)
  309. {
  310. IOMMUState *s = SUN4M_IOMMU(d);
  311. memset(s->regs, 0, IOMMU_NREGS * 4);
  312. s->iostart = 0;
  313. s->regs[IOMMU_CTRL] = s->version;
  314. s->regs[IOMMU_ARBEN] = IOMMU_MID;
  315. s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
  316. s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
  317. s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
  318. }
  319. static void iommu_init(Object *obj)
  320. {
  321. IOMMUState *s = SUN4M_IOMMU(obj);
  322. SysBusDevice *dev = SYS_BUS_DEVICE(obj);
  323. memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
  324. TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev),
  325. "iommu-sun4m", UINT64_MAX);
  326. address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
  327. sysbus_init_irq(dev, &s->irq);
  328. memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
  329. IOMMU_NREGS * sizeof(uint32_t));
  330. sysbus_init_mmio(dev, &s->iomem);
  331. }
  332. static Property iommu_properties[] = {
  333. DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
  334. DEFINE_PROP_END_OF_LIST(),
  335. };
  336. static void iommu_class_init(ObjectClass *klass, void *data)
  337. {
  338. DeviceClass *dc = DEVICE_CLASS(klass);
  339. dc->reset = iommu_reset;
  340. dc->vmsd = &vmstate_iommu;
  341. dc->props = iommu_properties;
  342. }
  343. static const TypeInfo iommu_info = {
  344. .name = TYPE_SUN4M_IOMMU,
  345. .parent = TYPE_SYS_BUS_DEVICE,
  346. .instance_size = sizeof(IOMMUState),
  347. .instance_init = iommu_init,
  348. .class_init = iommu_class_init,
  349. };
  350. static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void *data)
  351. {
  352. IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
  353. imrc->translate = sun4m_translate_iommu;
  354. }
  355. static const TypeInfo sun4m_iommu_memory_region_info = {
  356. .parent = TYPE_IOMMU_MEMORY_REGION,
  357. .name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
  358. .class_init = sun4m_iommu_memory_region_class_init,
  359. };
  360. static void iommu_register_types(void)
  361. {
  362. type_register_static(&iommu_info);
  363. type_register_static(&sun4m_iommu_memory_region_info);
  364. }
  365. type_init(iommu_register_types)