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omap_mmc.c 16 KB

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  1. /*
  2. * OMAP on-chip MMC/SD host emulation.
  3. *
  4. * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
  5. *
  6. * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 or
  11. * (at your option) version 3 of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include "qemu/osdep.h"
  22. #include "qemu/log.h"
  23. #include "hw/irq.h"
  24. #include "hw/arm/omap.h"
  25. #include "hw/sd/sd.h"
  26. struct omap_mmc_s {
  27. qemu_irq irq;
  28. qemu_irq *dma;
  29. qemu_irq coverswitch;
  30. MemoryRegion iomem;
  31. omap_clk clk;
  32. SDState *card;
  33. uint16_t last_cmd;
  34. uint16_t sdio;
  35. uint16_t rsp[8];
  36. uint32_t arg;
  37. int lines;
  38. int dw;
  39. int mode;
  40. int enable;
  41. int be;
  42. int rev;
  43. uint16_t status;
  44. uint16_t mask;
  45. uint8_t cto;
  46. uint16_t dto;
  47. int clkdiv;
  48. uint16_t fifo[32];
  49. int fifo_start;
  50. int fifo_len;
  51. uint16_t blen;
  52. uint16_t blen_counter;
  53. uint16_t nblk;
  54. uint16_t nblk_counter;
  55. int tx_dma;
  56. int rx_dma;
  57. int af_level;
  58. int ae_level;
  59. int ddir;
  60. int transfer;
  61. int cdet_wakeup;
  62. int cdet_enable;
  63. int cdet_state;
  64. qemu_irq cdet;
  65. };
  66. static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
  67. {
  68. qemu_set_irq(s->irq, !!(s->status & s->mask));
  69. }
  70. static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
  71. {
  72. if (!host->transfer && !host->fifo_len) {
  73. host->status &= 0xf3ff;
  74. return;
  75. }
  76. if (host->fifo_len > host->af_level && host->ddir) {
  77. if (host->rx_dma) {
  78. host->status &= 0xfbff;
  79. qemu_irq_raise(host->dma[1]);
  80. } else
  81. host->status |= 0x0400;
  82. } else {
  83. host->status &= 0xfbff;
  84. qemu_irq_lower(host->dma[1]);
  85. }
  86. if (host->fifo_len < host->ae_level && !host->ddir) {
  87. if (host->tx_dma) {
  88. host->status &= 0xf7ff;
  89. qemu_irq_raise(host->dma[0]);
  90. } else
  91. host->status |= 0x0800;
  92. } else {
  93. qemu_irq_lower(host->dma[0]);
  94. host->status &= 0xf7ff;
  95. }
  96. }
  97. typedef enum {
  98. sd_nore = 0, /* no response */
  99. sd_r1, /* normal response command */
  100. sd_r2, /* CID, CSD registers */
  101. sd_r3, /* OCR register */
  102. sd_r6 = 6, /* Published RCA response */
  103. sd_r1b = -1,
  104. } sd_rsp_type_t;
  105. static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
  106. sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
  107. {
  108. uint32_t rspstatus, mask;
  109. int rsplen, timeout;
  110. SDRequest request;
  111. uint8_t response[16];
  112. if (init && cmd == 0) {
  113. host->status |= 0x0001;
  114. return;
  115. }
  116. if (resptype == sd_r1 && busy)
  117. resptype = sd_r1b;
  118. if (type == sd_adtc) {
  119. host->fifo_start = 0;
  120. host->fifo_len = 0;
  121. host->transfer = 1;
  122. host->ddir = dir;
  123. } else
  124. host->transfer = 0;
  125. timeout = 0;
  126. mask = 0;
  127. rspstatus = 0;
  128. request.cmd = cmd;
  129. request.arg = host->arg;
  130. request.crc = 0; /* FIXME */
  131. rsplen = sd_do_command(host->card, &request, response);
  132. /* TODO: validate CRCs */
  133. switch (resptype) {
  134. case sd_nore:
  135. rsplen = 0;
  136. break;
  137. case sd_r1:
  138. case sd_r1b:
  139. if (rsplen < 4) {
  140. timeout = 1;
  141. break;
  142. }
  143. rsplen = 4;
  144. mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
  145. ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
  146. LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
  147. CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
  148. CID_CSD_OVERWRITE;
  149. if (host->sdio & (1 << 13))
  150. mask |= AKE_SEQ_ERROR;
  151. rspstatus = ldl_be_p(response);
  152. break;
  153. case sd_r2:
  154. if (rsplen < 16) {
  155. timeout = 1;
  156. break;
  157. }
  158. rsplen = 16;
  159. break;
  160. case sd_r3:
  161. if (rsplen < 4) {
  162. timeout = 1;
  163. break;
  164. }
  165. rsplen = 4;
  166. rspstatus = ldl_be_p(response);
  167. if (rspstatus & 0x80000000)
  168. host->status &= 0xe000;
  169. else
  170. host->status |= 0x1000;
  171. break;
  172. case sd_r6:
  173. if (rsplen < 4) {
  174. timeout = 1;
  175. break;
  176. }
  177. rsplen = 4;
  178. mask = 0xe000 | AKE_SEQ_ERROR;
  179. rspstatus = (response[2] << 8) | (response[3] << 0);
  180. }
  181. if (rspstatus & mask)
  182. host->status |= 0x4000;
  183. else
  184. host->status &= 0xb000;
  185. if (rsplen)
  186. for (rsplen = 0; rsplen < 8; rsplen ++)
  187. host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
  188. (response[(rsplen << 1) | 0] << 8);
  189. if (timeout)
  190. host->status |= 0x0080;
  191. else if (cmd == 12)
  192. host->status |= 0x0005; /* Makes it more real */
  193. else
  194. host->status |= 0x0001;
  195. }
  196. static void omap_mmc_transfer(struct omap_mmc_s *host)
  197. {
  198. uint8_t value;
  199. if (!host->transfer)
  200. return;
  201. while (1) {
  202. if (host->ddir) {
  203. if (host->fifo_len > host->af_level)
  204. break;
  205. value = sd_read_data(host->card);
  206. host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
  207. if (-- host->blen_counter) {
  208. value = sd_read_data(host->card);
  209. host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
  210. value << 8;
  211. host->blen_counter --;
  212. }
  213. host->fifo_len ++;
  214. } else {
  215. if (!host->fifo_len)
  216. break;
  217. value = host->fifo[host->fifo_start] & 0xff;
  218. sd_write_data(host->card, value);
  219. if (-- host->blen_counter) {
  220. value = host->fifo[host->fifo_start] >> 8;
  221. sd_write_data(host->card, value);
  222. host->blen_counter --;
  223. }
  224. host->fifo_start ++;
  225. host->fifo_len --;
  226. host->fifo_start &= 31;
  227. }
  228. if (host->blen_counter == 0) {
  229. host->nblk_counter --;
  230. host->blen_counter = host->blen;
  231. if (host->nblk_counter == 0) {
  232. host->nblk_counter = host->nblk;
  233. host->transfer = 0;
  234. host->status |= 0x0008;
  235. break;
  236. }
  237. }
  238. }
  239. }
  240. static void omap_mmc_update(void *opaque)
  241. {
  242. struct omap_mmc_s *s = opaque;
  243. omap_mmc_transfer(s);
  244. omap_mmc_fifolevel_update(s);
  245. omap_mmc_interrupts_update(s);
  246. }
  247. static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
  248. {
  249. host->status = 0;
  250. host->fifo_len = 0;
  251. }
  252. void omap_mmc_reset(struct omap_mmc_s *host)
  253. {
  254. host->last_cmd = 0;
  255. memset(host->rsp, 0, sizeof(host->rsp));
  256. host->arg = 0;
  257. host->dw = 0;
  258. host->mode = 0;
  259. host->enable = 0;
  260. host->mask = 0;
  261. host->cto = 0;
  262. host->dto = 0;
  263. host->blen = 0;
  264. host->blen_counter = 0;
  265. host->nblk = 0;
  266. host->nblk_counter = 0;
  267. host->tx_dma = 0;
  268. host->rx_dma = 0;
  269. host->ae_level = 0x00;
  270. host->af_level = 0x1f;
  271. host->transfer = 0;
  272. host->cdet_wakeup = 0;
  273. host->cdet_enable = 0;
  274. qemu_set_irq(host->coverswitch, host->cdet_state);
  275. host->clkdiv = 0;
  276. omap_mmc_pseudo_reset(host);
  277. /* Since we're still using the legacy SD API the card is not plugged
  278. * into any bus, and we must reset it manually. When omap_mmc is
  279. * QOMified this must move into the QOM reset function.
  280. */
  281. device_reset(DEVICE(host->card));
  282. }
  283. static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
  284. unsigned size)
  285. {
  286. uint16_t i;
  287. struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
  288. if (size != 2) {
  289. return omap_badwidth_read16(opaque, offset);
  290. }
  291. switch (offset) {
  292. case 0x00: /* MMC_CMD */
  293. return s->last_cmd;
  294. case 0x04: /* MMC_ARGL */
  295. return s->arg & 0x0000ffff;
  296. case 0x08: /* MMC_ARGH */
  297. return s->arg >> 16;
  298. case 0x0c: /* MMC_CON */
  299. return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
  300. (s->be << 10) | s->clkdiv;
  301. case 0x10: /* MMC_STAT */
  302. return s->status;
  303. case 0x14: /* MMC_IE */
  304. return s->mask;
  305. case 0x18: /* MMC_CTO */
  306. return s->cto;
  307. case 0x1c: /* MMC_DTO */
  308. return s->dto;
  309. case 0x20: /* MMC_DATA */
  310. /* TODO: support 8-bit access */
  311. i = s->fifo[s->fifo_start];
  312. if (s->fifo_len == 0) {
  313. printf("MMC: FIFO underrun\n");
  314. return i;
  315. }
  316. s->fifo_start ++;
  317. s->fifo_len --;
  318. s->fifo_start &= 31;
  319. omap_mmc_transfer(s);
  320. omap_mmc_fifolevel_update(s);
  321. omap_mmc_interrupts_update(s);
  322. return i;
  323. case 0x24: /* MMC_BLEN */
  324. return s->blen_counter;
  325. case 0x28: /* MMC_NBLK */
  326. return s->nblk_counter;
  327. case 0x2c: /* MMC_BUF */
  328. return (s->rx_dma << 15) | (s->af_level << 8) |
  329. (s->tx_dma << 7) | s->ae_level;
  330. case 0x30: /* MMC_SPI */
  331. return 0x0000;
  332. case 0x34: /* MMC_SDIO */
  333. return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
  334. case 0x38: /* MMC_SYST */
  335. return 0x0000;
  336. case 0x3c: /* MMC_REV */
  337. return s->rev;
  338. case 0x40: /* MMC_RSP0 */
  339. case 0x44: /* MMC_RSP1 */
  340. case 0x48: /* MMC_RSP2 */
  341. case 0x4c: /* MMC_RSP3 */
  342. case 0x50: /* MMC_RSP4 */
  343. case 0x54: /* MMC_RSP5 */
  344. case 0x58: /* MMC_RSP6 */
  345. case 0x5c: /* MMC_RSP7 */
  346. return s->rsp[(offset - 0x40) >> 2];
  347. /* OMAP2-specific */
  348. case 0x60: /* MMC_IOSR */
  349. case 0x64: /* MMC_SYSC */
  350. return 0;
  351. case 0x68: /* MMC_SYSS */
  352. return 1; /* RSTD */
  353. }
  354. OMAP_BAD_REG(offset);
  355. return 0;
  356. }
  357. static void omap_mmc_write(void *opaque, hwaddr offset,
  358. uint64_t value, unsigned size)
  359. {
  360. int i;
  361. struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
  362. if (size != 2) {
  363. omap_badwidth_write16(opaque, offset, value);
  364. return;
  365. }
  366. switch (offset) {
  367. case 0x00: /* MMC_CMD */
  368. if (!s->enable)
  369. break;
  370. s->last_cmd = value;
  371. for (i = 0; i < 8; i ++)
  372. s->rsp[i] = 0x0000;
  373. omap_mmc_command(s, value & 63, (value >> 15) & 1,
  374. (sd_cmd_type_t) ((value >> 12) & 3),
  375. (value >> 11) & 1,
  376. (sd_rsp_type_t) ((value >> 8) & 7),
  377. (value >> 7) & 1);
  378. omap_mmc_update(s);
  379. break;
  380. case 0x04: /* MMC_ARGL */
  381. s->arg &= 0xffff0000;
  382. s->arg |= 0x0000ffff & value;
  383. break;
  384. case 0x08: /* MMC_ARGH */
  385. s->arg &= 0x0000ffff;
  386. s->arg |= value << 16;
  387. break;
  388. case 0x0c: /* MMC_CON */
  389. s->dw = (value >> 15) & 1;
  390. s->mode = (value >> 12) & 3;
  391. s->enable = (value >> 11) & 1;
  392. s->be = (value >> 10) & 1;
  393. s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
  394. if (s->mode != 0) {
  395. qemu_log_mask(LOG_UNIMP,
  396. "omap_mmc_wr: mode #%i unimplemented\n", s->mode);
  397. }
  398. if (s->be != 0) {
  399. qemu_log_mask(LOG_UNIMP,
  400. "omap_mmc_wr: Big Endian not implemented\n");
  401. }
  402. if (s->dw != 0 && s->lines < 4)
  403. printf("4-bit SD bus enabled\n");
  404. if (!s->enable)
  405. omap_mmc_pseudo_reset(s);
  406. break;
  407. case 0x10: /* MMC_STAT */
  408. s->status &= ~value;
  409. omap_mmc_interrupts_update(s);
  410. break;
  411. case 0x14: /* MMC_IE */
  412. s->mask = value & 0x7fff;
  413. omap_mmc_interrupts_update(s);
  414. break;
  415. case 0x18: /* MMC_CTO */
  416. s->cto = value & 0xff;
  417. if (s->cto > 0xfd && s->rev <= 1)
  418. printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
  419. break;
  420. case 0x1c: /* MMC_DTO */
  421. s->dto = value & 0xffff;
  422. break;
  423. case 0x20: /* MMC_DATA */
  424. /* TODO: support 8-bit access */
  425. if (s->fifo_len == 32)
  426. break;
  427. s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
  428. s->fifo_len ++;
  429. omap_mmc_transfer(s);
  430. omap_mmc_fifolevel_update(s);
  431. omap_mmc_interrupts_update(s);
  432. break;
  433. case 0x24: /* MMC_BLEN */
  434. s->blen = (value & 0x07ff) + 1;
  435. s->blen_counter = s->blen;
  436. break;
  437. case 0x28: /* MMC_NBLK */
  438. s->nblk = (value & 0x07ff) + 1;
  439. s->nblk_counter = s->nblk;
  440. s->blen_counter = s->blen;
  441. break;
  442. case 0x2c: /* MMC_BUF */
  443. s->rx_dma = (value >> 15) & 1;
  444. s->af_level = (value >> 8) & 0x1f;
  445. s->tx_dma = (value >> 7) & 1;
  446. s->ae_level = value & 0x1f;
  447. if (s->rx_dma)
  448. s->status &= 0xfbff;
  449. if (s->tx_dma)
  450. s->status &= 0xf7ff;
  451. omap_mmc_fifolevel_update(s);
  452. omap_mmc_interrupts_update(s);
  453. break;
  454. /* SPI, SDIO and TEST modes unimplemented */
  455. case 0x30: /* MMC_SPI (OMAP1 only) */
  456. break;
  457. case 0x34: /* MMC_SDIO */
  458. s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
  459. s->cdet_wakeup = (value >> 9) & 1;
  460. s->cdet_enable = (value >> 2) & 1;
  461. break;
  462. case 0x38: /* MMC_SYST */
  463. break;
  464. case 0x3c: /* MMC_REV */
  465. case 0x40: /* MMC_RSP0 */
  466. case 0x44: /* MMC_RSP1 */
  467. case 0x48: /* MMC_RSP2 */
  468. case 0x4c: /* MMC_RSP3 */
  469. case 0x50: /* MMC_RSP4 */
  470. case 0x54: /* MMC_RSP5 */
  471. case 0x58: /* MMC_RSP6 */
  472. case 0x5c: /* MMC_RSP7 */
  473. OMAP_RO_REG(offset);
  474. break;
  475. /* OMAP2-specific */
  476. case 0x60: /* MMC_IOSR */
  477. if (value & 0xf)
  478. printf("MMC: SDIO bits used!\n");
  479. break;
  480. case 0x64: /* MMC_SYSC */
  481. if (value & (1 << 2)) /* SRTS */
  482. omap_mmc_reset(s);
  483. break;
  484. case 0x68: /* MMC_SYSS */
  485. OMAP_RO_REG(offset);
  486. break;
  487. default:
  488. OMAP_BAD_REG(offset);
  489. }
  490. }
  491. static const MemoryRegionOps omap_mmc_ops = {
  492. .read = omap_mmc_read,
  493. .write = omap_mmc_write,
  494. .endianness = DEVICE_NATIVE_ENDIAN,
  495. };
  496. static void omap_mmc_cover_cb(void *opaque, int line, int level)
  497. {
  498. struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
  499. if (!host->cdet_state && level) {
  500. host->status |= 0x0002;
  501. omap_mmc_interrupts_update(host);
  502. if (host->cdet_wakeup) {
  503. /* TODO: Assert wake-up */
  504. }
  505. }
  506. if (host->cdet_state != level) {
  507. qemu_set_irq(host->coverswitch, level);
  508. host->cdet_state = level;
  509. }
  510. }
  511. struct omap_mmc_s *omap_mmc_init(hwaddr base,
  512. MemoryRegion *sysmem,
  513. BlockBackend *blk,
  514. qemu_irq irq, qemu_irq dma[], omap_clk clk)
  515. {
  516. struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
  517. s->irq = irq;
  518. s->dma = dma;
  519. s->clk = clk;
  520. s->lines = 1; /* TODO: needs to be settable per-board */
  521. s->rev = 1;
  522. memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
  523. memory_region_add_subregion(sysmem, base, &s->iomem);
  524. /* Instantiate the storage */
  525. s->card = sd_init(blk, false);
  526. if (s->card == NULL) {
  527. exit(1);
  528. }
  529. omap_mmc_reset(s);
  530. return s;
  531. }
  532. struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
  533. BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
  534. omap_clk fclk, omap_clk iclk)
  535. {
  536. struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
  537. s->irq = irq;
  538. s->dma = dma;
  539. s->clk = fclk;
  540. s->lines = 4;
  541. s->rev = 2;
  542. memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
  543. omap_l4_region_size(ta, 0));
  544. omap_l4_attach(ta, 0, &s->iomem);
  545. /* Instantiate the storage */
  546. s->card = sd_init(blk, false);
  547. if (s->card == NULL) {
  548. exit(1);
  549. }
  550. s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
  551. sd_set_cb(s->card, NULL, s->cdet);
  552. omap_mmc_reset(s);
  553. return s;
  554. }
  555. void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
  556. {
  557. if (s->cdet) {
  558. sd_set_cb(s->card, ro, s->cdet);
  559. s->coverswitch = cover;
  560. qemu_set_irq(cover, s->cdet_state);
  561. } else
  562. sd_set_cb(s->card, ro, cover);
  563. }
  564. void omap_mmc_enable(struct omap_mmc_s *s, int enable)
  565. {
  566. sd_enable(s->card, enable);
  567. }