twl92230.c 25 KB

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  1. /*
  2. * TI TWL92230C energy-management companion device for the OMAP24xx.
  3. * Aka. Menelaus (N4200 MENELAUS1_V2.2)
  4. *
  5. * Copyright (C) 2008 Nokia Corporation
  6. * Written by Andrzej Zaborowski <andrew@openedhand.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 or
  11. * (at your option) version 3 of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include "qemu/osdep.h"
  22. #include "qemu-common.h"
  23. #include "qemu/timer.h"
  24. #include "hw/i2c/i2c.h"
  25. #include "hw/irq.h"
  26. #include "migration/qemu-file-types.h"
  27. #include "migration/vmstate.h"
  28. #include "sysemu/sysemu.h"
  29. #include "ui/console.h"
  30. #include "qemu/bcd.h"
  31. #include "qemu/module.h"
  32. #define VERBOSE 1
  33. #define TYPE_TWL92230 "twl92230"
  34. #define TWL92230(obj) OBJECT_CHECK(MenelausState, (obj), TYPE_TWL92230)
  35. typedef struct MenelausState {
  36. I2CSlave parent_obj;
  37. int firstbyte;
  38. uint8_t reg;
  39. uint8_t vcore[5];
  40. uint8_t dcdc[3];
  41. uint8_t ldo[8];
  42. uint8_t sleep[2];
  43. uint8_t osc;
  44. uint8_t detect;
  45. uint16_t mask;
  46. uint16_t status;
  47. uint8_t dir;
  48. uint8_t inputs;
  49. uint8_t outputs;
  50. uint8_t bbsms;
  51. uint8_t pull[4];
  52. uint8_t mmc_ctrl[3];
  53. uint8_t mmc_debounce;
  54. struct {
  55. uint8_t ctrl;
  56. uint16_t comp;
  57. QEMUTimer *hz_tm;
  58. int64_t next;
  59. struct tm tm;
  60. struct tm new;
  61. struct tm alm;
  62. int sec_offset;
  63. int alm_sec;
  64. int next_comp;
  65. } rtc;
  66. uint16_t rtc_next_vmstate;
  67. qemu_irq out[4];
  68. uint8_t pwrbtn_state;
  69. } MenelausState;
  70. static inline void menelaus_update(MenelausState *s)
  71. {
  72. qemu_set_irq(s->out[3], s->status & ~s->mask);
  73. }
  74. static inline void menelaus_rtc_start(MenelausState *s)
  75. {
  76. s->rtc.next += qemu_clock_get_ms(rtc_clock);
  77. timer_mod(s->rtc.hz_tm, s->rtc.next);
  78. }
  79. static inline void menelaus_rtc_stop(MenelausState *s)
  80. {
  81. timer_del(s->rtc.hz_tm);
  82. s->rtc.next -= qemu_clock_get_ms(rtc_clock);
  83. if (s->rtc.next < 1)
  84. s->rtc.next = 1;
  85. }
  86. static void menelaus_rtc_update(MenelausState *s)
  87. {
  88. qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
  89. }
  90. static void menelaus_alm_update(MenelausState *s)
  91. {
  92. if ((s->rtc.ctrl & 3) == 3)
  93. s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
  94. }
  95. static void menelaus_rtc_hz(void *opaque)
  96. {
  97. MenelausState *s = (MenelausState *) opaque;
  98. s->rtc.next_comp --;
  99. s->rtc.alm_sec --;
  100. s->rtc.next += 1000;
  101. timer_mod(s->rtc.hz_tm, s->rtc.next);
  102. if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
  103. menelaus_rtc_update(s);
  104. if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
  105. s->status |= 1 << 8; /* RTCTMR */
  106. else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
  107. s->status |= 1 << 8; /* RTCTMR */
  108. else if (!s->rtc.tm.tm_hour)
  109. s->status |= 1 << 8; /* RTCTMR */
  110. } else
  111. s->status |= 1 << 8; /* RTCTMR */
  112. if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
  113. if (s->rtc.alm_sec == 0)
  114. s->status |= 1 << 9; /* RTCALM */
  115. /* TODO: wake-up */
  116. }
  117. if (s->rtc.next_comp <= 0) {
  118. s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
  119. s->rtc.next_comp = 3600;
  120. }
  121. menelaus_update(s);
  122. }
  123. static void menelaus_reset(I2CSlave *i2c)
  124. {
  125. MenelausState *s = TWL92230(i2c);
  126. s->reg = 0x00;
  127. s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
  128. s->vcore[1] = 0x05;
  129. s->vcore[2] = 0x02;
  130. s->vcore[3] = 0x0c;
  131. s->vcore[4] = 0x03;
  132. s->dcdc[0] = 0x33; /* Depends on wiring */
  133. s->dcdc[1] = 0x03;
  134. s->dcdc[2] = 0x00;
  135. s->ldo[0] = 0x95;
  136. s->ldo[1] = 0x7e;
  137. s->ldo[2] = 0x00;
  138. s->ldo[3] = 0x00; /* Depends on wiring */
  139. s->ldo[4] = 0x03; /* Depends on wiring */
  140. s->ldo[5] = 0x00;
  141. s->ldo[6] = 0x00;
  142. s->ldo[7] = 0x00;
  143. s->sleep[0] = 0x00;
  144. s->sleep[1] = 0x00;
  145. s->osc = 0x01;
  146. s->detect = 0x09;
  147. s->mask = 0x0fff;
  148. s->status = 0;
  149. s->dir = 0x07;
  150. s->outputs = 0x00;
  151. s->bbsms = 0x00;
  152. s->pull[0] = 0x00;
  153. s->pull[1] = 0x00;
  154. s->pull[2] = 0x00;
  155. s->pull[3] = 0x00;
  156. s->mmc_ctrl[0] = 0x03;
  157. s->mmc_ctrl[1] = 0xc0;
  158. s->mmc_ctrl[2] = 0x00;
  159. s->mmc_debounce = 0x05;
  160. if (s->rtc.ctrl & 1)
  161. menelaus_rtc_stop(s);
  162. s->rtc.ctrl = 0x00;
  163. s->rtc.comp = 0x0000;
  164. s->rtc.next = 1000;
  165. s->rtc.sec_offset = 0;
  166. s->rtc.next_comp = 1800;
  167. s->rtc.alm_sec = 1800;
  168. s->rtc.alm.tm_sec = 0x00;
  169. s->rtc.alm.tm_min = 0x00;
  170. s->rtc.alm.tm_hour = 0x00;
  171. s->rtc.alm.tm_mday = 0x01;
  172. s->rtc.alm.tm_mon = 0x00;
  173. s->rtc.alm.tm_year = 2004;
  174. menelaus_update(s);
  175. }
  176. static void menelaus_gpio_set(void *opaque, int line, int level)
  177. {
  178. MenelausState *s = (MenelausState *) opaque;
  179. if (line < 3) {
  180. /* No interrupt generated */
  181. s->inputs &= ~(1 << line);
  182. s->inputs |= level << line;
  183. return;
  184. }
  185. if (!s->pwrbtn_state && level) {
  186. s->status |= 1 << 11; /* PSHBTN */
  187. menelaus_update(s);
  188. }
  189. s->pwrbtn_state = level;
  190. }
  191. #define MENELAUS_REV 0x01
  192. #define MENELAUS_VCORE_CTRL1 0x02
  193. #define MENELAUS_VCORE_CTRL2 0x03
  194. #define MENELAUS_VCORE_CTRL3 0x04
  195. #define MENELAUS_VCORE_CTRL4 0x05
  196. #define MENELAUS_VCORE_CTRL5 0x06
  197. #define MENELAUS_DCDC_CTRL1 0x07
  198. #define MENELAUS_DCDC_CTRL2 0x08
  199. #define MENELAUS_DCDC_CTRL3 0x09
  200. #define MENELAUS_LDO_CTRL1 0x0a
  201. #define MENELAUS_LDO_CTRL2 0x0b
  202. #define MENELAUS_LDO_CTRL3 0x0c
  203. #define MENELAUS_LDO_CTRL4 0x0d
  204. #define MENELAUS_LDO_CTRL5 0x0e
  205. #define MENELAUS_LDO_CTRL6 0x0f
  206. #define MENELAUS_LDO_CTRL7 0x10
  207. #define MENELAUS_LDO_CTRL8 0x11
  208. #define MENELAUS_SLEEP_CTRL1 0x12
  209. #define MENELAUS_SLEEP_CTRL2 0x13
  210. #define MENELAUS_DEVICE_OFF 0x14
  211. #define MENELAUS_OSC_CTRL 0x15
  212. #define MENELAUS_DETECT_CTRL 0x16
  213. #define MENELAUS_INT_MASK1 0x17
  214. #define MENELAUS_INT_MASK2 0x18
  215. #define MENELAUS_INT_STATUS1 0x19
  216. #define MENELAUS_INT_STATUS2 0x1a
  217. #define MENELAUS_INT_ACK1 0x1b
  218. #define MENELAUS_INT_ACK2 0x1c
  219. #define MENELAUS_GPIO_CTRL 0x1d
  220. #define MENELAUS_GPIO_IN 0x1e
  221. #define MENELAUS_GPIO_OUT 0x1f
  222. #define MENELAUS_BBSMS 0x20
  223. #define MENELAUS_RTC_CTRL 0x21
  224. #define MENELAUS_RTC_UPDATE 0x22
  225. #define MENELAUS_RTC_SEC 0x23
  226. #define MENELAUS_RTC_MIN 0x24
  227. #define MENELAUS_RTC_HR 0x25
  228. #define MENELAUS_RTC_DAY 0x26
  229. #define MENELAUS_RTC_MON 0x27
  230. #define MENELAUS_RTC_YR 0x28
  231. #define MENELAUS_RTC_WKDAY 0x29
  232. #define MENELAUS_RTC_AL_SEC 0x2a
  233. #define MENELAUS_RTC_AL_MIN 0x2b
  234. #define MENELAUS_RTC_AL_HR 0x2c
  235. #define MENELAUS_RTC_AL_DAY 0x2d
  236. #define MENELAUS_RTC_AL_MON 0x2e
  237. #define MENELAUS_RTC_AL_YR 0x2f
  238. #define MENELAUS_RTC_COMP_MSB 0x30
  239. #define MENELAUS_RTC_COMP_LSB 0x31
  240. #define MENELAUS_S1_PULL_EN 0x32
  241. #define MENELAUS_S1_PULL_DIR 0x33
  242. #define MENELAUS_S2_PULL_EN 0x34
  243. #define MENELAUS_S2_PULL_DIR 0x35
  244. #define MENELAUS_MCT_CTRL1 0x36
  245. #define MENELAUS_MCT_CTRL2 0x37
  246. #define MENELAUS_MCT_CTRL3 0x38
  247. #define MENELAUS_MCT_PIN_ST 0x39
  248. #define MENELAUS_DEBOUNCE1 0x3a
  249. static uint8_t menelaus_read(void *opaque, uint8_t addr)
  250. {
  251. MenelausState *s = (MenelausState *) opaque;
  252. int reg = 0;
  253. switch (addr) {
  254. case MENELAUS_REV:
  255. return 0x22;
  256. case MENELAUS_VCORE_CTRL5: reg ++;
  257. case MENELAUS_VCORE_CTRL4: reg ++;
  258. case MENELAUS_VCORE_CTRL3: reg ++;
  259. case MENELAUS_VCORE_CTRL2: reg ++;
  260. case MENELAUS_VCORE_CTRL1:
  261. return s->vcore[reg];
  262. case MENELAUS_DCDC_CTRL3: reg ++;
  263. case MENELAUS_DCDC_CTRL2: reg ++;
  264. case MENELAUS_DCDC_CTRL1:
  265. return s->dcdc[reg];
  266. case MENELAUS_LDO_CTRL8: reg ++;
  267. case MENELAUS_LDO_CTRL7: reg ++;
  268. case MENELAUS_LDO_CTRL6: reg ++;
  269. case MENELAUS_LDO_CTRL5: reg ++;
  270. case MENELAUS_LDO_CTRL4: reg ++;
  271. case MENELAUS_LDO_CTRL3: reg ++;
  272. case MENELAUS_LDO_CTRL2: reg ++;
  273. case MENELAUS_LDO_CTRL1:
  274. return s->ldo[reg];
  275. case MENELAUS_SLEEP_CTRL2: reg ++;
  276. case MENELAUS_SLEEP_CTRL1:
  277. return s->sleep[reg];
  278. case MENELAUS_DEVICE_OFF:
  279. return 0;
  280. case MENELAUS_OSC_CTRL:
  281. return s->osc | (1 << 7); /* CLK32K_GOOD */
  282. case MENELAUS_DETECT_CTRL:
  283. return s->detect;
  284. case MENELAUS_INT_MASK1:
  285. return (s->mask >> 0) & 0xff;
  286. case MENELAUS_INT_MASK2:
  287. return (s->mask >> 8) & 0xff;
  288. case MENELAUS_INT_STATUS1:
  289. return (s->status >> 0) & 0xff;
  290. case MENELAUS_INT_STATUS2:
  291. return (s->status >> 8) & 0xff;
  292. case MENELAUS_INT_ACK1:
  293. case MENELAUS_INT_ACK2:
  294. return 0;
  295. case MENELAUS_GPIO_CTRL:
  296. return s->dir;
  297. case MENELAUS_GPIO_IN:
  298. return s->inputs | (~s->dir & s->outputs);
  299. case MENELAUS_GPIO_OUT:
  300. return s->outputs;
  301. case MENELAUS_BBSMS:
  302. return s->bbsms;
  303. case MENELAUS_RTC_CTRL:
  304. return s->rtc.ctrl;
  305. case MENELAUS_RTC_UPDATE:
  306. return 0x00;
  307. case MENELAUS_RTC_SEC:
  308. menelaus_rtc_update(s);
  309. return to_bcd(s->rtc.tm.tm_sec);
  310. case MENELAUS_RTC_MIN:
  311. menelaus_rtc_update(s);
  312. return to_bcd(s->rtc.tm.tm_min);
  313. case MENELAUS_RTC_HR:
  314. menelaus_rtc_update(s);
  315. if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
  316. return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
  317. (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
  318. else
  319. return to_bcd(s->rtc.tm.tm_hour);
  320. case MENELAUS_RTC_DAY:
  321. menelaus_rtc_update(s);
  322. return to_bcd(s->rtc.tm.tm_mday);
  323. case MENELAUS_RTC_MON:
  324. menelaus_rtc_update(s);
  325. return to_bcd(s->rtc.tm.tm_mon + 1);
  326. case MENELAUS_RTC_YR:
  327. menelaus_rtc_update(s);
  328. return to_bcd(s->rtc.tm.tm_year - 2000);
  329. case MENELAUS_RTC_WKDAY:
  330. menelaus_rtc_update(s);
  331. return to_bcd(s->rtc.tm.tm_wday);
  332. case MENELAUS_RTC_AL_SEC:
  333. return to_bcd(s->rtc.alm.tm_sec);
  334. case MENELAUS_RTC_AL_MIN:
  335. return to_bcd(s->rtc.alm.tm_min);
  336. case MENELAUS_RTC_AL_HR:
  337. if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
  338. return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
  339. (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
  340. else
  341. return to_bcd(s->rtc.alm.tm_hour);
  342. case MENELAUS_RTC_AL_DAY:
  343. return to_bcd(s->rtc.alm.tm_mday);
  344. case MENELAUS_RTC_AL_MON:
  345. return to_bcd(s->rtc.alm.tm_mon + 1);
  346. case MENELAUS_RTC_AL_YR:
  347. return to_bcd(s->rtc.alm.tm_year - 2000);
  348. case MENELAUS_RTC_COMP_MSB:
  349. return (s->rtc.comp >> 8) & 0xff;
  350. case MENELAUS_RTC_COMP_LSB:
  351. return (s->rtc.comp >> 0) & 0xff;
  352. case MENELAUS_S1_PULL_EN:
  353. return s->pull[0];
  354. case MENELAUS_S1_PULL_DIR:
  355. return s->pull[1];
  356. case MENELAUS_S2_PULL_EN:
  357. return s->pull[2];
  358. case MENELAUS_S2_PULL_DIR:
  359. return s->pull[3];
  360. case MENELAUS_MCT_CTRL3: reg ++;
  361. case MENELAUS_MCT_CTRL2: reg ++;
  362. case MENELAUS_MCT_CTRL1:
  363. return s->mmc_ctrl[reg];
  364. case MENELAUS_MCT_PIN_ST:
  365. /* TODO: return the real Card Detect */
  366. return 0;
  367. case MENELAUS_DEBOUNCE1:
  368. return s->mmc_debounce;
  369. default:
  370. #ifdef VERBOSE
  371. printf("%s: unknown register %02x\n", __func__, addr);
  372. #endif
  373. break;
  374. }
  375. return 0;
  376. }
  377. static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
  378. {
  379. MenelausState *s = (MenelausState *) opaque;
  380. int line;
  381. int reg = 0;
  382. struct tm tm;
  383. switch (addr) {
  384. case MENELAUS_VCORE_CTRL1:
  385. s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
  386. break;
  387. case MENELAUS_VCORE_CTRL2:
  388. s->vcore[1] = value;
  389. break;
  390. case MENELAUS_VCORE_CTRL3:
  391. s->vcore[2] = MIN(value & 0x1f, 0x12);
  392. break;
  393. case MENELAUS_VCORE_CTRL4:
  394. s->vcore[3] = MIN(value & 0x1f, 0x12);
  395. break;
  396. case MENELAUS_VCORE_CTRL5:
  397. s->vcore[4] = value & 3;
  398. /* XXX
  399. * auto set to 3 on M_Active, nRESWARM
  400. * auto set to 0 on M_WaitOn, M_Backup
  401. */
  402. break;
  403. case MENELAUS_DCDC_CTRL1:
  404. s->dcdc[0] = value & 0x3f;
  405. break;
  406. case MENELAUS_DCDC_CTRL2:
  407. s->dcdc[1] = value & 0x07;
  408. /* XXX
  409. * auto set to 3 on M_Active, nRESWARM
  410. * auto set to 0 on M_WaitOn, M_Backup
  411. */
  412. break;
  413. case MENELAUS_DCDC_CTRL3:
  414. s->dcdc[2] = value & 0x07;
  415. break;
  416. case MENELAUS_LDO_CTRL1:
  417. s->ldo[0] = value;
  418. break;
  419. case MENELAUS_LDO_CTRL2:
  420. s->ldo[1] = value & 0x7f;
  421. /* XXX
  422. * auto set to 0x7e on M_WaitOn, M_Backup
  423. */
  424. break;
  425. case MENELAUS_LDO_CTRL3:
  426. s->ldo[2] = value & 3;
  427. /* XXX
  428. * auto set to 3 on M_Active, nRESWARM
  429. * auto set to 0 on M_WaitOn, M_Backup
  430. */
  431. break;
  432. case MENELAUS_LDO_CTRL4:
  433. s->ldo[3] = value & 3;
  434. /* XXX
  435. * auto set to 3 on M_Active, nRESWARM
  436. * auto set to 0 on M_WaitOn, M_Backup
  437. */
  438. break;
  439. case MENELAUS_LDO_CTRL5:
  440. s->ldo[4] = value & 3;
  441. /* XXX
  442. * auto set to 3 on M_Active, nRESWARM
  443. * auto set to 0 on M_WaitOn, M_Backup
  444. */
  445. break;
  446. case MENELAUS_LDO_CTRL6:
  447. s->ldo[5] = value & 3;
  448. break;
  449. case MENELAUS_LDO_CTRL7:
  450. s->ldo[6] = value & 3;
  451. break;
  452. case MENELAUS_LDO_CTRL8:
  453. s->ldo[7] = value & 3;
  454. break;
  455. case MENELAUS_SLEEP_CTRL2: reg ++;
  456. case MENELAUS_SLEEP_CTRL1:
  457. s->sleep[reg] = value;
  458. break;
  459. case MENELAUS_DEVICE_OFF:
  460. if (value & 1) {
  461. menelaus_reset(I2C_SLAVE(s));
  462. }
  463. break;
  464. case MENELAUS_OSC_CTRL:
  465. s->osc = value & 7;
  466. break;
  467. case MENELAUS_DETECT_CTRL:
  468. s->detect = value & 0x7f;
  469. break;
  470. case MENELAUS_INT_MASK1:
  471. s->mask &= 0xf00;
  472. s->mask |= value << 0;
  473. menelaus_update(s);
  474. break;
  475. case MENELAUS_INT_MASK2:
  476. s->mask &= 0x0ff;
  477. s->mask |= value << 8;
  478. menelaus_update(s);
  479. break;
  480. case MENELAUS_INT_ACK1:
  481. s->status &= ~(((uint16_t) value) << 0);
  482. menelaus_update(s);
  483. break;
  484. case MENELAUS_INT_ACK2:
  485. s->status &= ~(((uint16_t) value) << 8);
  486. menelaus_update(s);
  487. break;
  488. case MENELAUS_GPIO_CTRL:
  489. for (line = 0; line < 3; line ++) {
  490. if (((s->dir ^ value) >> line) & 1) {
  491. qemu_set_irq(s->out[line],
  492. ((s->outputs & ~s->dir) >> line) & 1);
  493. }
  494. }
  495. s->dir = value & 0x67;
  496. break;
  497. case MENELAUS_GPIO_OUT:
  498. for (line = 0; line < 3; line ++) {
  499. if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
  500. qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
  501. }
  502. }
  503. s->outputs = value & 0x07;
  504. break;
  505. case MENELAUS_BBSMS:
  506. s->bbsms = 0x0d;
  507. break;
  508. case MENELAUS_RTC_CTRL:
  509. if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
  510. if (value & 1)
  511. menelaus_rtc_start(s);
  512. else
  513. menelaus_rtc_stop(s);
  514. }
  515. s->rtc.ctrl = value & 0x1f;
  516. menelaus_alm_update(s);
  517. break;
  518. case MENELAUS_RTC_UPDATE:
  519. menelaus_rtc_update(s);
  520. memcpy(&tm, &s->rtc.tm, sizeof(tm));
  521. switch (value & 0xf) {
  522. case 0:
  523. break;
  524. case 1:
  525. tm.tm_sec = s->rtc.new.tm_sec;
  526. break;
  527. case 2:
  528. tm.tm_min = s->rtc.new.tm_min;
  529. break;
  530. case 3:
  531. if (s->rtc.new.tm_hour > 23)
  532. goto rtc_badness;
  533. tm.tm_hour = s->rtc.new.tm_hour;
  534. break;
  535. case 4:
  536. if (s->rtc.new.tm_mday < 1)
  537. goto rtc_badness;
  538. /* TODO check range */
  539. tm.tm_mday = s->rtc.new.tm_mday;
  540. break;
  541. case 5:
  542. if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
  543. goto rtc_badness;
  544. tm.tm_mon = s->rtc.new.tm_mon;
  545. break;
  546. case 6:
  547. tm.tm_year = s->rtc.new.tm_year;
  548. break;
  549. case 7:
  550. /* TODO set .tm_mday instead */
  551. tm.tm_wday = s->rtc.new.tm_wday;
  552. break;
  553. case 8:
  554. if (s->rtc.new.tm_hour > 23)
  555. goto rtc_badness;
  556. if (s->rtc.new.tm_mday < 1)
  557. goto rtc_badness;
  558. if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
  559. goto rtc_badness;
  560. tm.tm_sec = s->rtc.new.tm_sec;
  561. tm.tm_min = s->rtc.new.tm_min;
  562. tm.tm_hour = s->rtc.new.tm_hour;
  563. tm.tm_mday = s->rtc.new.tm_mday;
  564. tm.tm_mon = s->rtc.new.tm_mon;
  565. tm.tm_year = s->rtc.new.tm_year;
  566. break;
  567. rtc_badness:
  568. default:
  569. fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
  570. __func__, value);
  571. s->status |= 1 << 10; /* RTCERR */
  572. menelaus_update(s);
  573. }
  574. s->rtc.sec_offset = qemu_timedate_diff(&tm);
  575. break;
  576. case MENELAUS_RTC_SEC:
  577. s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
  578. break;
  579. case MENELAUS_RTC_MIN:
  580. s->rtc.tm.tm_min = from_bcd(value & 0x7f);
  581. break;
  582. case MENELAUS_RTC_HR:
  583. s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
  584. MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
  585. from_bcd(value & 0x3f);
  586. break;
  587. case MENELAUS_RTC_DAY:
  588. s->rtc.tm.tm_mday = from_bcd(value);
  589. break;
  590. case MENELAUS_RTC_MON:
  591. s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
  592. break;
  593. case MENELAUS_RTC_YR:
  594. s->rtc.tm.tm_year = 2000 + from_bcd(value);
  595. break;
  596. case MENELAUS_RTC_WKDAY:
  597. s->rtc.tm.tm_mday = from_bcd(value);
  598. break;
  599. case MENELAUS_RTC_AL_SEC:
  600. s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
  601. menelaus_alm_update(s);
  602. break;
  603. case MENELAUS_RTC_AL_MIN:
  604. s->rtc.alm.tm_min = from_bcd(value & 0x7f);
  605. menelaus_alm_update(s);
  606. break;
  607. case MENELAUS_RTC_AL_HR:
  608. s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
  609. MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
  610. from_bcd(value & 0x3f);
  611. menelaus_alm_update(s);
  612. break;
  613. case MENELAUS_RTC_AL_DAY:
  614. s->rtc.alm.tm_mday = from_bcd(value);
  615. menelaus_alm_update(s);
  616. break;
  617. case MENELAUS_RTC_AL_MON:
  618. s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
  619. menelaus_alm_update(s);
  620. break;
  621. case MENELAUS_RTC_AL_YR:
  622. s->rtc.alm.tm_year = 2000 + from_bcd(value);
  623. menelaus_alm_update(s);
  624. break;
  625. case MENELAUS_RTC_COMP_MSB:
  626. s->rtc.comp &= 0xff;
  627. s->rtc.comp |= value << 8;
  628. break;
  629. case MENELAUS_RTC_COMP_LSB:
  630. s->rtc.comp &= 0xff << 8;
  631. s->rtc.comp |= value;
  632. break;
  633. case MENELAUS_S1_PULL_EN:
  634. s->pull[0] = value;
  635. break;
  636. case MENELAUS_S1_PULL_DIR:
  637. s->pull[1] = value & 0x1f;
  638. break;
  639. case MENELAUS_S2_PULL_EN:
  640. s->pull[2] = value;
  641. break;
  642. case MENELAUS_S2_PULL_DIR:
  643. s->pull[3] = value & 0x1f;
  644. break;
  645. case MENELAUS_MCT_CTRL1:
  646. s->mmc_ctrl[0] = value & 0x7f;
  647. break;
  648. case MENELAUS_MCT_CTRL2:
  649. s->mmc_ctrl[1] = value;
  650. /* TODO update Card Detect interrupts */
  651. break;
  652. case MENELAUS_MCT_CTRL3:
  653. s->mmc_ctrl[2] = value & 0xf;
  654. break;
  655. case MENELAUS_DEBOUNCE1:
  656. s->mmc_debounce = value & 0x3f;
  657. break;
  658. default:
  659. #ifdef VERBOSE
  660. printf("%s: unknown register %02x\n", __func__, addr);
  661. #endif
  662. }
  663. }
  664. static int menelaus_event(I2CSlave *i2c, enum i2c_event event)
  665. {
  666. MenelausState *s = TWL92230(i2c);
  667. if (event == I2C_START_SEND)
  668. s->firstbyte = 1;
  669. return 0;
  670. }
  671. static int menelaus_tx(I2CSlave *i2c, uint8_t data)
  672. {
  673. MenelausState *s = TWL92230(i2c);
  674. /* Interpret register address byte */
  675. if (s->firstbyte) {
  676. s->reg = data;
  677. s->firstbyte = 0;
  678. } else
  679. menelaus_write(s, s->reg ++, data);
  680. return 0;
  681. }
  682. static uint8_t menelaus_rx(I2CSlave *i2c)
  683. {
  684. MenelausState *s = TWL92230(i2c);
  685. return menelaus_read(s, s->reg ++);
  686. }
  687. /* Save restore 32 bit int as uint16_t
  688. This is a Big hack, but it is how the old state did it.
  689. Or we broke compatibility in the state, or we can't use struct tm
  690. */
  691. static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
  692. const VMStateField *field)
  693. {
  694. int *v = pv;
  695. *v = qemu_get_be16(f);
  696. return 0;
  697. }
  698. static int put_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
  699. const VMStateField *field, QJSON *vmdesc)
  700. {
  701. int *v = pv;
  702. qemu_put_be16(f, *v);
  703. return 0;
  704. }
  705. static const VMStateInfo vmstate_hack_int32_as_uint16 = {
  706. .name = "int32_as_uint16",
  707. .get = get_int32_as_uint16,
  708. .put = put_int32_as_uint16,
  709. };
  710. #define VMSTATE_UINT16_HACK(_f, _s) \
  711. VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
  712. static const VMStateDescription vmstate_menelaus_tm = {
  713. .name = "menelaus_tm",
  714. .version_id = 0,
  715. .minimum_version_id = 0,
  716. .fields = (VMStateField[]) {
  717. VMSTATE_UINT16_HACK(tm_sec, struct tm),
  718. VMSTATE_UINT16_HACK(tm_min, struct tm),
  719. VMSTATE_UINT16_HACK(tm_hour, struct tm),
  720. VMSTATE_UINT16_HACK(tm_mday, struct tm),
  721. VMSTATE_UINT16_HACK(tm_min, struct tm),
  722. VMSTATE_UINT16_HACK(tm_year, struct tm),
  723. VMSTATE_END_OF_LIST()
  724. }
  725. };
  726. static int menelaus_pre_save(void *opaque)
  727. {
  728. MenelausState *s = opaque;
  729. /* Should be <= 1000 */
  730. s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
  731. return 0;
  732. }
  733. static int menelaus_post_load(void *opaque, int version_id)
  734. {
  735. MenelausState *s = opaque;
  736. if (s->rtc.ctrl & 1) /* RTC_EN */
  737. menelaus_rtc_stop(s);
  738. s->rtc.next = s->rtc_next_vmstate;
  739. menelaus_alm_update(s);
  740. menelaus_update(s);
  741. if (s->rtc.ctrl & 1) /* RTC_EN */
  742. menelaus_rtc_start(s);
  743. return 0;
  744. }
  745. static const VMStateDescription vmstate_menelaus = {
  746. .name = "menelaus",
  747. .version_id = 0,
  748. .minimum_version_id = 0,
  749. .pre_save = menelaus_pre_save,
  750. .post_load = menelaus_post_load,
  751. .fields = (VMStateField[]) {
  752. VMSTATE_INT32(firstbyte, MenelausState),
  753. VMSTATE_UINT8(reg, MenelausState),
  754. VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
  755. VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
  756. VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
  757. VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
  758. VMSTATE_UINT8(osc, MenelausState),
  759. VMSTATE_UINT8(detect, MenelausState),
  760. VMSTATE_UINT16(mask, MenelausState),
  761. VMSTATE_UINT16(status, MenelausState),
  762. VMSTATE_UINT8(dir, MenelausState),
  763. VMSTATE_UINT8(inputs, MenelausState),
  764. VMSTATE_UINT8(outputs, MenelausState),
  765. VMSTATE_UINT8(bbsms, MenelausState),
  766. VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
  767. VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
  768. VMSTATE_UINT8(mmc_debounce, MenelausState),
  769. VMSTATE_UINT8(rtc.ctrl, MenelausState),
  770. VMSTATE_UINT16(rtc.comp, MenelausState),
  771. VMSTATE_UINT16(rtc_next_vmstate, MenelausState),
  772. VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
  773. struct tm),
  774. VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
  775. struct tm),
  776. VMSTATE_UINT8(pwrbtn_state, MenelausState),
  777. VMSTATE_I2C_SLAVE(parent_obj, MenelausState),
  778. VMSTATE_END_OF_LIST()
  779. }
  780. };
  781. static void twl92230_realize(DeviceState *dev, Error **errp)
  782. {
  783. MenelausState *s = TWL92230(dev);
  784. s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
  785. /* Three output pins plus one interrupt pin. */
  786. qdev_init_gpio_out(dev, s->out, 4);
  787. /* Three input pins plus one power-button pin. */
  788. qdev_init_gpio_in(dev, menelaus_gpio_set, 4);
  789. menelaus_reset(I2C_SLAVE(dev));
  790. }
  791. static void twl92230_class_init(ObjectClass *klass, void *data)
  792. {
  793. DeviceClass *dc = DEVICE_CLASS(klass);
  794. I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
  795. dc->realize = twl92230_realize;
  796. sc->event = menelaus_event;
  797. sc->recv = menelaus_rx;
  798. sc->send = menelaus_tx;
  799. dc->vmsd = &vmstate_menelaus;
  800. }
  801. static const TypeInfo twl92230_info = {
  802. .name = TYPE_TWL92230,
  803. .parent = TYPE_I2C_SLAVE,
  804. .instance_size = sizeof(MenelausState),
  805. .class_init = twl92230_class_init,
  806. };
  807. static void twl92230_register_types(void)
  808. {
  809. type_register_static(&twl92230_info);
  810. }
  811. type_init(twl92230_register_types)