spapr_iommu.c 20 KB

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  1. /*
  2. * QEMU sPAPR IOMMU (TCE) code
  3. *
  4. * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
  5. *
  6. * This library is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU Lesser General Public
  8. * License as published by the Free Software Foundation; either
  9. * version 2 of the License, or (at your option) any later version.
  10. *
  11. * This library is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * Lesser General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU Lesser General Public
  17. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "qemu/error-report.h"
  21. #include "qemu/log.h"
  22. #include "qemu/module.h"
  23. #include "sysemu/kvm.h"
  24. #include "kvm_ppc.h"
  25. #include "migration/vmstate.h"
  26. #include "sysemu/dma.h"
  27. #include "exec/address-spaces.h"
  28. #include "trace.h"
  29. #include "hw/ppc/spapr.h"
  30. #include "hw/ppc/spapr_vio.h"
  31. #include <libfdt.h>
  32. enum SpaprTceAccess {
  33. SPAPR_TCE_FAULT = 0,
  34. SPAPR_TCE_RO = 1,
  35. SPAPR_TCE_WO = 2,
  36. SPAPR_TCE_RW = 3,
  37. };
  38. #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
  39. #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
  40. static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables;
  41. SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn)
  42. {
  43. SpaprTceTable *tcet;
  44. if (liobn & 0xFFFFFFFF00000000ULL) {
  45. hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
  46. liobn);
  47. return NULL;
  48. }
  49. QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
  50. if (tcet->liobn == (uint32_t)liobn) {
  51. return tcet;
  52. }
  53. }
  54. return NULL;
  55. }
  56. static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
  57. {
  58. switch (tce & SPAPR_TCE_RW) {
  59. case SPAPR_TCE_FAULT:
  60. return IOMMU_NONE;
  61. case SPAPR_TCE_RO:
  62. return IOMMU_RO;
  63. case SPAPR_TCE_WO:
  64. return IOMMU_WO;
  65. default: /* SPAPR_TCE_RW */
  66. return IOMMU_RW;
  67. }
  68. }
  69. static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
  70. uint32_t page_shift,
  71. uint64_t bus_offset,
  72. uint32_t nb_table,
  73. int *fd,
  74. bool need_vfio)
  75. {
  76. uint64_t *table = NULL;
  77. if (kvm_enabled()) {
  78. table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
  79. fd, need_vfio);
  80. }
  81. if (!table) {
  82. *fd = -1;
  83. table = g_new0(uint64_t, nb_table);
  84. }
  85. trace_spapr_iommu_new_table(liobn, table, *fd);
  86. return table;
  87. }
  88. static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
  89. {
  90. if (!kvm_enabled() ||
  91. (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
  92. g_free(table);
  93. }
  94. }
  95. /* Called from RCU critical section */
  96. static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
  97. hwaddr addr,
  98. IOMMUAccessFlags flag,
  99. int iommu_idx)
  100. {
  101. SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
  102. uint64_t tce;
  103. IOMMUTLBEntry ret = {
  104. .target_as = &address_space_memory,
  105. .iova = 0,
  106. .translated_addr = 0,
  107. .addr_mask = ~(hwaddr)0,
  108. .perm = IOMMU_NONE,
  109. };
  110. if ((addr >> tcet->page_shift) < tcet->nb_table) {
  111. /* Check if we are in bound */
  112. hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  113. tce = tcet->table[addr >> tcet->page_shift];
  114. ret.iova = addr & page_mask;
  115. ret.translated_addr = tce & page_mask;
  116. ret.addr_mask = ~page_mask;
  117. ret.perm = spapr_tce_iommu_access_flags(tce);
  118. }
  119. trace_spapr_iommu_xlate(tcet->liobn, addr, ret.translated_addr, ret.perm,
  120. ret.addr_mask);
  121. return ret;
  122. }
  123. static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
  124. {
  125. MemoryRegion *mr = MEMORY_REGION(iommu_mr);
  126. IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
  127. hwaddr addr, granularity;
  128. IOMMUTLBEntry iotlb;
  129. SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu);
  130. if (tcet->skipping_replay) {
  131. return;
  132. }
  133. granularity = memory_region_iommu_get_min_page_size(iommu_mr);
  134. for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
  135. iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
  136. if (iotlb.perm != IOMMU_NONE) {
  137. n->notify(n, &iotlb);
  138. }
  139. /*
  140. * if (2^64 - MR size) < granularity, it's possible to get an
  141. * infinite loop here. This should catch such a wraparound.
  142. */
  143. if ((addr + granularity) < addr) {
  144. break;
  145. }
  146. }
  147. }
  148. static int spapr_tce_table_pre_save(void *opaque)
  149. {
  150. SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
  151. tcet->mig_table = tcet->table;
  152. tcet->mig_nb_table = tcet->nb_table;
  153. trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
  154. tcet->bus_offset, tcet->page_shift);
  155. return 0;
  156. }
  157. static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
  158. {
  159. SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
  160. return 1ULL << tcet->page_shift;
  161. }
  162. static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
  163. enum IOMMUMemoryRegionAttr attr, void *data)
  164. {
  165. SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
  166. if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
  167. *(int *) data = tcet->fd;
  168. return 0;
  169. }
  170. return -EINVAL;
  171. }
  172. static int spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
  173. IOMMUNotifierFlag old,
  174. IOMMUNotifierFlag new,
  175. Error **errp)
  176. {
  177. struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu);
  178. if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
  179. spapr_tce_set_need_vfio(tbl, true);
  180. } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
  181. spapr_tce_set_need_vfio(tbl, false);
  182. }
  183. return 0;
  184. }
  185. static int spapr_tce_table_post_load(void *opaque, int version_id)
  186. {
  187. SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
  188. uint32_t old_nb_table = tcet->nb_table;
  189. uint64_t old_bus_offset = tcet->bus_offset;
  190. uint32_t old_page_shift = tcet->page_shift;
  191. if (tcet->vdev) {
  192. spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
  193. }
  194. if (tcet->mig_nb_table != tcet->nb_table) {
  195. spapr_tce_table_disable(tcet);
  196. }
  197. if (tcet->mig_nb_table) {
  198. if (!tcet->nb_table) {
  199. spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
  200. tcet->mig_nb_table);
  201. }
  202. memcpy(tcet->table, tcet->mig_table,
  203. tcet->nb_table * sizeof(tcet->table[0]));
  204. free(tcet->mig_table);
  205. tcet->mig_table = NULL;
  206. }
  207. trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
  208. tcet->bus_offset, tcet->page_shift);
  209. return 0;
  210. }
  211. static bool spapr_tce_table_ex_needed(void *opaque)
  212. {
  213. SpaprTceTable *tcet = opaque;
  214. return tcet->bus_offset || tcet->page_shift != 0xC;
  215. }
  216. static const VMStateDescription vmstate_spapr_tce_table_ex = {
  217. .name = "spapr_iommu_ex",
  218. .version_id = 1,
  219. .minimum_version_id = 1,
  220. .needed = spapr_tce_table_ex_needed,
  221. .fields = (VMStateField[]) {
  222. VMSTATE_UINT64(bus_offset, SpaprTceTable),
  223. VMSTATE_UINT32(page_shift, SpaprTceTable),
  224. VMSTATE_END_OF_LIST()
  225. },
  226. };
  227. static const VMStateDescription vmstate_spapr_tce_table = {
  228. .name = "spapr_iommu",
  229. .version_id = 2,
  230. .minimum_version_id = 2,
  231. .pre_save = spapr_tce_table_pre_save,
  232. .post_load = spapr_tce_table_post_load,
  233. .fields = (VMStateField []) {
  234. /* Sanity check */
  235. VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL),
  236. /* IOMMU state */
  237. VMSTATE_UINT32(mig_nb_table, SpaprTceTable),
  238. VMSTATE_BOOL(bypass, SpaprTceTable),
  239. VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0,
  240. vmstate_info_uint64, uint64_t),
  241. VMSTATE_END_OF_LIST()
  242. },
  243. .subsections = (const VMStateDescription*[]) {
  244. &vmstate_spapr_tce_table_ex,
  245. NULL
  246. }
  247. };
  248. static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
  249. {
  250. SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
  251. Object *tcetobj = OBJECT(tcet);
  252. gchar *tmp;
  253. tcet->fd = -1;
  254. tcet->need_vfio = false;
  255. tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
  256. memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
  257. g_free(tmp);
  258. tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
  259. memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
  260. TYPE_SPAPR_IOMMU_MEMORY_REGION,
  261. tcetobj, tmp, 0);
  262. g_free(tmp);
  263. QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
  264. vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
  265. tcet);
  266. }
  267. void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio)
  268. {
  269. size_t table_size = tcet->nb_table * sizeof(uint64_t);
  270. uint64_t *oldtable;
  271. int newfd = -1;
  272. g_assert(need_vfio != tcet->need_vfio);
  273. tcet->need_vfio = need_vfio;
  274. if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
  275. return;
  276. }
  277. oldtable = tcet->table;
  278. tcet->table = spapr_tce_alloc_table(tcet->liobn,
  279. tcet->page_shift,
  280. tcet->bus_offset,
  281. tcet->nb_table,
  282. &newfd,
  283. need_vfio);
  284. memcpy(tcet->table, oldtable, table_size);
  285. spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
  286. tcet->fd = newfd;
  287. }
  288. SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
  289. {
  290. SpaprTceTable *tcet;
  291. gchar *tmp;
  292. if (spapr_tce_find_by_liobn(liobn)) {
  293. error_report("Attempted to create TCE table with duplicate"
  294. " LIOBN 0x%x", liobn);
  295. return NULL;
  296. }
  297. tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
  298. tcet->liobn = liobn;
  299. tmp = g_strdup_printf("tce-table-%x", liobn);
  300. object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
  301. g_free(tmp);
  302. object_unref(OBJECT(tcet));
  303. object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
  304. return tcet;
  305. }
  306. void spapr_tce_table_enable(SpaprTceTable *tcet,
  307. uint32_t page_shift, uint64_t bus_offset,
  308. uint32_t nb_table)
  309. {
  310. if (tcet->nb_table) {
  311. warn_report("trying to enable already enabled TCE table");
  312. return;
  313. }
  314. tcet->bus_offset = bus_offset;
  315. tcet->page_shift = page_shift;
  316. tcet->nb_table = nb_table;
  317. tcet->table = spapr_tce_alloc_table(tcet->liobn,
  318. tcet->page_shift,
  319. tcet->bus_offset,
  320. tcet->nb_table,
  321. &tcet->fd,
  322. tcet->need_vfio);
  323. memory_region_set_size(MEMORY_REGION(&tcet->iommu),
  324. (uint64_t)tcet->nb_table << tcet->page_shift);
  325. memory_region_add_subregion(&tcet->root, tcet->bus_offset,
  326. MEMORY_REGION(&tcet->iommu));
  327. }
  328. void spapr_tce_table_disable(SpaprTceTable *tcet)
  329. {
  330. if (!tcet->nb_table) {
  331. return;
  332. }
  333. memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
  334. memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
  335. spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
  336. tcet->fd = -1;
  337. tcet->table = NULL;
  338. tcet->bus_offset = 0;
  339. tcet->page_shift = 0;
  340. tcet->nb_table = 0;
  341. }
  342. static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
  343. {
  344. SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
  345. vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet);
  346. QLIST_REMOVE(tcet, list);
  347. spapr_tce_table_disable(tcet);
  348. }
  349. MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet)
  350. {
  351. return &tcet->root;
  352. }
  353. static void spapr_tce_reset(DeviceState *dev)
  354. {
  355. SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
  356. size_t table_size = tcet->nb_table * sizeof(uint64_t);
  357. if (tcet->nb_table) {
  358. memset(tcet->table, 0, table_size);
  359. }
  360. }
  361. static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
  362. target_ulong tce)
  363. {
  364. IOMMUTLBEntry entry;
  365. hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  366. unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
  367. if (index >= tcet->nb_table) {
  368. hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
  369. TARGET_FMT_lx "\n", ioba);
  370. return H_PARAMETER;
  371. }
  372. tcet->table[index] = tce;
  373. entry.target_as = &address_space_memory,
  374. entry.iova = (ioba - tcet->bus_offset) & page_mask;
  375. entry.translated_addr = tce & page_mask;
  376. entry.addr_mask = ~page_mask;
  377. entry.perm = spapr_tce_iommu_access_flags(tce);
  378. memory_region_notify_iommu(&tcet->iommu, 0, entry);
  379. return H_SUCCESS;
  380. }
  381. static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
  382. SpaprMachineState *spapr,
  383. target_ulong opcode, target_ulong *args)
  384. {
  385. int i;
  386. target_ulong liobn = args[0];
  387. target_ulong ioba = args[1];
  388. target_ulong ioba1 = ioba;
  389. target_ulong tce_list = args[2];
  390. target_ulong npages = args[3];
  391. target_ulong ret = H_PARAMETER, tce = 0;
  392. SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
  393. CPUState *cs = CPU(cpu);
  394. hwaddr page_mask, page_size;
  395. if (!tcet) {
  396. return H_PARAMETER;
  397. }
  398. if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
  399. return H_PARAMETER;
  400. }
  401. page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  402. page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
  403. ioba &= page_mask;
  404. for (i = 0; i < npages; ++i, ioba += page_size) {
  405. tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
  406. ret = put_tce_emu(tcet, ioba, tce);
  407. if (ret) {
  408. break;
  409. }
  410. }
  411. /* Trace last successful or the first problematic entry */
  412. i = i ? (i - 1) : 0;
  413. if (SPAPR_IS_PCI_LIOBN(liobn)) {
  414. trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
  415. } else {
  416. trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
  417. }
  418. return ret;
  419. }
  420. static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
  421. target_ulong opcode, target_ulong *args)
  422. {
  423. int i;
  424. target_ulong liobn = args[0];
  425. target_ulong ioba = args[1];
  426. target_ulong tce_value = args[2];
  427. target_ulong npages = args[3];
  428. target_ulong ret = H_PARAMETER;
  429. SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
  430. hwaddr page_mask, page_size;
  431. if (!tcet) {
  432. return H_PARAMETER;
  433. }
  434. if (npages > tcet->nb_table) {
  435. return H_PARAMETER;
  436. }
  437. page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  438. page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
  439. ioba &= page_mask;
  440. for (i = 0; i < npages; ++i, ioba += page_size) {
  441. ret = put_tce_emu(tcet, ioba, tce_value);
  442. if (ret) {
  443. break;
  444. }
  445. }
  446. if (SPAPR_IS_PCI_LIOBN(liobn)) {
  447. trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
  448. } else {
  449. trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
  450. }
  451. return ret;
  452. }
  453. static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
  454. target_ulong opcode, target_ulong *args)
  455. {
  456. target_ulong liobn = args[0];
  457. target_ulong ioba = args[1];
  458. target_ulong tce = args[2];
  459. target_ulong ret = H_PARAMETER;
  460. SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
  461. if (tcet) {
  462. hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  463. ioba &= page_mask;
  464. ret = put_tce_emu(tcet, ioba, tce);
  465. }
  466. if (SPAPR_IS_PCI_LIOBN(liobn)) {
  467. trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
  468. } else {
  469. trace_spapr_iommu_put(liobn, ioba, tce, ret);
  470. }
  471. return ret;
  472. }
  473. static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
  474. target_ulong *tce)
  475. {
  476. unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
  477. if (index >= tcet->nb_table) {
  478. hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
  479. TARGET_FMT_lx "\n", ioba);
  480. return H_PARAMETER;
  481. }
  482. *tce = tcet->table[index];
  483. return H_SUCCESS;
  484. }
  485. static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
  486. target_ulong opcode, target_ulong *args)
  487. {
  488. target_ulong liobn = args[0];
  489. target_ulong ioba = args[1];
  490. target_ulong tce = 0;
  491. target_ulong ret = H_PARAMETER;
  492. SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
  493. if (tcet) {
  494. hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  495. ioba &= page_mask;
  496. ret = get_tce_emu(tcet, ioba, &tce);
  497. if (!ret) {
  498. args[0] = tce;
  499. }
  500. }
  501. if (SPAPR_IS_PCI_LIOBN(liobn)) {
  502. trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
  503. } else {
  504. trace_spapr_iommu_get(liobn, ioba, ret, tce);
  505. }
  506. return ret;
  507. }
  508. int spapr_dma_dt(void *fdt, int node_off, const char *propname,
  509. uint32_t liobn, uint64_t window, uint32_t size)
  510. {
  511. uint32_t dma_prop[5];
  512. int ret;
  513. dma_prop[0] = cpu_to_be32(liobn);
  514. dma_prop[1] = cpu_to_be32(window >> 32);
  515. dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
  516. dma_prop[3] = 0; /* window size is 32 bits */
  517. dma_prop[4] = cpu_to_be32(size);
  518. ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
  519. if (ret < 0) {
  520. return ret;
  521. }
  522. ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
  523. if (ret < 0) {
  524. return ret;
  525. }
  526. ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
  527. if (ret < 0) {
  528. return ret;
  529. }
  530. return 0;
  531. }
  532. int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
  533. SpaprTceTable *tcet)
  534. {
  535. if (!tcet) {
  536. return 0;
  537. }
  538. return spapr_dma_dt(fdt, node_off, propname,
  539. tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
  540. }
  541. static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
  542. {
  543. DeviceClass *dc = DEVICE_CLASS(klass);
  544. dc->realize = spapr_tce_table_realize;
  545. dc->reset = spapr_tce_reset;
  546. dc->unrealize = spapr_tce_table_unrealize;
  547. /* Reason: This is just an internal device for handling the hypercalls */
  548. dc->user_creatable = false;
  549. QLIST_INIT(&spapr_tce_tables);
  550. /* hcall-tce */
  551. spapr_register_hypercall(H_PUT_TCE, h_put_tce);
  552. spapr_register_hypercall(H_GET_TCE, h_get_tce);
  553. spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
  554. spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
  555. }
  556. static TypeInfo spapr_tce_table_info = {
  557. .name = TYPE_SPAPR_TCE_TABLE,
  558. .parent = TYPE_DEVICE,
  559. .instance_size = sizeof(SpaprTceTable),
  560. .class_init = spapr_tce_table_class_init,
  561. };
  562. static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
  563. {
  564. IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
  565. imrc->translate = spapr_tce_translate_iommu;
  566. imrc->replay = spapr_tce_replay;
  567. imrc->get_min_page_size = spapr_tce_get_min_page_size;
  568. imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
  569. imrc->get_attr = spapr_tce_get_attr;
  570. }
  571. static const TypeInfo spapr_iommu_memory_region_info = {
  572. .parent = TYPE_IOMMU_MEMORY_REGION,
  573. .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
  574. .class_init = spapr_iommu_memory_region_class_init,
  575. };
  576. static void register_types(void)
  577. {
  578. type_register_static(&spapr_tce_table_info);
  579. type_register_static(&spapr_iommu_memory_region_info);
  580. }
  581. type_init(register_types);