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sungem.c 43 KB

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  1. /*
  2. * QEMU model of SUN GEM ethernet controller
  3. *
  4. * As found in Apple ASICs among others
  5. *
  6. * Copyright 2016 Ben Herrenschmidt
  7. * Copyright 2017 Mark Cave-Ayland
  8. */
  9. #include "qemu/osdep.h"
  10. #include "hw/pci/pci.h"
  11. #include "hw/qdev-properties.h"
  12. #include "migration/vmstate.h"
  13. #include "qemu/log.h"
  14. #include "qemu/module.h"
  15. #include "net/net.h"
  16. #include "net/eth.h"
  17. #include "net/checksum.h"
  18. #include "hw/net/mii.h"
  19. #include "sysemu/sysemu.h"
  20. #include "trace.h"
  21. #define TYPE_SUNGEM "sungem"
  22. #define SUNGEM(obj) OBJECT_CHECK(SunGEMState, (obj), TYPE_SUNGEM)
  23. #define MAX_PACKET_SIZE 9016
  24. #define SUNGEM_MMIO_SIZE 0x200000
  25. /* Global registers */
  26. #define SUNGEM_MMIO_GREG_SIZE 0x2000
  27. #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
  28. #define GREG_STAT 0x000CUL /* Status Register */
  29. #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
  30. #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
  31. #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
  32. #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
  33. #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
  34. #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
  35. #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
  36. #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
  37. #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
  38. #define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */
  39. #define GREG_STAT_TXNR_SHIFT 19
  40. /* These interrupts are edge latches in the status register,
  41. * reading it (or writing the corresponding bit in IACK) will
  42. * clear them
  43. */
  44. #define GREG_STAT_LATCH (GREG_STAT_TXALL | GREG_STAT_TXINTME | \
  45. GREG_STAT_RXDONE | GREG_STAT_RXDONE | \
  46. GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR)
  47. #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
  48. #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
  49. #define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */
  50. #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
  51. #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
  52. #define GREG_SWRST 0x1010UL /* Software Reset Register */
  53. #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */
  54. #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */
  55. #define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */
  56. /* TX DMA Registers */
  57. #define SUNGEM_MMIO_TXDMA_SIZE 0x1000
  58. #define TXDMA_KICK 0x0000UL /* TX Kick Register */
  59. #define TXDMA_CFG 0x0004UL /* TX Configuration Register */
  60. #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
  61. #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */
  62. #define TXDMA_DBLOW 0x0008UL /* TX Desc. Base Low */
  63. #define TXDMA_DBHI 0x000CUL /* TX Desc. Base High */
  64. #define TXDMA_PCNT 0x0024UL /* TX FIFO Packet Counter */
  65. #define TXDMA_SMACHINE 0x0028UL /* TX State Machine Register */
  66. #define TXDMA_DPLOW 0x0030UL /* TX Data Pointer Low */
  67. #define TXDMA_DPHI 0x0034UL /* TX Data Pointer High */
  68. #define TXDMA_TXDONE 0x0100UL /* TX Completion Register */
  69. #define TXDMA_FTAG 0x0108UL /* TX FIFO Tag */
  70. #define TXDMA_FSZ 0x0118UL /* TX FIFO Size */
  71. /* Receive DMA Registers */
  72. #define SUNGEM_MMIO_RXDMA_SIZE 0x2000
  73. #define RXDMA_CFG 0x0000UL /* RX Configuration Register */
  74. #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
  75. #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */
  76. #define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */
  77. #define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */
  78. #define RXDMA_DBLOW 0x0004UL /* RX Descriptor Base Low */
  79. #define RXDMA_DBHI 0x0008UL /* RX Descriptor Base High */
  80. #define RXDMA_PCNT 0x0018UL /* RX FIFO Packet Counter */
  81. #define RXDMA_SMACHINE 0x001CUL /* RX State Machine Register */
  82. #define RXDMA_PTHRESH 0x0020UL /* Pause Thresholds */
  83. #define RXDMA_DPLOW 0x0024UL /* RX Data Pointer Low */
  84. #define RXDMA_DPHI 0x0028UL /* RX Data Pointer High */
  85. #define RXDMA_KICK 0x0100UL /* RX Kick Register */
  86. #define RXDMA_DONE 0x0104UL /* RX Completion Register */
  87. #define RXDMA_BLANK 0x0108UL /* RX Blanking Register */
  88. #define RXDMA_FTAG 0x0110UL /* RX FIFO Tag */
  89. #define RXDMA_FSZ 0x0120UL /* RX FIFO Size */
  90. /* MAC Registers */
  91. #define SUNGEM_MMIO_MAC_SIZE 0x200
  92. #define MAC_TXRST 0x0000UL /* TX MAC Software Reset Command */
  93. #define MAC_RXRST 0x0004UL /* RX MAC Software Reset Command */
  94. #define MAC_TXSTAT 0x0010UL /* TX MAC Status Register */
  95. #define MAC_RXSTAT 0x0014UL /* RX MAC Status Register */
  96. #define MAC_CSTAT 0x0018UL /* MAC Control Status Register */
  97. #define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */
  98. #define MAC_TXMASK 0x0020UL /* TX MAC Mask Register */
  99. #define MAC_RXMASK 0x0024UL /* RX MAC Mask Register */
  100. #define MAC_MCMASK 0x0028UL /* MAC Control Mask Register */
  101. #define MAC_TXCFG 0x0030UL /* TX MAC Configuration Register */
  102. #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
  103. #define MAC_RXCFG 0x0034UL /* RX MAC Configuration Register */
  104. #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
  105. #define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */
  106. #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */
  107. #define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */
  108. #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
  109. #define MAC_XIFCFG 0x003CUL /* XIF Configuration Register */
  110. #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
  111. #define MAC_MINFSZ 0x0050UL /* MinFrameSize Register */
  112. #define MAC_MAXFSZ 0x0054UL /* MaxFrameSize Register */
  113. #define MAC_ADDR0 0x0080UL /* MAC Address 0 Register */
  114. #define MAC_ADDR1 0x0084UL /* MAC Address 1 Register */
  115. #define MAC_ADDR2 0x0088UL /* MAC Address 2 Register */
  116. #define MAC_ADDR3 0x008CUL /* MAC Address 3 Register */
  117. #define MAC_ADDR4 0x0090UL /* MAC Address 4 Register */
  118. #define MAC_ADDR5 0x0094UL /* MAC Address 5 Register */
  119. #define MAC_HASH0 0x00C0UL /* Hash Table 0 Register */
  120. #define MAC_PATMPS 0x0114UL /* Peak Attempts Register */
  121. #define MAC_SMACHINE 0x0134UL /* State Machine Register */
  122. /* MIF Registers */
  123. #define SUNGEM_MMIO_MIF_SIZE 0x20
  124. #define MIF_FRAME 0x000CUL /* MIF Frame/Output Register */
  125. #define MIF_FRAME_OP 0x30000000 /* OPcode */
  126. #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */
  127. #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
  128. #define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */
  129. #define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */
  130. #define MIF_CFG 0x0010UL /* MIF Configuration Register */
  131. #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
  132. #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
  133. #define MIF_STATUS 0x0018UL /* MIF Status Register */
  134. #define MIF_SMACHINE 0x001CUL /* MIF State Machine Register */
  135. /* PCS/Serialink Registers */
  136. #define SUNGEM_MMIO_PCS_SIZE 0x60
  137. #define PCS_MIISTAT 0x0004UL /* PCS MII Status Register */
  138. #define PCS_ISTAT 0x0018UL /* PCS Interrupt Status Reg */
  139. #define PCS_SSTATE 0x005CUL /* Serialink State Register */
  140. /* Descriptors */
  141. struct gem_txd {
  142. uint64_t control_word;
  143. uint64_t buffer;
  144. };
  145. #define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */
  146. #define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */
  147. #define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */
  148. #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
  149. #define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */
  150. #define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */
  151. #define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */
  152. struct gem_rxd {
  153. uint64_t status_word;
  154. uint64_t buffer;
  155. };
  156. #define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */
  157. #define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */
  158. typedef struct {
  159. PCIDevice pdev;
  160. MemoryRegion sungem;
  161. MemoryRegion greg;
  162. MemoryRegion txdma;
  163. MemoryRegion rxdma;
  164. MemoryRegion mac;
  165. MemoryRegion mif;
  166. MemoryRegion pcs;
  167. NICState *nic;
  168. NICConf conf;
  169. uint32_t phy_addr;
  170. uint32_t gregs[SUNGEM_MMIO_GREG_SIZE >> 2];
  171. uint32_t txdmaregs[SUNGEM_MMIO_TXDMA_SIZE >> 2];
  172. uint32_t rxdmaregs[SUNGEM_MMIO_RXDMA_SIZE >> 2];
  173. uint32_t macregs[SUNGEM_MMIO_MAC_SIZE >> 2];
  174. uint32_t mifregs[SUNGEM_MMIO_MIF_SIZE >> 2];
  175. uint32_t pcsregs[SUNGEM_MMIO_PCS_SIZE >> 2];
  176. /* Cache some useful things */
  177. uint32_t rx_mask;
  178. uint32_t tx_mask;
  179. /* Current tx packet */
  180. uint8_t tx_data[MAX_PACKET_SIZE];
  181. uint32_t tx_size;
  182. uint64_t tx_first_ctl;
  183. } SunGEMState;
  184. static void sungem_eval_irq(SunGEMState *s)
  185. {
  186. uint32_t stat, mask;
  187. mask = s->gregs[GREG_IMASK >> 2];
  188. stat = s->gregs[GREG_STAT >> 2] & ~GREG_STAT_TXNR;
  189. if (stat & ~mask) {
  190. pci_set_irq(PCI_DEVICE(s), 1);
  191. } else {
  192. pci_set_irq(PCI_DEVICE(s), 0);
  193. }
  194. }
  195. static void sungem_update_status(SunGEMState *s, uint32_t bits, bool val)
  196. {
  197. uint32_t stat;
  198. stat = s->gregs[GREG_STAT >> 2];
  199. if (val) {
  200. stat |= bits;
  201. } else {
  202. stat &= ~bits;
  203. }
  204. s->gregs[GREG_STAT >> 2] = stat;
  205. sungem_eval_irq(s);
  206. }
  207. static void sungem_eval_cascade_irq(SunGEMState *s)
  208. {
  209. uint32_t stat, mask;
  210. mask = s->macregs[MAC_TXSTAT >> 2];
  211. stat = s->macregs[MAC_TXMASK >> 2];
  212. if (stat & ~mask) {
  213. sungem_update_status(s, GREG_STAT_TXMAC, true);
  214. } else {
  215. sungem_update_status(s, GREG_STAT_TXMAC, false);
  216. }
  217. mask = s->macregs[MAC_RXSTAT >> 2];
  218. stat = s->macregs[MAC_RXMASK >> 2];
  219. if (stat & ~mask) {
  220. sungem_update_status(s, GREG_STAT_RXMAC, true);
  221. } else {
  222. sungem_update_status(s, GREG_STAT_RXMAC, false);
  223. }
  224. mask = s->macregs[MAC_CSTAT >> 2];
  225. stat = s->macregs[MAC_MCMASK >> 2] & ~MAC_CSTAT_PTR;
  226. if (stat & ~mask) {
  227. sungem_update_status(s, GREG_STAT_MAC, true);
  228. } else {
  229. sungem_update_status(s, GREG_STAT_MAC, false);
  230. }
  231. }
  232. static void sungem_do_tx_csum(SunGEMState *s)
  233. {
  234. uint16_t start, off;
  235. uint32_t csum;
  236. start = (s->tx_first_ctl & TXDCTRL_CSTART) >> 15;
  237. off = (s->tx_first_ctl & TXDCTRL_COFF) >> 21;
  238. trace_sungem_tx_checksum(start, off);
  239. if (start > (s->tx_size - 2) || off > (s->tx_size - 2)) {
  240. trace_sungem_tx_checksum_oob();
  241. return;
  242. }
  243. csum = net_raw_checksum(s->tx_data + start, s->tx_size - start);
  244. stw_be_p(s->tx_data + off, csum);
  245. }
  246. static void sungem_send_packet(SunGEMState *s, const uint8_t *buf,
  247. int size)
  248. {
  249. NetClientState *nc = qemu_get_queue(s->nic);
  250. if (s->macregs[MAC_XIFCFG >> 2] & MAC_XIFCFG_LBCK) {
  251. nc->info->receive(nc, buf, size);
  252. } else {
  253. qemu_send_packet(nc, buf, size);
  254. }
  255. }
  256. static void sungem_process_tx_desc(SunGEMState *s, struct gem_txd *desc)
  257. {
  258. PCIDevice *d = PCI_DEVICE(s);
  259. uint32_t len;
  260. /* If it's a start of frame, discard anything we had in the
  261. * buffer and start again. This should be an error condition
  262. * if we had something ... for now we ignore it
  263. */
  264. if (desc->control_word & TXDCTRL_SOF) {
  265. if (s->tx_first_ctl) {
  266. trace_sungem_tx_unfinished();
  267. }
  268. s->tx_size = 0;
  269. s->tx_first_ctl = desc->control_word;
  270. }
  271. /* Grab data size */
  272. len = desc->control_word & TXDCTRL_BUFSZ;
  273. /* Clamp it to our max size */
  274. if ((s->tx_size + len) > MAX_PACKET_SIZE) {
  275. trace_sungem_tx_overflow();
  276. len = MAX_PACKET_SIZE - s->tx_size;
  277. }
  278. /* Read the data */
  279. pci_dma_read(d, desc->buffer, &s->tx_data[s->tx_size], len);
  280. s->tx_size += len;
  281. /* If end of frame, send packet */
  282. if (desc->control_word & TXDCTRL_EOF) {
  283. trace_sungem_tx_finished(s->tx_size);
  284. /* Handle csum */
  285. if (s->tx_first_ctl & TXDCTRL_CENAB) {
  286. sungem_do_tx_csum(s);
  287. }
  288. /* Send it */
  289. sungem_send_packet(s, s->tx_data, s->tx_size);
  290. /* No more pending packet */
  291. s->tx_size = 0;
  292. s->tx_first_ctl = 0;
  293. }
  294. }
  295. static void sungem_tx_kick(SunGEMState *s)
  296. {
  297. PCIDevice *d = PCI_DEVICE(s);
  298. uint32_t comp, kick;
  299. uint32_t txdma_cfg, txmac_cfg, ints;
  300. uint64_t dbase;
  301. trace_sungem_tx_kick();
  302. /* Check that both TX MAC and TX DMA are enabled. We don't
  303. * handle DMA-less direct FIFO operations (we don't emulate
  304. * the FIFO at all).
  305. *
  306. * A write to TXDMA_KICK while DMA isn't enabled can happen
  307. * when the driver is resetting the pointer.
  308. */
  309. txdma_cfg = s->txdmaregs[TXDMA_CFG >> 2];
  310. txmac_cfg = s->macregs[MAC_TXCFG >> 2];
  311. if (!(txdma_cfg & TXDMA_CFG_ENABLE) ||
  312. !(txmac_cfg & MAC_TXCFG_ENAB)) {
  313. trace_sungem_tx_disabled();
  314. return;
  315. }
  316. /* XXX Test min frame size register ? */
  317. /* XXX Test max frame size register ? */
  318. dbase = s->txdmaregs[TXDMA_DBHI >> 2];
  319. dbase = (dbase << 32) | s->txdmaregs[TXDMA_DBLOW >> 2];
  320. comp = s->txdmaregs[TXDMA_TXDONE >> 2] & s->tx_mask;
  321. kick = s->txdmaregs[TXDMA_KICK >> 2] & s->tx_mask;
  322. trace_sungem_tx_process(comp, kick, s->tx_mask + 1);
  323. /* This is rather primitive for now, we just send everything we
  324. * can in one go, like e1000. Ideally we should do the sending
  325. * from some kind of background task
  326. */
  327. while (comp != kick) {
  328. struct gem_txd desc;
  329. /* Read the next descriptor */
  330. pci_dma_read(d, dbase + comp * sizeof(desc), &desc, sizeof(desc));
  331. /* Byteswap descriptor */
  332. desc.control_word = le64_to_cpu(desc.control_word);
  333. desc.buffer = le64_to_cpu(desc.buffer);
  334. trace_sungem_tx_desc(comp, desc.control_word, desc.buffer);
  335. /* Send it for processing */
  336. sungem_process_tx_desc(s, &desc);
  337. /* Interrupt */
  338. ints = GREG_STAT_TXDONE;
  339. if (desc.control_word & TXDCTRL_INTME) {
  340. ints |= GREG_STAT_TXINTME;
  341. }
  342. sungem_update_status(s, ints, true);
  343. /* Next ! */
  344. comp = (comp + 1) & s->tx_mask;
  345. s->txdmaregs[TXDMA_TXDONE >> 2] = comp;
  346. }
  347. /* We sent everything, set status/irq bit */
  348. sungem_update_status(s, GREG_STAT_TXALL, true);
  349. }
  350. static bool sungem_rx_full(SunGEMState *s, uint32_t kick, uint32_t done)
  351. {
  352. return kick == ((done + 1) & s->rx_mask);
  353. }
  354. static int sungem_can_receive(NetClientState *nc)
  355. {
  356. SunGEMState *s = qemu_get_nic_opaque(nc);
  357. uint32_t kick, done, rxdma_cfg, rxmac_cfg;
  358. bool full;
  359. rxmac_cfg = s->macregs[MAC_RXCFG >> 2];
  360. rxdma_cfg = s->rxdmaregs[RXDMA_CFG >> 2];
  361. /* If MAC disabled, can't receive */
  362. if ((rxmac_cfg & MAC_RXCFG_ENAB) == 0) {
  363. trace_sungem_rx_mac_disabled();
  364. return 0;
  365. }
  366. if ((rxdma_cfg & RXDMA_CFG_ENABLE) == 0) {
  367. trace_sungem_rx_txdma_disabled();
  368. return 0;
  369. }
  370. /* Check RX availability */
  371. kick = s->rxdmaregs[RXDMA_KICK >> 2];
  372. done = s->rxdmaregs[RXDMA_DONE >> 2];
  373. full = sungem_rx_full(s, kick, done);
  374. trace_sungem_rx_check(!full, kick, done);
  375. return !full;
  376. }
  377. enum {
  378. rx_no_match,
  379. rx_match_promisc,
  380. rx_match_bcast,
  381. rx_match_allmcast,
  382. rx_match_mcast,
  383. rx_match_mac,
  384. rx_match_altmac,
  385. };
  386. static int sungem_check_rx_mac(SunGEMState *s, const uint8_t *mac, uint32_t crc)
  387. {
  388. uint32_t rxcfg = s->macregs[MAC_RXCFG >> 2];
  389. uint32_t mac0, mac1, mac2;
  390. /* Promisc enabled ? */
  391. if (rxcfg & MAC_RXCFG_PROM) {
  392. return rx_match_promisc;
  393. }
  394. /* Format MAC address into dwords */
  395. mac0 = (mac[4] << 8) | mac[5];
  396. mac1 = (mac[2] << 8) | mac[3];
  397. mac2 = (mac[0] << 8) | mac[1];
  398. trace_sungem_rx_mac_check(mac0, mac1, mac2);
  399. /* Is this a broadcast frame ? */
  400. if (mac0 == 0xffff && mac1 == 0xffff && mac2 == 0xffff) {
  401. return rx_match_bcast;
  402. }
  403. /* TODO: Implement address filter registers (or we don't care ?) */
  404. /* Is this a multicast frame ? */
  405. if (mac[0] & 1) {
  406. trace_sungem_rx_mac_multicast();
  407. /* Promisc group enabled ? */
  408. if (rxcfg & MAC_RXCFG_PGRP) {
  409. return rx_match_allmcast;
  410. }
  411. /* TODO: Check MAC control frames (or we don't care) ? */
  412. /* Check hash filter (somebody check that's correct ?) */
  413. if (rxcfg & MAC_RXCFG_HFE) {
  414. uint32_t hash, idx;
  415. crc >>= 24;
  416. idx = (crc >> 2) & 0x3c;
  417. hash = s->macregs[(MAC_HASH0 + idx) >> 2];
  418. if (hash & (1 << (15 - (crc & 0xf)))) {
  419. return rx_match_mcast;
  420. }
  421. }
  422. return rx_no_match;
  423. }
  424. /* Main MAC check */
  425. trace_sungem_rx_mac_compare(s->macregs[MAC_ADDR0 >> 2],
  426. s->macregs[MAC_ADDR1 >> 2],
  427. s->macregs[MAC_ADDR2 >> 2]);
  428. if (mac0 == s->macregs[MAC_ADDR0 >> 2] &&
  429. mac1 == s->macregs[MAC_ADDR1 >> 2] &&
  430. mac2 == s->macregs[MAC_ADDR2 >> 2]) {
  431. return rx_match_mac;
  432. }
  433. /* Alt MAC check */
  434. if (mac0 == s->macregs[MAC_ADDR3 >> 2] &&
  435. mac1 == s->macregs[MAC_ADDR4 >> 2] &&
  436. mac2 == s->macregs[MAC_ADDR5 >> 2]) {
  437. return rx_match_altmac;
  438. }
  439. return rx_no_match;
  440. }
  441. static ssize_t sungem_receive(NetClientState *nc, const uint8_t *buf,
  442. size_t size)
  443. {
  444. SunGEMState *s = qemu_get_nic_opaque(nc);
  445. PCIDevice *d = PCI_DEVICE(s);
  446. uint32_t mac_crc, done, kick, max_fsize;
  447. uint32_t fcs_size, ints, rxdma_cfg, rxmac_cfg, csum, coff;
  448. uint8_t smallbuf[60];
  449. struct gem_rxd desc;
  450. uint64_t dbase, baddr;
  451. unsigned int rx_cond;
  452. trace_sungem_rx_packet(size);
  453. rxmac_cfg = s->macregs[MAC_RXCFG >> 2];
  454. rxdma_cfg = s->rxdmaregs[RXDMA_CFG >> 2];
  455. max_fsize = s->macregs[MAC_MAXFSZ >> 2] & 0x7fff;
  456. /* If MAC or DMA disabled, can't receive */
  457. if (!(rxdma_cfg & RXDMA_CFG_ENABLE) ||
  458. !(rxmac_cfg & MAC_RXCFG_ENAB)) {
  459. trace_sungem_rx_disabled();
  460. return 0;
  461. }
  462. /* Size adjustment for FCS */
  463. if (rxmac_cfg & MAC_RXCFG_SFCS) {
  464. fcs_size = 0;
  465. } else {
  466. fcs_size = 4;
  467. }
  468. /* Discard frame smaller than a MAC or larger than max frame size
  469. * (when accounting for FCS)
  470. */
  471. if (size < 6 || (size + 4) > max_fsize) {
  472. trace_sungem_rx_bad_frame_size(size);
  473. /* XXX Increment error statistics ? */
  474. return size;
  475. }
  476. /* We don't drop too small frames since we get them in qemu, we pad
  477. * them instead. We should probably use the min frame size register
  478. * but I don't want to use a variable size staging buffer and I
  479. * know both MacOS and Linux use the default 64 anyway. We use 60
  480. * here to account for the non-existent FCS.
  481. */
  482. if (size < 60) {
  483. memcpy(smallbuf, buf, size);
  484. memset(&smallbuf[size], 0, 60 - size);
  485. buf = smallbuf;
  486. size = 60;
  487. }
  488. /* Get MAC crc */
  489. mac_crc = net_crc32_le(buf, ETH_ALEN);
  490. /* Packet isn't for me ? */
  491. rx_cond = sungem_check_rx_mac(s, buf, mac_crc);
  492. if (rx_cond == rx_no_match) {
  493. /* Just drop it */
  494. trace_sungem_rx_unmatched();
  495. return size;
  496. }
  497. /* Get ring pointers */
  498. kick = s->rxdmaregs[RXDMA_KICK >> 2] & s->rx_mask;
  499. done = s->rxdmaregs[RXDMA_DONE >> 2] & s->rx_mask;
  500. trace_sungem_rx_process(done, kick, s->rx_mask + 1);
  501. /* Ring full ? Can't receive */
  502. if (sungem_rx_full(s, kick, done)) {
  503. trace_sungem_rx_ringfull();
  504. return 0;
  505. }
  506. /* Note: The real GEM will fetch descriptors in blocks of 4,
  507. * for now we handle them one at a time, I think the driver will
  508. * cope
  509. */
  510. dbase = s->rxdmaregs[RXDMA_DBHI >> 2];
  511. dbase = (dbase << 32) | s->rxdmaregs[RXDMA_DBLOW >> 2];
  512. /* Read the next descriptor */
  513. pci_dma_read(d, dbase + done * sizeof(desc), &desc, sizeof(desc));
  514. trace_sungem_rx_desc(le64_to_cpu(desc.status_word),
  515. le64_to_cpu(desc.buffer));
  516. /* Effective buffer address */
  517. baddr = le64_to_cpu(desc.buffer) & ~7ull;
  518. baddr |= (rxdma_cfg & RXDMA_CFG_FBOFF) >> 10;
  519. /* Write buffer out */
  520. pci_dma_write(d, baddr, buf, size);
  521. if (fcs_size) {
  522. /* Should we add an FCS ? Linux doesn't ask us to strip it,
  523. * however I believe nothing checks it... For now we just
  524. * do nothing. It's faster this way.
  525. */
  526. }
  527. /* Calculate the checksum */
  528. coff = (rxdma_cfg & RXDMA_CFG_CSUMOFF) >> 13;
  529. csum = net_raw_checksum((uint8_t *)buf + coff, size - coff);
  530. /* Build the updated descriptor */
  531. desc.status_word = (size + fcs_size) << 16;
  532. desc.status_word |= ((uint64_t)(mac_crc >> 16)) << 44;
  533. desc.status_word |= csum;
  534. if (rx_cond == rx_match_mcast) {
  535. desc.status_word |= RXDCTRL_HPASS;
  536. }
  537. if (rx_cond == rx_match_altmac) {
  538. desc.status_word |= RXDCTRL_ALTMAC;
  539. }
  540. desc.status_word = cpu_to_le64(desc.status_word);
  541. pci_dma_write(d, dbase + done * sizeof(desc), &desc, sizeof(desc));
  542. done = (done + 1) & s->rx_mask;
  543. s->rxdmaregs[RXDMA_DONE >> 2] = done;
  544. /* XXX Unconditionally set RX interrupt for now. The interrupt
  545. * mitigation timer might well end up adding more overhead than
  546. * helping here...
  547. */
  548. ints = GREG_STAT_RXDONE;
  549. if (sungem_rx_full(s, kick, done)) {
  550. ints |= GREG_STAT_RXNOBUF;
  551. }
  552. sungem_update_status(s, ints, true);
  553. return size;
  554. }
  555. static void sungem_set_link_status(NetClientState *nc)
  556. {
  557. /* We don't do anything for now as I believe none of the OSes
  558. * drivers use the MIF autopoll feature nor the PHY interrupt
  559. */
  560. }
  561. static void sungem_update_masks(SunGEMState *s)
  562. {
  563. uint32_t sz;
  564. sz = 1 << (((s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_RINGSZ) >> 1) + 5);
  565. s->rx_mask = sz - 1;
  566. sz = 1 << (((s->txdmaregs[TXDMA_CFG >> 2] & TXDMA_CFG_RINGSZ) >> 1) + 5);
  567. s->tx_mask = sz - 1;
  568. }
  569. static void sungem_reset_rx(SunGEMState *s)
  570. {
  571. trace_sungem_rx_reset();
  572. /* XXX Do RXCFG */
  573. /* XXX Check value */
  574. s->rxdmaregs[RXDMA_FSZ >> 2] = 0x140;
  575. s->rxdmaregs[RXDMA_DONE >> 2] = 0;
  576. s->rxdmaregs[RXDMA_KICK >> 2] = 0;
  577. s->rxdmaregs[RXDMA_CFG >> 2] = 0x1000010;
  578. s->rxdmaregs[RXDMA_PTHRESH >> 2] = 0xf8;
  579. s->rxdmaregs[RXDMA_BLANK >> 2] = 0;
  580. sungem_update_masks(s);
  581. }
  582. static void sungem_reset_tx(SunGEMState *s)
  583. {
  584. trace_sungem_tx_reset();
  585. /* XXX Do TXCFG */
  586. /* XXX Check value */
  587. s->txdmaregs[TXDMA_FSZ >> 2] = 0x90;
  588. s->txdmaregs[TXDMA_TXDONE >> 2] = 0;
  589. s->txdmaregs[TXDMA_KICK >> 2] = 0;
  590. s->txdmaregs[TXDMA_CFG >> 2] = 0x118010;
  591. sungem_update_masks(s);
  592. s->tx_size = 0;
  593. s->tx_first_ctl = 0;
  594. }
  595. static void sungem_reset_all(SunGEMState *s, bool pci_reset)
  596. {
  597. trace_sungem_reset(pci_reset);
  598. sungem_reset_rx(s);
  599. sungem_reset_tx(s);
  600. s->gregs[GREG_IMASK >> 2] = 0xFFFFFFF;
  601. s->gregs[GREG_STAT >> 2] = 0;
  602. if (pci_reset) {
  603. uint8_t *ma = s->conf.macaddr.a;
  604. s->gregs[GREG_SWRST >> 2] = 0;
  605. s->macregs[MAC_ADDR0 >> 2] = (ma[4] << 8) | ma[5];
  606. s->macregs[MAC_ADDR1 >> 2] = (ma[2] << 8) | ma[3];
  607. s->macregs[MAC_ADDR2 >> 2] = (ma[0] << 8) | ma[1];
  608. } else {
  609. s->gregs[GREG_SWRST >> 2] &= GREG_SWRST_RSTOUT;
  610. }
  611. s->mifregs[MIF_CFG >> 2] = MIF_CFG_MDI0;
  612. }
  613. static void sungem_mii_write(SunGEMState *s, uint8_t phy_addr,
  614. uint8_t reg_addr, uint16_t val)
  615. {
  616. trace_sungem_mii_write(phy_addr, reg_addr, val);
  617. /* XXX TODO */
  618. }
  619. static uint16_t __sungem_mii_read(SunGEMState *s, uint8_t phy_addr,
  620. uint8_t reg_addr)
  621. {
  622. if (phy_addr != s->phy_addr) {
  623. return 0xffff;
  624. }
  625. /* Primitive emulation of a BCM5201 to please the driver,
  626. * ID is 0x00406210. TODO: Do a gigabit PHY like BCM5400
  627. */
  628. switch (reg_addr) {
  629. case MII_BMCR:
  630. return 0;
  631. case MII_PHYID1:
  632. return 0x0040;
  633. case MII_PHYID2:
  634. return 0x6210;
  635. case MII_BMSR:
  636. if (qemu_get_queue(s->nic)->link_down) {
  637. return MII_BMSR_100TX_FD | MII_BMSR_AUTONEG;
  638. } else {
  639. return MII_BMSR_100TX_FD | MII_BMSR_AN_COMP |
  640. MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
  641. }
  642. case MII_ANLPAR:
  643. case MII_ANAR:
  644. return MII_ANLPAR_TXFD;
  645. case 0x18: /* 5201 AUX status */
  646. return 3; /* 100FD */
  647. default:
  648. return 0;
  649. };
  650. }
  651. static uint16_t sungem_mii_read(SunGEMState *s, uint8_t phy_addr,
  652. uint8_t reg_addr)
  653. {
  654. uint16_t val;
  655. val = __sungem_mii_read(s, phy_addr, reg_addr);
  656. trace_sungem_mii_read(phy_addr, reg_addr, val);
  657. return val;
  658. }
  659. static uint32_t sungem_mii_op(SunGEMState *s, uint32_t val)
  660. {
  661. uint8_t phy_addr, reg_addr, op;
  662. /* Ignore not start of frame */
  663. if ((val >> 30) != 1) {
  664. trace_sungem_mii_invalid_sof(val >> 30);
  665. return 0xffff;
  666. }
  667. phy_addr = (val & MIF_FRAME_PHYAD) >> 23;
  668. reg_addr = (val & MIF_FRAME_REGAD) >> 18;
  669. op = (val & MIF_FRAME_OP) >> 28;
  670. switch (op) {
  671. case 1:
  672. sungem_mii_write(s, phy_addr, reg_addr, val & MIF_FRAME_DATA);
  673. return val | MIF_FRAME_TALSB;
  674. case 2:
  675. return sungem_mii_read(s, phy_addr, reg_addr) | MIF_FRAME_TALSB;
  676. default:
  677. trace_sungem_mii_invalid_op(op);
  678. }
  679. return 0xffff | MIF_FRAME_TALSB;
  680. }
  681. static void sungem_mmio_greg_write(void *opaque, hwaddr addr, uint64_t val,
  682. unsigned size)
  683. {
  684. SunGEMState *s = opaque;
  685. if (!(addr < 0x20) && !(addr >= 0x1000 && addr <= 0x1010)) {
  686. qemu_log_mask(LOG_GUEST_ERROR,
  687. "Write to unknown GREG register 0x%"HWADDR_PRIx"\n",
  688. addr);
  689. return;
  690. }
  691. trace_sungem_mmio_greg_write(addr, val);
  692. /* Pre-write filter */
  693. switch (addr) {
  694. /* Read only registers */
  695. case GREG_SEBSTATE:
  696. case GREG_STAT:
  697. case GREG_STAT2:
  698. case GREG_PCIESTAT:
  699. return; /* No actual write */
  700. case GREG_IACK:
  701. val &= GREG_STAT_LATCH;
  702. s->gregs[GREG_STAT >> 2] &= ~val;
  703. sungem_eval_irq(s);
  704. return; /* No actual write */
  705. case GREG_PCIEMASK:
  706. val &= 0x7;
  707. break;
  708. }
  709. s->gregs[addr >> 2] = val;
  710. /* Post write action */
  711. switch (addr) {
  712. case GREG_IMASK:
  713. /* Re-evaluate interrupt */
  714. sungem_eval_irq(s);
  715. break;
  716. case GREG_SWRST:
  717. switch (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)) {
  718. case GREG_SWRST_RXRST:
  719. sungem_reset_rx(s);
  720. break;
  721. case GREG_SWRST_TXRST:
  722. sungem_reset_tx(s);
  723. break;
  724. case GREG_SWRST_RXRST | GREG_SWRST_TXRST:
  725. sungem_reset_all(s, false);
  726. }
  727. break;
  728. }
  729. }
  730. static uint64_t sungem_mmio_greg_read(void *opaque, hwaddr addr, unsigned size)
  731. {
  732. SunGEMState *s = opaque;
  733. uint32_t val;
  734. if (!(addr < 0x20) && !(addr >= 0x1000 && addr <= 0x1010)) {
  735. qemu_log_mask(LOG_GUEST_ERROR,
  736. "Read from unknown GREG register 0x%"HWADDR_PRIx"\n",
  737. addr);
  738. return 0;
  739. }
  740. val = s->gregs[addr >> 2];
  741. trace_sungem_mmio_greg_read(addr, val);
  742. switch (addr) {
  743. case GREG_STAT:
  744. /* Side effect, clear bottom 7 bits */
  745. s->gregs[GREG_STAT >> 2] &= ~GREG_STAT_LATCH;
  746. sungem_eval_irq(s);
  747. /* Inject TX completion in returned value */
  748. val = (val & ~GREG_STAT_TXNR) |
  749. (s->txdmaregs[TXDMA_TXDONE >> 2] << GREG_STAT_TXNR_SHIFT);
  750. break;
  751. case GREG_STAT2:
  752. /* Return the status reg without side effect
  753. * (and inject TX completion in returned value)
  754. */
  755. val = (s->gregs[GREG_STAT >> 2] & ~GREG_STAT_TXNR) |
  756. (s->txdmaregs[TXDMA_TXDONE >> 2] << GREG_STAT_TXNR_SHIFT);
  757. break;
  758. }
  759. return val;
  760. }
  761. static const MemoryRegionOps sungem_mmio_greg_ops = {
  762. .read = sungem_mmio_greg_read,
  763. .write = sungem_mmio_greg_write,
  764. .endianness = DEVICE_LITTLE_ENDIAN,
  765. .impl = {
  766. .min_access_size = 4,
  767. .max_access_size = 4,
  768. },
  769. };
  770. static void sungem_mmio_txdma_write(void *opaque, hwaddr addr, uint64_t val,
  771. unsigned size)
  772. {
  773. SunGEMState *s = opaque;
  774. if (!(addr < 0x38) && !(addr >= 0x100 && addr <= 0x118)) {
  775. qemu_log_mask(LOG_GUEST_ERROR,
  776. "Write to unknown TXDMA register 0x%"HWADDR_PRIx"\n",
  777. addr);
  778. return;
  779. }
  780. trace_sungem_mmio_txdma_write(addr, val);
  781. /* Pre-write filter */
  782. switch (addr) {
  783. /* Read only registers */
  784. case TXDMA_TXDONE:
  785. case TXDMA_PCNT:
  786. case TXDMA_SMACHINE:
  787. case TXDMA_DPLOW:
  788. case TXDMA_DPHI:
  789. case TXDMA_FSZ:
  790. case TXDMA_FTAG:
  791. return; /* No actual write */
  792. }
  793. s->txdmaregs[addr >> 2] = val;
  794. /* Post write action */
  795. switch (addr) {
  796. case TXDMA_KICK:
  797. sungem_tx_kick(s);
  798. break;
  799. case TXDMA_CFG:
  800. sungem_update_masks(s);
  801. break;
  802. }
  803. }
  804. static uint64_t sungem_mmio_txdma_read(void *opaque, hwaddr addr, unsigned size)
  805. {
  806. SunGEMState *s = opaque;
  807. uint32_t val;
  808. if (!(addr < 0x38) && !(addr >= 0x100 && addr <= 0x118)) {
  809. qemu_log_mask(LOG_GUEST_ERROR,
  810. "Read from unknown TXDMA register 0x%"HWADDR_PRIx"\n",
  811. addr);
  812. return 0;
  813. }
  814. val = s->txdmaregs[addr >> 2];
  815. trace_sungem_mmio_txdma_read(addr, val);
  816. return val;
  817. }
  818. static const MemoryRegionOps sungem_mmio_txdma_ops = {
  819. .read = sungem_mmio_txdma_read,
  820. .write = sungem_mmio_txdma_write,
  821. .endianness = DEVICE_LITTLE_ENDIAN,
  822. .impl = {
  823. .min_access_size = 4,
  824. .max_access_size = 4,
  825. },
  826. };
  827. static void sungem_mmio_rxdma_write(void *opaque, hwaddr addr, uint64_t val,
  828. unsigned size)
  829. {
  830. SunGEMState *s = opaque;
  831. if (!(addr <= 0x28) && !(addr >= 0x100 && addr <= 0x120)) {
  832. qemu_log_mask(LOG_GUEST_ERROR,
  833. "Write to unknown RXDMA register 0x%"HWADDR_PRIx"\n",
  834. addr);
  835. return;
  836. }
  837. trace_sungem_mmio_rxdma_write(addr, val);
  838. /* Pre-write filter */
  839. switch (addr) {
  840. /* Read only registers */
  841. case RXDMA_DONE:
  842. case RXDMA_PCNT:
  843. case RXDMA_SMACHINE:
  844. case RXDMA_DPLOW:
  845. case RXDMA_DPHI:
  846. case RXDMA_FSZ:
  847. case RXDMA_FTAG:
  848. return; /* No actual write */
  849. }
  850. s->rxdmaregs[addr >> 2] = val;
  851. /* Post write action */
  852. switch (addr) {
  853. case RXDMA_KICK:
  854. trace_sungem_rx_kick(val);
  855. break;
  856. case RXDMA_CFG:
  857. sungem_update_masks(s);
  858. if ((s->macregs[MAC_RXCFG >> 2] & MAC_RXCFG_ENAB) != 0 &&
  859. (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) {
  860. qemu_flush_queued_packets(qemu_get_queue(s->nic));
  861. }
  862. break;
  863. }
  864. }
  865. static uint64_t sungem_mmio_rxdma_read(void *opaque, hwaddr addr, unsigned size)
  866. {
  867. SunGEMState *s = opaque;
  868. uint32_t val;
  869. if (!(addr <= 0x28) && !(addr >= 0x100 && addr <= 0x120)) {
  870. qemu_log_mask(LOG_GUEST_ERROR,
  871. "Read from unknown RXDMA register 0x%"HWADDR_PRIx"\n",
  872. addr);
  873. return 0;
  874. }
  875. val = s->rxdmaregs[addr >> 2];
  876. trace_sungem_mmio_rxdma_read(addr, val);
  877. return val;
  878. }
  879. static const MemoryRegionOps sungem_mmio_rxdma_ops = {
  880. .read = sungem_mmio_rxdma_read,
  881. .write = sungem_mmio_rxdma_write,
  882. .endianness = DEVICE_LITTLE_ENDIAN,
  883. .impl = {
  884. .min_access_size = 4,
  885. .max_access_size = 4,
  886. },
  887. };
  888. static void sungem_mmio_mac_write(void *opaque, hwaddr addr, uint64_t val,
  889. unsigned size)
  890. {
  891. SunGEMState *s = opaque;
  892. if (!(addr <= 0x134)) {
  893. qemu_log_mask(LOG_GUEST_ERROR,
  894. "Write to unknown MAC register 0x%"HWADDR_PRIx"\n",
  895. addr);
  896. return;
  897. }
  898. trace_sungem_mmio_mac_write(addr, val);
  899. /* Pre-write filter */
  900. switch (addr) {
  901. /* Read only registers */
  902. case MAC_TXRST: /* Not technically read-only but will do for now */
  903. case MAC_RXRST: /* Not technically read-only but will do for now */
  904. case MAC_TXSTAT:
  905. case MAC_RXSTAT:
  906. case MAC_CSTAT:
  907. case MAC_PATMPS:
  908. case MAC_SMACHINE:
  909. return; /* No actual write */
  910. case MAC_MINFSZ:
  911. /* 10-bits implemented */
  912. val &= 0x3ff;
  913. break;
  914. }
  915. s->macregs[addr >> 2] = val;
  916. /* Post write action */
  917. switch (addr) {
  918. case MAC_TXMASK:
  919. case MAC_RXMASK:
  920. case MAC_MCMASK:
  921. sungem_eval_cascade_irq(s);
  922. break;
  923. case MAC_RXCFG:
  924. sungem_update_masks(s);
  925. if ((s->macregs[MAC_RXCFG >> 2] & MAC_RXCFG_ENAB) != 0 &&
  926. (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) {
  927. qemu_flush_queued_packets(qemu_get_queue(s->nic));
  928. }
  929. break;
  930. }
  931. }
  932. static uint64_t sungem_mmio_mac_read(void *opaque, hwaddr addr, unsigned size)
  933. {
  934. SunGEMState *s = opaque;
  935. uint32_t val;
  936. if (!(addr <= 0x134)) {
  937. qemu_log_mask(LOG_GUEST_ERROR,
  938. "Read from unknown MAC register 0x%"HWADDR_PRIx"\n",
  939. addr);
  940. return 0;
  941. }
  942. val = s->macregs[addr >> 2];
  943. trace_sungem_mmio_mac_read(addr, val);
  944. switch (addr) {
  945. case MAC_TXSTAT:
  946. /* Side effect, clear all */
  947. s->macregs[addr >> 2] = 0;
  948. sungem_update_status(s, GREG_STAT_TXMAC, false);
  949. break;
  950. case MAC_RXSTAT:
  951. /* Side effect, clear all */
  952. s->macregs[addr >> 2] = 0;
  953. sungem_update_status(s, GREG_STAT_RXMAC, false);
  954. break;
  955. case MAC_CSTAT:
  956. /* Side effect, interrupt bits */
  957. s->macregs[addr >> 2] &= MAC_CSTAT_PTR;
  958. sungem_update_status(s, GREG_STAT_MAC, false);
  959. break;
  960. }
  961. return val;
  962. }
  963. static const MemoryRegionOps sungem_mmio_mac_ops = {
  964. .read = sungem_mmio_mac_read,
  965. .write = sungem_mmio_mac_write,
  966. .endianness = DEVICE_LITTLE_ENDIAN,
  967. .impl = {
  968. .min_access_size = 4,
  969. .max_access_size = 4,
  970. },
  971. };
  972. static void sungem_mmio_mif_write(void *opaque, hwaddr addr, uint64_t val,
  973. unsigned size)
  974. {
  975. SunGEMState *s = opaque;
  976. if (!(addr <= 0x1c)) {
  977. qemu_log_mask(LOG_GUEST_ERROR,
  978. "Write to unknown MIF register 0x%"HWADDR_PRIx"\n",
  979. addr);
  980. return;
  981. }
  982. trace_sungem_mmio_mif_write(addr, val);
  983. /* Pre-write filter */
  984. switch (addr) {
  985. /* Read only registers */
  986. case MIF_STATUS:
  987. case MIF_SMACHINE:
  988. return; /* No actual write */
  989. case MIF_CFG:
  990. /* Maintain the RO MDI bits to advertize an MDIO PHY on MDI0 */
  991. val &= ~MIF_CFG_MDI1;
  992. val |= MIF_CFG_MDI0;
  993. break;
  994. }
  995. s->mifregs[addr >> 2] = val;
  996. /* Post write action */
  997. switch (addr) {
  998. case MIF_FRAME:
  999. s->mifregs[addr >> 2] = sungem_mii_op(s, val);
  1000. break;
  1001. }
  1002. }
  1003. static uint64_t sungem_mmio_mif_read(void *opaque, hwaddr addr, unsigned size)
  1004. {
  1005. SunGEMState *s = opaque;
  1006. uint32_t val;
  1007. if (!(addr <= 0x1c)) {
  1008. qemu_log_mask(LOG_GUEST_ERROR,
  1009. "Read from unknown MIF register 0x%"HWADDR_PRIx"\n",
  1010. addr);
  1011. return 0;
  1012. }
  1013. val = s->mifregs[addr >> 2];
  1014. trace_sungem_mmio_mif_read(addr, val);
  1015. return val;
  1016. }
  1017. static const MemoryRegionOps sungem_mmio_mif_ops = {
  1018. .read = sungem_mmio_mif_read,
  1019. .write = sungem_mmio_mif_write,
  1020. .endianness = DEVICE_LITTLE_ENDIAN,
  1021. .impl = {
  1022. .min_access_size = 4,
  1023. .max_access_size = 4,
  1024. },
  1025. };
  1026. static void sungem_mmio_pcs_write(void *opaque, hwaddr addr, uint64_t val,
  1027. unsigned size)
  1028. {
  1029. SunGEMState *s = opaque;
  1030. if (!(addr <= 0x18) && !(addr >= 0x50 && addr <= 0x5c)) {
  1031. qemu_log_mask(LOG_GUEST_ERROR,
  1032. "Write to unknown PCS register 0x%"HWADDR_PRIx"\n",
  1033. addr);
  1034. return;
  1035. }
  1036. trace_sungem_mmio_pcs_write(addr, val);
  1037. /* Pre-write filter */
  1038. switch (addr) {
  1039. /* Read only registers */
  1040. case PCS_MIISTAT:
  1041. case PCS_ISTAT:
  1042. case PCS_SSTATE:
  1043. return; /* No actual write */
  1044. }
  1045. s->pcsregs[addr >> 2] = val;
  1046. }
  1047. static uint64_t sungem_mmio_pcs_read(void *opaque, hwaddr addr, unsigned size)
  1048. {
  1049. SunGEMState *s = opaque;
  1050. uint32_t val;
  1051. if (!(addr <= 0x18) && !(addr >= 0x50 && addr <= 0x5c)) {
  1052. qemu_log_mask(LOG_GUEST_ERROR,
  1053. "Read from unknown PCS register 0x%"HWADDR_PRIx"\n",
  1054. addr);
  1055. return 0;
  1056. }
  1057. val = s->pcsregs[addr >> 2];
  1058. trace_sungem_mmio_pcs_read(addr, val);
  1059. return val;
  1060. }
  1061. static const MemoryRegionOps sungem_mmio_pcs_ops = {
  1062. .read = sungem_mmio_pcs_read,
  1063. .write = sungem_mmio_pcs_write,
  1064. .endianness = DEVICE_LITTLE_ENDIAN,
  1065. .impl = {
  1066. .min_access_size = 4,
  1067. .max_access_size = 4,
  1068. },
  1069. };
  1070. static void sungem_uninit(PCIDevice *dev)
  1071. {
  1072. SunGEMState *s = SUNGEM(dev);
  1073. qemu_del_nic(s->nic);
  1074. }
  1075. static NetClientInfo net_sungem_info = {
  1076. .type = NET_CLIENT_DRIVER_NIC,
  1077. .size = sizeof(NICState),
  1078. .can_receive = sungem_can_receive,
  1079. .receive = sungem_receive,
  1080. .link_status_changed = sungem_set_link_status,
  1081. };
  1082. static void sungem_realize(PCIDevice *pci_dev, Error **errp)
  1083. {
  1084. DeviceState *dev = DEVICE(pci_dev);
  1085. SunGEMState *s = SUNGEM(pci_dev);
  1086. uint8_t *pci_conf;
  1087. pci_conf = pci_dev->config;
  1088. pci_set_word(pci_conf + PCI_STATUS,
  1089. PCI_STATUS_FAST_BACK |
  1090. PCI_STATUS_DEVSEL_MEDIUM |
  1091. PCI_STATUS_66MHZ);
  1092. pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
  1093. pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
  1094. pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
  1095. pci_conf[PCI_MIN_GNT] = 0x40;
  1096. pci_conf[PCI_MAX_LAT] = 0x40;
  1097. sungem_reset_all(s, true);
  1098. memory_region_init(&s->sungem, OBJECT(s), "sungem", SUNGEM_MMIO_SIZE);
  1099. memory_region_init_io(&s->greg, OBJECT(s), &sungem_mmio_greg_ops, s,
  1100. "sungem.greg", SUNGEM_MMIO_GREG_SIZE);
  1101. memory_region_add_subregion(&s->sungem, 0, &s->greg);
  1102. memory_region_init_io(&s->txdma, OBJECT(s), &sungem_mmio_txdma_ops, s,
  1103. "sungem.txdma", SUNGEM_MMIO_TXDMA_SIZE);
  1104. memory_region_add_subregion(&s->sungem, 0x2000, &s->txdma);
  1105. memory_region_init_io(&s->rxdma, OBJECT(s), &sungem_mmio_rxdma_ops, s,
  1106. "sungem.rxdma", SUNGEM_MMIO_RXDMA_SIZE);
  1107. memory_region_add_subregion(&s->sungem, 0x4000, &s->rxdma);
  1108. memory_region_init_io(&s->mac, OBJECT(s), &sungem_mmio_mac_ops, s,
  1109. "sungem.mac", SUNGEM_MMIO_MAC_SIZE);
  1110. memory_region_add_subregion(&s->sungem, 0x6000, &s->mac);
  1111. memory_region_init_io(&s->mif, OBJECT(s), &sungem_mmio_mif_ops, s,
  1112. "sungem.mif", SUNGEM_MMIO_MIF_SIZE);
  1113. memory_region_add_subregion(&s->sungem, 0x6200, &s->mif);
  1114. memory_region_init_io(&s->pcs, OBJECT(s), &sungem_mmio_pcs_ops, s,
  1115. "sungem.pcs", SUNGEM_MMIO_PCS_SIZE);
  1116. memory_region_add_subregion(&s->sungem, 0x9000, &s->pcs);
  1117. pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->sungem);
  1118. qemu_macaddr_default_if_unset(&s->conf.macaddr);
  1119. s->nic = qemu_new_nic(&net_sungem_info, &s->conf,
  1120. object_get_typename(OBJECT(dev)),
  1121. dev->id, s);
  1122. qemu_format_nic_info_str(qemu_get_queue(s->nic),
  1123. s->conf.macaddr.a);
  1124. }
  1125. static void sungem_reset(DeviceState *dev)
  1126. {
  1127. SunGEMState *s = SUNGEM(dev);
  1128. sungem_reset_all(s, true);
  1129. }
  1130. static void sungem_instance_init(Object *obj)
  1131. {
  1132. SunGEMState *s = SUNGEM(obj);
  1133. device_add_bootindex_property(obj, &s->conf.bootindex,
  1134. "bootindex", "/ethernet-phy@0",
  1135. DEVICE(obj), NULL);
  1136. }
  1137. static Property sungem_properties[] = {
  1138. DEFINE_NIC_PROPERTIES(SunGEMState, conf),
  1139. /* Phy address should be 0 for most Apple machines except
  1140. * for K2 in which case it's 1. Will be set by a machine
  1141. * override.
  1142. */
  1143. DEFINE_PROP_UINT32("phy_addr", SunGEMState, phy_addr, 0),
  1144. DEFINE_PROP_END_OF_LIST(),
  1145. };
  1146. static const VMStateDescription vmstate_sungem = {
  1147. .name = "sungem",
  1148. .version_id = 0,
  1149. .minimum_version_id = 0,
  1150. .fields = (VMStateField[]) {
  1151. VMSTATE_PCI_DEVICE(pdev, SunGEMState),
  1152. VMSTATE_MACADDR(conf.macaddr, SunGEMState),
  1153. VMSTATE_UINT32(phy_addr, SunGEMState),
  1154. VMSTATE_UINT32_ARRAY(gregs, SunGEMState, (SUNGEM_MMIO_GREG_SIZE >> 2)),
  1155. VMSTATE_UINT32_ARRAY(txdmaregs, SunGEMState,
  1156. (SUNGEM_MMIO_TXDMA_SIZE >> 2)),
  1157. VMSTATE_UINT32_ARRAY(rxdmaregs, SunGEMState,
  1158. (SUNGEM_MMIO_RXDMA_SIZE >> 2)),
  1159. VMSTATE_UINT32_ARRAY(macregs, SunGEMState, (SUNGEM_MMIO_MAC_SIZE >> 2)),
  1160. VMSTATE_UINT32_ARRAY(mifregs, SunGEMState, (SUNGEM_MMIO_MIF_SIZE >> 2)),
  1161. VMSTATE_UINT32_ARRAY(pcsregs, SunGEMState, (SUNGEM_MMIO_PCS_SIZE >> 2)),
  1162. VMSTATE_UINT32(rx_mask, SunGEMState),
  1163. VMSTATE_UINT32(tx_mask, SunGEMState),
  1164. VMSTATE_UINT8_ARRAY(tx_data, SunGEMState, MAX_PACKET_SIZE),
  1165. VMSTATE_UINT32(tx_size, SunGEMState),
  1166. VMSTATE_UINT64(tx_first_ctl, SunGEMState),
  1167. VMSTATE_END_OF_LIST()
  1168. }
  1169. };
  1170. static void sungem_class_init(ObjectClass *klass, void *data)
  1171. {
  1172. DeviceClass *dc = DEVICE_CLASS(klass);
  1173. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1174. k->realize = sungem_realize;
  1175. k->exit = sungem_uninit;
  1176. k->vendor_id = PCI_VENDOR_ID_APPLE;
  1177. k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_GMAC;
  1178. k->revision = 0x01;
  1179. k->class_id = PCI_CLASS_NETWORK_ETHERNET;
  1180. dc->vmsd = &vmstate_sungem;
  1181. dc->reset = sungem_reset;
  1182. dc->props = sungem_properties;
  1183. set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
  1184. }
  1185. static const TypeInfo sungem_info = {
  1186. .name = TYPE_SUNGEM,
  1187. .parent = TYPE_PCI_DEVICE,
  1188. .instance_size = sizeof(SunGEMState),
  1189. .class_init = sungem_class_init,
  1190. .instance_init = sungem_instance_init,
  1191. .interfaces = (InterfaceInfo[]) {
  1192. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1193. { }
  1194. }
  1195. };
  1196. static void sungem_register_types(void)
  1197. {
  1198. type_register_static(&sungem_info);
  1199. }
  1200. type_init(sungem_register_types)