cadence_gem.c 56 KB

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  1. /*
  2. * QEMU Cadence GEM emulation
  3. *
  4. * Copyright (c) 2011 Xilinx, Inc.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include <zlib.h> /* For crc32 */
  26. #include "hw/irq.h"
  27. #include "hw/net/cadence_gem.h"
  28. #include "hw/qdev-properties.h"
  29. #include "migration/vmstate.h"
  30. #include "qapi/error.h"
  31. #include "qemu/log.h"
  32. #include "qemu/module.h"
  33. #include "sysemu/dma.h"
  34. #include "net/checksum.h"
  35. #ifdef CADENCE_GEM_ERR_DEBUG
  36. #define DB_PRINT(...) do { \
  37. fprintf(stderr, ": %s: ", __func__); \
  38. fprintf(stderr, ## __VA_ARGS__); \
  39. } while (0)
  40. #else
  41. #define DB_PRINT(...)
  42. #endif
  43. #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
  44. #define GEM_NWCFG (0x00000004/4) /* Network Config reg */
  45. #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
  46. #define GEM_USERIO (0x0000000C/4) /* User IO reg */
  47. #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
  48. #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
  49. #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
  50. #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
  51. #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
  52. #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
  53. #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
  54. #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
  55. #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
  56. #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
  57. #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
  58. #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
  59. #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
  60. #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
  61. #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
  62. #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
  63. #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
  64. #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
  65. #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
  66. #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
  67. #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
  68. #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
  69. #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
  70. #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
  71. #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
  72. #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
  73. #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
  74. #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
  75. #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
  76. #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
  77. #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
  78. #define GEM_MODID (0x000000FC/4) /* Module ID reg */
  79. #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
  80. #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
  81. #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
  82. #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
  83. #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
  84. #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
  85. #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
  86. #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
  87. #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
  88. #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
  89. #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
  90. #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
  91. #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
  92. #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
  93. #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
  94. #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
  95. #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
  96. #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
  97. #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
  98. #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
  99. #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
  100. #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
  101. #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
  102. #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
  103. #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
  104. #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
  105. #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
  106. #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
  107. #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
  108. #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
  109. #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
  110. #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
  111. #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
  112. #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
  113. #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
  114. #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
  115. #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
  116. #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
  117. #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
  118. #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
  119. #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
  120. #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
  121. #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
  122. #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
  123. #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
  124. #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
  125. #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
  126. #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
  127. #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
  128. #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
  129. #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
  130. #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
  131. #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
  132. #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
  133. #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
  134. #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
  135. #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
  136. /* Design Configuration Registers */
  137. #define GEM_DESCONF (0x00000280/4)
  138. #define GEM_DESCONF2 (0x00000284/4)
  139. #define GEM_DESCONF3 (0x00000288/4)
  140. #define GEM_DESCONF4 (0x0000028C/4)
  141. #define GEM_DESCONF5 (0x00000290/4)
  142. #define GEM_DESCONF6 (0x00000294/4)
  143. #define GEM_DESCONF6_64B_MASK (1U << 23)
  144. #define GEM_DESCONF7 (0x00000298/4)
  145. #define GEM_INT_Q1_STATUS (0x00000400 / 4)
  146. #define GEM_INT_Q1_MASK (0x00000640 / 4)
  147. #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
  148. #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
  149. #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
  150. #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
  151. #define GEM_TBQPH (0x000004C8 / 4)
  152. #define GEM_RBQPH (0x000004D4 / 4)
  153. #define GEM_INT_Q1_ENABLE (0x00000600 / 4)
  154. #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
  155. #define GEM_INT_Q1_DISABLE (0x00000620 / 4)
  156. #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
  157. #define GEM_INT_Q1_MASK (0x00000640 / 4)
  158. #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
  159. #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
  160. #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
  161. #define GEM_ST1R_DSTC_ENABLE (1 << 28)
  162. #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
  163. #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
  164. #define GEM_ST1R_DSTC_MATCH_SHIFT (4)
  165. #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
  166. #define GEM_ST1R_QUEUE_SHIFT (0)
  167. #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
  168. #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
  169. #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
  170. #define GEM_ST2R_COMPARE_A_SHIFT (13)
  171. #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
  172. #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
  173. #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
  174. #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
  175. + 1)
  176. #define GEM_ST2R_QUEUE_SHIFT (0)
  177. #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
  178. #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
  179. #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
  180. #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
  181. #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
  182. #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
  183. #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
  184. /*****************************************/
  185. #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
  186. #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
  187. #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
  188. #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
  189. #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
  190. #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
  191. #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
  192. #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
  193. #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
  194. #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
  195. #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
  196. #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
  197. #define GEM_DMACFG_ADDR_64B (1U << 30)
  198. #define GEM_DMACFG_TX_BD_EXT (1U << 29)
  199. #define GEM_DMACFG_RX_BD_EXT (1U << 28)
  200. #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
  201. #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
  202. #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
  203. #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
  204. #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
  205. #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
  206. #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
  207. #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
  208. /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
  209. #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
  210. #define GEM_INT_TXUSED 0x00000008
  211. #define GEM_INT_RXUSED 0x00000004
  212. #define GEM_INT_RXCMPL 0x00000002
  213. #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
  214. #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
  215. #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
  216. #define GEM_PHYMNTNC_ADDR_SHFT 23
  217. #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
  218. #define GEM_PHYMNTNC_REG_SHIFT 18
  219. /* Marvell PHY definitions */
  220. #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
  221. #define PHY_REG_CONTROL 0
  222. #define PHY_REG_STATUS 1
  223. #define PHY_REG_PHYID1 2
  224. #define PHY_REG_PHYID2 3
  225. #define PHY_REG_ANEGADV 4
  226. #define PHY_REG_LINKPABIL 5
  227. #define PHY_REG_ANEGEXP 6
  228. #define PHY_REG_NEXTP 7
  229. #define PHY_REG_LINKPNEXTP 8
  230. #define PHY_REG_100BTCTRL 9
  231. #define PHY_REG_1000BTSTAT 10
  232. #define PHY_REG_EXTSTAT 15
  233. #define PHY_REG_PHYSPCFC_CTL 16
  234. #define PHY_REG_PHYSPCFC_ST 17
  235. #define PHY_REG_INT_EN 18
  236. #define PHY_REG_INT_ST 19
  237. #define PHY_REG_EXT_PHYSPCFC_CTL 20
  238. #define PHY_REG_RXERR 21
  239. #define PHY_REG_EACD 22
  240. #define PHY_REG_LED 24
  241. #define PHY_REG_LED_OVRD 25
  242. #define PHY_REG_EXT_PHYSPCFC_CTL2 26
  243. #define PHY_REG_EXT_PHYSPCFC_ST 27
  244. #define PHY_REG_CABLE_DIAG 28
  245. #define PHY_REG_CONTROL_RST 0x8000
  246. #define PHY_REG_CONTROL_LOOP 0x4000
  247. #define PHY_REG_CONTROL_ANEG 0x1000
  248. #define PHY_REG_CONTROL_ANRESTART 0x0200
  249. #define PHY_REG_STATUS_LINK 0x0004
  250. #define PHY_REG_STATUS_ANEGCMPL 0x0020
  251. #define PHY_REG_INT_ST_ANEGCMPL 0x0800
  252. #define PHY_REG_INT_ST_LINKC 0x0400
  253. #define PHY_REG_INT_ST_ENERGY 0x0010
  254. /***********************************************************************/
  255. #define GEM_RX_REJECT (-1)
  256. #define GEM_RX_PROMISCUOUS_ACCEPT (-2)
  257. #define GEM_RX_BROADCAST_ACCEPT (-3)
  258. #define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
  259. #define GEM_RX_UNICAST_HASH_ACCEPT (-5)
  260. #define GEM_RX_SAR_ACCEPT 0
  261. /***********************************************************************/
  262. #define DESC_1_USED 0x80000000
  263. #define DESC_1_LENGTH 0x00001FFF
  264. #define DESC_1_TX_WRAP 0x40000000
  265. #define DESC_1_TX_LAST 0x00008000
  266. #define DESC_0_RX_WRAP 0x00000002
  267. #define DESC_0_RX_OWNERSHIP 0x00000001
  268. #define R_DESC_1_RX_SAR_SHIFT 25
  269. #define R_DESC_1_RX_SAR_LENGTH 2
  270. #define R_DESC_1_RX_SAR_MATCH (1 << 27)
  271. #define R_DESC_1_RX_UNICAST_HASH (1 << 29)
  272. #define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
  273. #define R_DESC_1_RX_BROADCAST (1 << 31)
  274. #define DESC_1_RX_SOF 0x00004000
  275. #define DESC_1_RX_EOF 0x00008000
  276. #define GEM_MODID_VALUE 0x00020118
  277. static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
  278. {
  279. uint64_t ret = desc[0];
  280. if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
  281. ret |= (uint64_t)desc[2] << 32;
  282. }
  283. return ret;
  284. }
  285. static inline unsigned tx_desc_get_used(uint32_t *desc)
  286. {
  287. return (desc[1] & DESC_1_USED) ? 1 : 0;
  288. }
  289. static inline void tx_desc_set_used(uint32_t *desc)
  290. {
  291. desc[1] |= DESC_1_USED;
  292. }
  293. static inline unsigned tx_desc_get_wrap(uint32_t *desc)
  294. {
  295. return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
  296. }
  297. static inline unsigned tx_desc_get_last(uint32_t *desc)
  298. {
  299. return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
  300. }
  301. static inline void tx_desc_set_last(uint32_t *desc)
  302. {
  303. desc[1] |= DESC_1_TX_LAST;
  304. }
  305. static inline unsigned tx_desc_get_length(uint32_t *desc)
  306. {
  307. return desc[1] & DESC_1_LENGTH;
  308. }
  309. static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
  310. {
  311. DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
  312. DB_PRINT("bufaddr: 0x%08x\n", *desc);
  313. DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
  314. DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
  315. DB_PRINT("last: %d\n", tx_desc_get_last(desc));
  316. DB_PRINT("length: %d\n", tx_desc_get_length(desc));
  317. }
  318. static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
  319. {
  320. uint64_t ret = desc[0] & ~0x3UL;
  321. if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
  322. ret |= (uint64_t)desc[2] << 32;
  323. }
  324. return ret;
  325. }
  326. static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
  327. {
  328. int ret = 2;
  329. if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
  330. ret += 2;
  331. }
  332. if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
  333. : GEM_DMACFG_TX_BD_EXT)) {
  334. ret += 2;
  335. }
  336. assert(ret <= DESC_MAX_NUM_WORDS);
  337. return ret;
  338. }
  339. static inline unsigned rx_desc_get_wrap(uint32_t *desc)
  340. {
  341. return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
  342. }
  343. static inline unsigned rx_desc_get_ownership(uint32_t *desc)
  344. {
  345. return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
  346. }
  347. static inline void rx_desc_set_ownership(uint32_t *desc)
  348. {
  349. desc[0] |= DESC_0_RX_OWNERSHIP;
  350. }
  351. static inline void rx_desc_set_sof(uint32_t *desc)
  352. {
  353. desc[1] |= DESC_1_RX_SOF;
  354. }
  355. static inline void rx_desc_set_eof(uint32_t *desc)
  356. {
  357. desc[1] |= DESC_1_RX_EOF;
  358. }
  359. static inline void rx_desc_set_length(uint32_t *desc, unsigned len)
  360. {
  361. desc[1] &= ~DESC_1_LENGTH;
  362. desc[1] |= len;
  363. }
  364. static inline void rx_desc_set_broadcast(uint32_t *desc)
  365. {
  366. desc[1] |= R_DESC_1_RX_BROADCAST;
  367. }
  368. static inline void rx_desc_set_unicast_hash(uint32_t *desc)
  369. {
  370. desc[1] |= R_DESC_1_RX_UNICAST_HASH;
  371. }
  372. static inline void rx_desc_set_multicast_hash(uint32_t *desc)
  373. {
  374. desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
  375. }
  376. static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
  377. {
  378. desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
  379. sar_idx);
  380. desc[1] |= R_DESC_1_RX_SAR_MATCH;
  381. }
  382. /* The broadcast MAC address: 0xFFFFFFFFFFFF */
  383. static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  384. /*
  385. * gem_init_register_masks:
  386. * One time initialization.
  387. * Set masks to identify which register bits have magical clear properties
  388. */
  389. static void gem_init_register_masks(CadenceGEMState *s)
  390. {
  391. /* Mask of register bits which are read only */
  392. memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
  393. s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
  394. s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
  395. s->regs_ro[GEM_DMACFG] = 0x8E00F000;
  396. s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
  397. s->regs_ro[GEM_RXQBASE] = 0x00000003;
  398. s->regs_ro[GEM_TXQBASE] = 0x00000003;
  399. s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
  400. s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
  401. s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
  402. s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
  403. /* Mask of register bits which are clear on read */
  404. memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
  405. s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
  406. /* Mask of register bits which are write 1 to clear */
  407. memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
  408. s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
  409. s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
  410. /* Mask of register bits which are write only */
  411. memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
  412. s->regs_wo[GEM_NWCTRL] = 0x00073E60;
  413. s->regs_wo[GEM_IER] = 0x07FFFFFF;
  414. s->regs_wo[GEM_IDR] = 0x07FFFFFF;
  415. }
  416. /*
  417. * phy_update_link:
  418. * Make the emulated PHY link state match the QEMU "interface" state.
  419. */
  420. static void phy_update_link(CadenceGEMState *s)
  421. {
  422. DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
  423. /* Autonegotiation status mirrors link status. */
  424. if (qemu_get_queue(s->nic)->link_down) {
  425. s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
  426. PHY_REG_STATUS_LINK);
  427. s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
  428. } else {
  429. s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
  430. PHY_REG_STATUS_LINK);
  431. s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
  432. PHY_REG_INT_ST_ANEGCMPL |
  433. PHY_REG_INT_ST_ENERGY);
  434. }
  435. }
  436. static int gem_can_receive(NetClientState *nc)
  437. {
  438. CadenceGEMState *s;
  439. int i;
  440. s = qemu_get_nic_opaque(nc);
  441. /* Do nothing if receive is not enabled. */
  442. if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
  443. if (s->can_rx_state != 1) {
  444. s->can_rx_state = 1;
  445. DB_PRINT("can't receive - no enable\n");
  446. }
  447. return 0;
  448. }
  449. for (i = 0; i < s->num_priority_queues; i++) {
  450. if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
  451. break;
  452. }
  453. };
  454. if (i == s->num_priority_queues) {
  455. if (s->can_rx_state != 2) {
  456. s->can_rx_state = 2;
  457. DB_PRINT("can't receive - all the buffer descriptors are busy\n");
  458. }
  459. return 0;
  460. }
  461. if (s->can_rx_state != 0) {
  462. s->can_rx_state = 0;
  463. DB_PRINT("can receive\n");
  464. }
  465. return 1;
  466. }
  467. /*
  468. * gem_update_int_status:
  469. * Raise or lower interrupt based on current status.
  470. */
  471. static void gem_update_int_status(CadenceGEMState *s)
  472. {
  473. int i;
  474. if (!s->regs[GEM_ISR]) {
  475. /* ISR isn't set, clear all the interrupts */
  476. for (i = 0; i < s->num_priority_queues; ++i) {
  477. qemu_set_irq(s->irq[i], 0);
  478. }
  479. return;
  480. }
  481. /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
  482. * check it again.
  483. */
  484. if (s->num_priority_queues == 1) {
  485. /* No priority queues, just trigger the interrupt */
  486. DB_PRINT("asserting int.\n");
  487. qemu_set_irq(s->irq[0], 1);
  488. return;
  489. }
  490. for (i = 0; i < s->num_priority_queues; ++i) {
  491. if (s->regs[GEM_INT_Q1_STATUS + i]) {
  492. DB_PRINT("asserting int. (q=%d)\n", i);
  493. qemu_set_irq(s->irq[i], 1);
  494. }
  495. }
  496. }
  497. /*
  498. * gem_receive_updatestats:
  499. * Increment receive statistics.
  500. */
  501. static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
  502. unsigned bytes)
  503. {
  504. uint64_t octets;
  505. /* Total octets (bytes) received */
  506. octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
  507. s->regs[GEM_OCTRXHI];
  508. octets += bytes;
  509. s->regs[GEM_OCTRXLO] = octets >> 32;
  510. s->regs[GEM_OCTRXHI] = octets;
  511. /* Error-free Frames received */
  512. s->regs[GEM_RXCNT]++;
  513. /* Error-free Broadcast Frames counter */
  514. if (!memcmp(packet, broadcast_addr, 6)) {
  515. s->regs[GEM_RXBROADCNT]++;
  516. }
  517. /* Error-free Multicast Frames counter */
  518. if (packet[0] == 0x01) {
  519. s->regs[GEM_RXMULTICNT]++;
  520. }
  521. if (bytes <= 64) {
  522. s->regs[GEM_RX64CNT]++;
  523. } else if (bytes <= 127) {
  524. s->regs[GEM_RX65CNT]++;
  525. } else if (bytes <= 255) {
  526. s->regs[GEM_RX128CNT]++;
  527. } else if (bytes <= 511) {
  528. s->regs[GEM_RX256CNT]++;
  529. } else if (bytes <= 1023) {
  530. s->regs[GEM_RX512CNT]++;
  531. } else if (bytes <= 1518) {
  532. s->regs[GEM_RX1024CNT]++;
  533. } else {
  534. s->regs[GEM_RX1519CNT]++;
  535. }
  536. }
  537. /*
  538. * Get the MAC Address bit from the specified position
  539. */
  540. static unsigned get_bit(const uint8_t *mac, unsigned bit)
  541. {
  542. unsigned byte;
  543. byte = mac[bit / 8];
  544. byte >>= (bit & 0x7);
  545. byte &= 1;
  546. return byte;
  547. }
  548. /*
  549. * Calculate a GEM MAC Address hash index
  550. */
  551. static unsigned calc_mac_hash(const uint8_t *mac)
  552. {
  553. int index_bit, mac_bit;
  554. unsigned hash_index;
  555. hash_index = 0;
  556. mac_bit = 5;
  557. for (index_bit = 5; index_bit >= 0; index_bit--) {
  558. hash_index |= (get_bit(mac, mac_bit) ^
  559. get_bit(mac, mac_bit + 6) ^
  560. get_bit(mac, mac_bit + 12) ^
  561. get_bit(mac, mac_bit + 18) ^
  562. get_bit(mac, mac_bit + 24) ^
  563. get_bit(mac, mac_bit + 30) ^
  564. get_bit(mac, mac_bit + 36) ^
  565. get_bit(mac, mac_bit + 42)) << index_bit;
  566. mac_bit--;
  567. }
  568. return hash_index;
  569. }
  570. /*
  571. * gem_mac_address_filter:
  572. * Accept or reject this destination address?
  573. * Returns:
  574. * GEM_RX_REJECT: reject
  575. * >= 0: Specific address accept (which matched SAR is returned)
  576. * others for various other modes of accept:
  577. * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
  578. * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
  579. */
  580. static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
  581. {
  582. uint8_t *gem_spaddr;
  583. int i;
  584. /* Promiscuous mode? */
  585. if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
  586. return GEM_RX_PROMISCUOUS_ACCEPT;
  587. }
  588. if (!memcmp(packet, broadcast_addr, 6)) {
  589. /* Reject broadcast packets? */
  590. if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
  591. return GEM_RX_REJECT;
  592. }
  593. return GEM_RX_BROADCAST_ACCEPT;
  594. }
  595. /* Accept packets -w- hash match? */
  596. if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
  597. (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
  598. unsigned hash_index;
  599. hash_index = calc_mac_hash(packet);
  600. if (hash_index < 32) {
  601. if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
  602. return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
  603. GEM_RX_UNICAST_HASH_ACCEPT;
  604. }
  605. } else {
  606. hash_index -= 32;
  607. if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
  608. return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
  609. GEM_RX_UNICAST_HASH_ACCEPT;
  610. }
  611. }
  612. }
  613. /* Check all 4 specific addresses */
  614. gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
  615. for (i = 3; i >= 0; i--) {
  616. if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
  617. return GEM_RX_SAR_ACCEPT + i;
  618. }
  619. }
  620. /* No address match; reject the packet */
  621. return GEM_RX_REJECT;
  622. }
  623. /* Figure out which queue the received data should be sent to */
  624. static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
  625. unsigned rxbufsize)
  626. {
  627. uint32_t reg;
  628. bool matched, mismatched;
  629. int i, j;
  630. for (i = 0; i < s->num_type1_screeners; i++) {
  631. reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
  632. matched = false;
  633. mismatched = false;
  634. /* Screening is based on UDP Port */
  635. if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
  636. uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
  637. if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
  638. GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
  639. matched = true;
  640. } else {
  641. mismatched = true;
  642. }
  643. }
  644. /* Screening is based on DS/TC */
  645. if (reg & GEM_ST1R_DSTC_ENABLE) {
  646. uint8_t dscp = rxbuf_ptr[14 + 1];
  647. if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
  648. GEM_ST1R_DSTC_MATCH_WIDTH)) {
  649. matched = true;
  650. } else {
  651. mismatched = true;
  652. }
  653. }
  654. if (matched && !mismatched) {
  655. return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
  656. }
  657. }
  658. for (i = 0; i < s->num_type2_screeners; i++) {
  659. reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
  660. matched = false;
  661. mismatched = false;
  662. if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
  663. uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
  664. int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
  665. GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
  666. if (et_idx > s->num_type2_screeners) {
  667. qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
  668. "register index: %d\n", et_idx);
  669. }
  670. if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
  671. et_idx]) {
  672. matched = true;
  673. } else {
  674. mismatched = true;
  675. }
  676. }
  677. /* Compare A, B, C */
  678. for (j = 0; j < 3; j++) {
  679. uint32_t cr0, cr1, mask;
  680. uint16_t rx_cmp;
  681. int offset;
  682. int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
  683. GEM_ST2R_COMPARE_WIDTH);
  684. if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
  685. continue;
  686. }
  687. if (cr_idx > s->num_type2_screeners) {
  688. qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
  689. "register index: %d\n", cr_idx);
  690. }
  691. cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
  692. cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
  693. offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
  694. GEM_T2CW1_OFFSET_VALUE_WIDTH);
  695. switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
  696. GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
  697. case 3: /* Skip UDP header */
  698. qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
  699. "unimplemented - assuming UDP\n");
  700. offset += 8;
  701. /* Fallthrough */
  702. case 2: /* skip the IP header */
  703. offset += 20;
  704. /* Fallthrough */
  705. case 1: /* Count from after the ethertype */
  706. offset += 14;
  707. break;
  708. case 0:
  709. /* Offset from start of frame */
  710. break;
  711. }
  712. rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
  713. mask = extract32(cr0, 0, 16);
  714. if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
  715. matched = true;
  716. } else {
  717. mismatched = true;
  718. }
  719. }
  720. if (matched && !mismatched) {
  721. return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
  722. }
  723. }
  724. /* We made it here, assume it's queue 0 */
  725. return 0;
  726. }
  727. static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
  728. {
  729. hwaddr desc_addr = 0;
  730. if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
  731. desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
  732. }
  733. desc_addr <<= 32;
  734. desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
  735. return desc_addr;
  736. }
  737. static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q)
  738. {
  739. return gem_get_desc_addr(s, true, q);
  740. }
  741. static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q)
  742. {
  743. return gem_get_desc_addr(s, false, q);
  744. }
  745. static void gem_get_rx_desc(CadenceGEMState *s, int q)
  746. {
  747. hwaddr desc_addr = gem_get_rx_desc_addr(s, q);
  748. DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr);
  749. /* read current descriptor */
  750. address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
  751. (uint8_t *)s->rx_desc[q],
  752. sizeof(uint32_t) * gem_get_desc_len(s, true));
  753. /* Descriptor owned by software ? */
  754. if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
  755. DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
  756. s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
  757. s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
  758. /* Handle interrupt consequences */
  759. gem_update_int_status(s);
  760. }
  761. }
  762. /*
  763. * gem_receive:
  764. * Fit a packet handed to us by QEMU into the receive descriptor ring.
  765. */
  766. static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
  767. {
  768. CadenceGEMState *s;
  769. unsigned rxbufsize, bytes_to_copy;
  770. unsigned rxbuf_offset;
  771. uint8_t rxbuf[2048];
  772. uint8_t *rxbuf_ptr;
  773. bool first_desc = true;
  774. int maf;
  775. int q = 0;
  776. s = qemu_get_nic_opaque(nc);
  777. /* Is this destination MAC address "for us" ? */
  778. maf = gem_mac_address_filter(s, buf);
  779. if (maf == GEM_RX_REJECT) {
  780. return -1;
  781. }
  782. /* Discard packets with receive length error enabled ? */
  783. if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
  784. unsigned type_len;
  785. /* Fish the ethertype / length field out of the RX packet */
  786. type_len = buf[12] << 8 | buf[13];
  787. /* It is a length field, not an ethertype */
  788. if (type_len < 0x600) {
  789. if (size < type_len) {
  790. /* discard */
  791. return -1;
  792. }
  793. }
  794. }
  795. /*
  796. * Determine configured receive buffer offset (probably 0)
  797. */
  798. rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
  799. GEM_NWCFG_BUFF_OFST_S;
  800. /* The configure size of each receive buffer. Determines how many
  801. * buffers needed to hold this packet.
  802. */
  803. rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
  804. GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
  805. bytes_to_copy = size;
  806. /* Hardware allows a zero value here but warns against it. To avoid QEMU
  807. * indefinite loops we enforce a minimum value here
  808. */
  809. if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
  810. rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
  811. }
  812. /* Pad to minimum length. Assume FCS field is stripped, logic
  813. * below will increment it to the real minimum of 64 when
  814. * not FCS stripping
  815. */
  816. if (size < 60) {
  817. size = 60;
  818. }
  819. /* Strip of FCS field ? (usually yes) */
  820. if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
  821. rxbuf_ptr = (void *)buf;
  822. } else {
  823. unsigned crc_val;
  824. if (size > sizeof(rxbuf) - sizeof(crc_val)) {
  825. size = sizeof(rxbuf) - sizeof(crc_val);
  826. }
  827. bytes_to_copy = size;
  828. /* The application wants the FCS field, which QEMU does not provide.
  829. * We must try and calculate one.
  830. */
  831. memcpy(rxbuf, buf, size);
  832. memset(rxbuf + size, 0, sizeof(rxbuf) - size);
  833. rxbuf_ptr = rxbuf;
  834. crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
  835. memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
  836. bytes_to_copy += 4;
  837. size += 4;
  838. }
  839. DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
  840. /* Find which queue we are targeting */
  841. q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
  842. while (bytes_to_copy) {
  843. hwaddr desc_addr;
  844. /* Do nothing if receive is not enabled. */
  845. if (!gem_can_receive(nc)) {
  846. return -1;
  847. }
  848. DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
  849. rx_desc_get_buffer(s->rx_desc[q]));
  850. /* Copy packet data to emulated DMA buffer */
  851. address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
  852. rxbuf_offset,
  853. MEMTXATTRS_UNSPECIFIED, rxbuf_ptr,
  854. MIN(bytes_to_copy, rxbufsize));
  855. rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
  856. bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
  857. /* Update the descriptor. */
  858. if (first_desc) {
  859. rx_desc_set_sof(s->rx_desc[q]);
  860. first_desc = false;
  861. }
  862. if (bytes_to_copy == 0) {
  863. rx_desc_set_eof(s->rx_desc[q]);
  864. rx_desc_set_length(s->rx_desc[q], size);
  865. }
  866. rx_desc_set_ownership(s->rx_desc[q]);
  867. switch (maf) {
  868. case GEM_RX_PROMISCUOUS_ACCEPT:
  869. break;
  870. case GEM_RX_BROADCAST_ACCEPT:
  871. rx_desc_set_broadcast(s->rx_desc[q]);
  872. break;
  873. case GEM_RX_UNICAST_HASH_ACCEPT:
  874. rx_desc_set_unicast_hash(s->rx_desc[q]);
  875. break;
  876. case GEM_RX_MULTICAST_HASH_ACCEPT:
  877. rx_desc_set_multicast_hash(s->rx_desc[q]);
  878. break;
  879. case GEM_RX_REJECT:
  880. abort();
  881. default: /* SAR */
  882. rx_desc_set_sar(s->rx_desc[q], maf);
  883. }
  884. /* Descriptor write-back. */
  885. desc_addr = gem_get_rx_desc_addr(s, q);
  886. address_space_write(&s->dma_as, desc_addr,
  887. MEMTXATTRS_UNSPECIFIED,
  888. (uint8_t *)s->rx_desc[q],
  889. sizeof(uint32_t) * gem_get_desc_len(s, true));
  890. /* Next descriptor */
  891. if (rx_desc_get_wrap(s->rx_desc[q])) {
  892. DB_PRINT("wrapping RX descriptor list\n");
  893. s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
  894. } else {
  895. DB_PRINT("incrementing RX descriptor list\n");
  896. s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
  897. }
  898. gem_get_rx_desc(s, q);
  899. }
  900. /* Count it */
  901. gem_receive_updatestats(s, buf, size);
  902. s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
  903. s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
  904. /* Handle interrupt consequences */
  905. gem_update_int_status(s);
  906. return size;
  907. }
  908. /*
  909. * gem_transmit_updatestats:
  910. * Increment transmit statistics.
  911. */
  912. static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
  913. unsigned bytes)
  914. {
  915. uint64_t octets;
  916. /* Total octets (bytes) transmitted */
  917. octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
  918. s->regs[GEM_OCTTXHI];
  919. octets += bytes;
  920. s->regs[GEM_OCTTXLO] = octets >> 32;
  921. s->regs[GEM_OCTTXHI] = octets;
  922. /* Error-free Frames transmitted */
  923. s->regs[GEM_TXCNT]++;
  924. /* Error-free Broadcast Frames counter */
  925. if (!memcmp(packet, broadcast_addr, 6)) {
  926. s->regs[GEM_TXBCNT]++;
  927. }
  928. /* Error-free Multicast Frames counter */
  929. if (packet[0] == 0x01) {
  930. s->regs[GEM_TXMCNT]++;
  931. }
  932. if (bytes <= 64) {
  933. s->regs[GEM_TX64CNT]++;
  934. } else if (bytes <= 127) {
  935. s->regs[GEM_TX65CNT]++;
  936. } else if (bytes <= 255) {
  937. s->regs[GEM_TX128CNT]++;
  938. } else if (bytes <= 511) {
  939. s->regs[GEM_TX256CNT]++;
  940. } else if (bytes <= 1023) {
  941. s->regs[GEM_TX512CNT]++;
  942. } else if (bytes <= 1518) {
  943. s->regs[GEM_TX1024CNT]++;
  944. } else {
  945. s->regs[GEM_TX1519CNT]++;
  946. }
  947. }
  948. /*
  949. * gem_transmit:
  950. * Fish packets out of the descriptor ring and feed them to QEMU
  951. */
  952. static void gem_transmit(CadenceGEMState *s)
  953. {
  954. uint32_t desc[DESC_MAX_NUM_WORDS];
  955. hwaddr packet_desc_addr;
  956. uint8_t tx_packet[2048];
  957. uint8_t *p;
  958. unsigned total_bytes;
  959. int q = 0;
  960. /* Do nothing if transmit is not enabled. */
  961. if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
  962. return;
  963. }
  964. DB_PRINT("\n");
  965. /* The packet we will hand off to QEMU.
  966. * Packets scattered across multiple descriptors are gathered to this
  967. * one contiguous buffer first.
  968. */
  969. p = tx_packet;
  970. total_bytes = 0;
  971. for (q = s->num_priority_queues - 1; q >= 0; q--) {
  972. /* read current descriptor */
  973. packet_desc_addr = gem_get_tx_desc_addr(s, q);
  974. DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
  975. address_space_read(&s->dma_as, packet_desc_addr,
  976. MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
  977. sizeof(uint32_t) * gem_get_desc_len(s, false));
  978. /* Handle all descriptors owned by hardware */
  979. while (tx_desc_get_used(desc) == 0) {
  980. /* Do nothing if transmit is not enabled. */
  981. if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
  982. return;
  983. }
  984. print_gem_tx_desc(desc, q);
  985. /* The real hardware would eat this (and possibly crash).
  986. * For QEMU let's lend a helping hand.
  987. */
  988. if ((tx_desc_get_buffer(s, desc) == 0) ||
  989. (tx_desc_get_length(desc) == 0)) {
  990. DB_PRINT("Invalid TX descriptor @ 0x%x\n",
  991. (unsigned)packet_desc_addr);
  992. break;
  993. }
  994. if (tx_desc_get_length(desc) > sizeof(tx_packet) -
  995. (p - tx_packet)) {
  996. DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
  997. "0x%x\n", (unsigned)packet_desc_addr,
  998. (unsigned)tx_desc_get_length(desc),
  999. sizeof(tx_packet) - (p - tx_packet));
  1000. break;
  1001. }
  1002. /* Gather this fragment of the packet from "dma memory" to our
  1003. * contig buffer.
  1004. */
  1005. address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc),
  1006. MEMTXATTRS_UNSPECIFIED,
  1007. p, tx_desc_get_length(desc));
  1008. p += tx_desc_get_length(desc);
  1009. total_bytes += tx_desc_get_length(desc);
  1010. /* Last descriptor for this packet; hand the whole thing off */
  1011. if (tx_desc_get_last(desc)) {
  1012. uint32_t desc_first[DESC_MAX_NUM_WORDS];
  1013. hwaddr desc_addr = gem_get_tx_desc_addr(s, q);
  1014. /* Modify the 1st descriptor of this packet to be owned by
  1015. * the processor.
  1016. */
  1017. address_space_read(&s->dma_as, desc_addr,
  1018. MEMTXATTRS_UNSPECIFIED,
  1019. (uint8_t *)desc_first,
  1020. sizeof(desc_first));
  1021. tx_desc_set_used(desc_first);
  1022. address_space_write(&s->dma_as, desc_addr,
  1023. MEMTXATTRS_UNSPECIFIED,
  1024. (uint8_t *)desc_first,
  1025. sizeof(desc_first));
  1026. /* Advance the hardware current descriptor past this packet */
  1027. if (tx_desc_get_wrap(desc)) {
  1028. s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
  1029. } else {
  1030. s->tx_desc_addr[q] = packet_desc_addr +
  1031. 4 * gem_get_desc_len(s, false);
  1032. }
  1033. DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
  1034. s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
  1035. s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
  1036. /* Update queue interrupt status */
  1037. if (s->num_priority_queues > 1) {
  1038. s->regs[GEM_INT_Q1_STATUS + q] |=
  1039. GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
  1040. }
  1041. /* Handle interrupt consequences */
  1042. gem_update_int_status(s);
  1043. /* Is checksum offload enabled? */
  1044. if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
  1045. net_checksum_calculate(tx_packet, total_bytes);
  1046. }
  1047. /* Update MAC statistics */
  1048. gem_transmit_updatestats(s, tx_packet, total_bytes);
  1049. /* Send the packet somewhere */
  1050. if (s->phy_loop || (s->regs[GEM_NWCTRL] &
  1051. GEM_NWCTRL_LOCALLOOP)) {
  1052. gem_receive(qemu_get_queue(s->nic), tx_packet,
  1053. total_bytes);
  1054. } else {
  1055. qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
  1056. total_bytes);
  1057. }
  1058. /* Prepare for next packet */
  1059. p = tx_packet;
  1060. total_bytes = 0;
  1061. }
  1062. /* read next descriptor */
  1063. if (tx_desc_get_wrap(desc)) {
  1064. tx_desc_set_last(desc);
  1065. packet_desc_addr = s->regs[GEM_TXQBASE];
  1066. } else {
  1067. packet_desc_addr += 4 * gem_get_desc_len(s, false);
  1068. }
  1069. DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
  1070. address_space_read(&s->dma_as, packet_desc_addr,
  1071. MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
  1072. sizeof(uint32_t) * gem_get_desc_len(s, false));
  1073. }
  1074. if (tx_desc_get_used(desc)) {
  1075. s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
  1076. s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
  1077. gem_update_int_status(s);
  1078. }
  1079. }
  1080. }
  1081. static void gem_phy_reset(CadenceGEMState *s)
  1082. {
  1083. memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
  1084. s->phy_regs[PHY_REG_CONTROL] = 0x1140;
  1085. s->phy_regs[PHY_REG_STATUS] = 0x7969;
  1086. s->phy_regs[PHY_REG_PHYID1] = 0x0141;
  1087. s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
  1088. s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
  1089. s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
  1090. s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
  1091. s->phy_regs[PHY_REG_NEXTP] = 0x2001;
  1092. s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
  1093. s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
  1094. s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
  1095. s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
  1096. s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
  1097. s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
  1098. s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
  1099. s->phy_regs[PHY_REG_LED] = 0x4100;
  1100. s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
  1101. s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
  1102. phy_update_link(s);
  1103. }
  1104. static void gem_reset(DeviceState *d)
  1105. {
  1106. int i;
  1107. CadenceGEMState *s = CADENCE_GEM(d);
  1108. const uint8_t *a;
  1109. uint32_t queues_mask = 0;
  1110. DB_PRINT("\n");
  1111. /* Set post reset register values */
  1112. memset(&s->regs[0], 0, sizeof(s->regs));
  1113. s->regs[GEM_NWCFG] = 0x00080000;
  1114. s->regs[GEM_NWSTATUS] = 0x00000006;
  1115. s->regs[GEM_DMACFG] = 0x00020784;
  1116. s->regs[GEM_IMR] = 0x07ffffff;
  1117. s->regs[GEM_TXPAUSE] = 0x0000ffff;
  1118. s->regs[GEM_TXPARTIALSF] = 0x000003ff;
  1119. s->regs[GEM_RXPARTIALSF] = 0x000003ff;
  1120. s->regs[GEM_MODID] = s->revision;
  1121. s->regs[GEM_DESCONF] = 0x02500111;
  1122. s->regs[GEM_DESCONF2] = 0x2ab13fff;
  1123. s->regs[GEM_DESCONF5] = 0x002f2045;
  1124. s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
  1125. if (s->num_priority_queues > 1) {
  1126. queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
  1127. s->regs[GEM_DESCONF6] |= queues_mask;
  1128. }
  1129. /* Set MAC address */
  1130. a = &s->conf.macaddr.a[0];
  1131. s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
  1132. s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
  1133. for (i = 0; i < 4; i++) {
  1134. s->sar_active[i] = false;
  1135. }
  1136. gem_phy_reset(s);
  1137. gem_update_int_status(s);
  1138. }
  1139. static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
  1140. {
  1141. DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
  1142. return s->phy_regs[reg_num];
  1143. }
  1144. static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
  1145. {
  1146. DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
  1147. switch (reg_num) {
  1148. case PHY_REG_CONTROL:
  1149. if (val & PHY_REG_CONTROL_RST) {
  1150. /* Phy reset */
  1151. gem_phy_reset(s);
  1152. val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
  1153. s->phy_loop = 0;
  1154. }
  1155. if (val & PHY_REG_CONTROL_ANEG) {
  1156. /* Complete autonegotiation immediately */
  1157. val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
  1158. s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
  1159. }
  1160. if (val & PHY_REG_CONTROL_LOOP) {
  1161. DB_PRINT("PHY placed in loopback\n");
  1162. s->phy_loop = 1;
  1163. } else {
  1164. s->phy_loop = 0;
  1165. }
  1166. break;
  1167. }
  1168. s->phy_regs[reg_num] = val;
  1169. }
  1170. /*
  1171. * gem_read32:
  1172. * Read a GEM register.
  1173. */
  1174. static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
  1175. {
  1176. CadenceGEMState *s;
  1177. uint32_t retval;
  1178. s = (CadenceGEMState *)opaque;
  1179. offset >>= 2;
  1180. retval = s->regs[offset];
  1181. DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
  1182. switch (offset) {
  1183. case GEM_ISR:
  1184. DB_PRINT("lowering irqs on ISR read\n");
  1185. /* The interrupts get updated at the end of the function. */
  1186. break;
  1187. case GEM_PHYMNTNC:
  1188. if (retval & GEM_PHYMNTNC_OP_R) {
  1189. uint32_t phy_addr, reg_num;
  1190. phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
  1191. if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
  1192. reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
  1193. retval &= 0xFFFF0000;
  1194. retval |= gem_phy_read(s, reg_num);
  1195. } else {
  1196. retval |= 0xFFFF; /* No device at this address */
  1197. }
  1198. }
  1199. break;
  1200. }
  1201. /* Squash read to clear bits */
  1202. s->regs[offset] &= ~(s->regs_rtc[offset]);
  1203. /* Do not provide write only bits */
  1204. retval &= ~(s->regs_wo[offset]);
  1205. DB_PRINT("0x%08x\n", retval);
  1206. gem_update_int_status(s);
  1207. return retval;
  1208. }
  1209. /*
  1210. * gem_write32:
  1211. * Write a GEM register.
  1212. */
  1213. static void gem_write(void *opaque, hwaddr offset, uint64_t val,
  1214. unsigned size)
  1215. {
  1216. CadenceGEMState *s = (CadenceGEMState *)opaque;
  1217. uint32_t readonly;
  1218. int i;
  1219. DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
  1220. offset >>= 2;
  1221. /* Squash bits which are read only in write value */
  1222. val &= ~(s->regs_ro[offset]);
  1223. /* Preserve (only) bits which are read only and wtc in register */
  1224. readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
  1225. /* Copy register write to backing store */
  1226. s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
  1227. /* do w1c */
  1228. s->regs[offset] &= ~(s->regs_w1c[offset] & val);
  1229. /* Handle register write side effects */
  1230. switch (offset) {
  1231. case GEM_NWCTRL:
  1232. if (val & GEM_NWCTRL_RXENA) {
  1233. for (i = 0; i < s->num_priority_queues; ++i) {
  1234. gem_get_rx_desc(s, i);
  1235. }
  1236. }
  1237. if (val & GEM_NWCTRL_TXSTART) {
  1238. gem_transmit(s);
  1239. }
  1240. if (!(val & GEM_NWCTRL_TXENA)) {
  1241. /* Reset to start of Q when transmit disabled. */
  1242. for (i = 0; i < s->num_priority_queues; i++) {
  1243. s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
  1244. }
  1245. }
  1246. if (gem_can_receive(qemu_get_queue(s->nic))) {
  1247. qemu_flush_queued_packets(qemu_get_queue(s->nic));
  1248. }
  1249. break;
  1250. case GEM_TXSTATUS:
  1251. gem_update_int_status(s);
  1252. break;
  1253. case GEM_RXQBASE:
  1254. s->rx_desc_addr[0] = val;
  1255. break;
  1256. case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
  1257. s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
  1258. break;
  1259. case GEM_TXQBASE:
  1260. s->tx_desc_addr[0] = val;
  1261. break;
  1262. case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
  1263. s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
  1264. break;
  1265. case GEM_RXSTATUS:
  1266. gem_update_int_status(s);
  1267. break;
  1268. case GEM_IER:
  1269. s->regs[GEM_IMR] &= ~val;
  1270. gem_update_int_status(s);
  1271. break;
  1272. case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
  1273. s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
  1274. gem_update_int_status(s);
  1275. break;
  1276. case GEM_IDR:
  1277. s->regs[GEM_IMR] |= val;
  1278. gem_update_int_status(s);
  1279. break;
  1280. case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
  1281. s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
  1282. gem_update_int_status(s);
  1283. break;
  1284. case GEM_SPADDR1LO:
  1285. case GEM_SPADDR2LO:
  1286. case GEM_SPADDR3LO:
  1287. case GEM_SPADDR4LO:
  1288. s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
  1289. break;
  1290. case GEM_SPADDR1HI:
  1291. case GEM_SPADDR2HI:
  1292. case GEM_SPADDR3HI:
  1293. case GEM_SPADDR4HI:
  1294. s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
  1295. break;
  1296. case GEM_PHYMNTNC:
  1297. if (val & GEM_PHYMNTNC_OP_W) {
  1298. uint32_t phy_addr, reg_num;
  1299. phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
  1300. if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
  1301. reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
  1302. gem_phy_write(s, reg_num, val);
  1303. }
  1304. }
  1305. break;
  1306. }
  1307. DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
  1308. }
  1309. static const MemoryRegionOps gem_ops = {
  1310. .read = gem_read,
  1311. .write = gem_write,
  1312. .endianness = DEVICE_LITTLE_ENDIAN,
  1313. };
  1314. static void gem_set_link(NetClientState *nc)
  1315. {
  1316. CadenceGEMState *s = qemu_get_nic_opaque(nc);
  1317. DB_PRINT("\n");
  1318. phy_update_link(s);
  1319. gem_update_int_status(s);
  1320. }
  1321. static NetClientInfo net_gem_info = {
  1322. .type = NET_CLIENT_DRIVER_NIC,
  1323. .size = sizeof(NICState),
  1324. .can_receive = gem_can_receive,
  1325. .receive = gem_receive,
  1326. .link_status_changed = gem_set_link,
  1327. };
  1328. static void gem_realize(DeviceState *dev, Error **errp)
  1329. {
  1330. CadenceGEMState *s = CADENCE_GEM(dev);
  1331. int i;
  1332. address_space_init(&s->dma_as,
  1333. s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
  1334. if (s->num_priority_queues == 0 ||
  1335. s->num_priority_queues > MAX_PRIORITY_QUEUES) {
  1336. error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
  1337. s->num_priority_queues);
  1338. return;
  1339. } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
  1340. error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
  1341. s->num_type1_screeners);
  1342. return;
  1343. } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
  1344. error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
  1345. s->num_type2_screeners);
  1346. return;
  1347. }
  1348. for (i = 0; i < s->num_priority_queues; ++i) {
  1349. sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
  1350. }
  1351. qemu_macaddr_default_if_unset(&s->conf.macaddr);
  1352. s->nic = qemu_new_nic(&net_gem_info, &s->conf,
  1353. object_get_typename(OBJECT(dev)), dev->id, s);
  1354. }
  1355. static void gem_init(Object *obj)
  1356. {
  1357. CadenceGEMState *s = CADENCE_GEM(obj);
  1358. DeviceState *dev = DEVICE(obj);
  1359. DB_PRINT("\n");
  1360. gem_init_register_masks(s);
  1361. memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
  1362. "enet", sizeof(s->regs));
  1363. sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
  1364. object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
  1365. (Object **)&s->dma_mr,
  1366. qdev_prop_allow_set_link_before_realize,
  1367. OBJ_PROP_LINK_STRONG,
  1368. &error_abort);
  1369. }
  1370. static const VMStateDescription vmstate_cadence_gem = {
  1371. .name = "cadence_gem",
  1372. .version_id = 4,
  1373. .minimum_version_id = 4,
  1374. .fields = (VMStateField[]) {
  1375. VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
  1376. VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
  1377. VMSTATE_UINT8(phy_loop, CadenceGEMState),
  1378. VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
  1379. MAX_PRIORITY_QUEUES),
  1380. VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
  1381. MAX_PRIORITY_QUEUES),
  1382. VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
  1383. VMSTATE_END_OF_LIST(),
  1384. }
  1385. };
  1386. static Property gem_properties[] = {
  1387. DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
  1388. DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
  1389. GEM_MODID_VALUE),
  1390. DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
  1391. num_priority_queues, 1),
  1392. DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
  1393. num_type1_screeners, 4),
  1394. DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
  1395. num_type2_screeners, 4),
  1396. DEFINE_PROP_END_OF_LIST(),
  1397. };
  1398. static void gem_class_init(ObjectClass *klass, void *data)
  1399. {
  1400. DeviceClass *dc = DEVICE_CLASS(klass);
  1401. dc->realize = gem_realize;
  1402. dc->props = gem_properties;
  1403. dc->vmsd = &vmstate_cadence_gem;
  1404. dc->reset = gem_reset;
  1405. }
  1406. static const TypeInfo gem_info = {
  1407. .name = TYPE_CADENCE_GEM,
  1408. .parent = TYPE_SYS_BUS_DEVICE,
  1409. .instance_size = sizeof(CadenceGEMState),
  1410. .instance_init = gem_init,
  1411. .class_init = gem_class_init,
  1412. };
  1413. static void gem_register_types(void)
  1414. {
  1415. type_register_static(&gem_info);
  1416. }
  1417. type_init(gem_register_types)