auxbus.c 8.4 KB

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  1. /*
  2. * auxbus.c
  3. *
  4. * Copyright 2015 : GreenSocs Ltd
  5. * http://www.greensocs.com/ , email: info@greensocs.com
  6. *
  7. * Developed by :
  8. * Frederic Konrad <fred.konrad@greensocs.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation, either version 2 of the License, or
  13. * (at your option)any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, see <http://www.gnu.org/licenses/>.
  22. *
  23. */
  24. /*
  25. * This is an implementation of the AUX bus for VESA Display Port v1.1a.
  26. */
  27. #include "qemu/osdep.h"
  28. #include "qemu/units.h"
  29. #include "qemu/log.h"
  30. #include "qemu/module.h"
  31. #include "hw/misc/auxbus.h"
  32. #include "hw/i2c/i2c.h"
  33. #include "monitor/monitor.h"
  34. #include "qapi/error.h"
  35. #ifndef DEBUG_AUX
  36. #define DEBUG_AUX 0
  37. #endif
  38. #define DPRINTF(fmt, ...) do { \
  39. if (DEBUG_AUX) { \
  40. qemu_log("aux: " fmt , ## __VA_ARGS__); \
  41. } \
  42. } while (0)
  43. #define TYPE_AUXTOI2C "aux-to-i2c-bridge"
  44. #define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
  45. static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
  46. static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);
  47. /* aux-bus implementation (internal not public) */
  48. static void aux_bus_class_init(ObjectClass *klass, void *data)
  49. {
  50. BusClass *k = BUS_CLASS(klass);
  51. /* AUXSlave has an MMIO so we need to change the way we print information
  52. * in monitor.
  53. */
  54. k->print_dev = aux_slave_dev_print;
  55. }
  56. AUXBus *aux_init_bus(DeviceState *parent, const char *name)
  57. {
  58. AUXBus *bus;
  59. Object *auxtoi2c;
  60. bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
  61. auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
  62. &error_abort, NULL);
  63. qdev_set_parent_bus(DEVICE(auxtoi2c), BUS(bus));
  64. bus->bridge = AUXTOI2C(auxtoi2c);
  65. /* Memory related. */
  66. bus->aux_io = g_malloc(sizeof(*bus->aux_io));
  67. memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB);
  68. address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
  69. return bus;
  70. }
  71. void aux_map_slave(AUXSlave *aux_dev, hwaddr addr)
  72. {
  73. DeviceState *dev = DEVICE(aux_dev);
  74. AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
  75. memory_region_add_subregion(bus->aux_io, addr, aux_dev->mmio);
  76. }
  77. static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
  78. {
  79. return (dev == DEVICE(bus->bridge));
  80. }
  81. I2CBus *aux_get_i2c_bus(AUXBus *bus)
  82. {
  83. return aux_bridge_get_i2c_bus(bus->bridge);
  84. }
  85. AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
  86. uint8_t len, uint8_t *data)
  87. {
  88. AUXReply ret = AUX_NACK;
  89. I2CBus *i2c_bus = aux_get_i2c_bus(bus);
  90. size_t i;
  91. bool is_write = false;
  92. DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address,
  93. cmd, len);
  94. switch (cmd) {
  95. /*
  96. * Forward the request on the AUX bus..
  97. */
  98. case WRITE_AUX:
  99. case READ_AUX:
  100. is_write = cmd == READ_AUX ? false : true;
  101. for (i = 0; i < len; i++) {
  102. if (!address_space_rw(&bus->aux_addr_space, address++,
  103. MEMTXATTRS_UNSPECIFIED, data++, 1,
  104. is_write)) {
  105. ret = AUX_I2C_ACK;
  106. } else {
  107. ret = AUX_NACK;
  108. break;
  109. }
  110. }
  111. break;
  112. /*
  113. * Classic I2C transactions..
  114. */
  115. case READ_I2C:
  116. case WRITE_I2C:
  117. is_write = cmd == READ_I2C ? false : true;
  118. if (i2c_bus_busy(i2c_bus)) {
  119. i2c_end_transfer(i2c_bus);
  120. }
  121. if (i2c_start_transfer(i2c_bus, address, is_write)) {
  122. ret = AUX_I2C_NACK;
  123. break;
  124. }
  125. ret = AUX_I2C_ACK;
  126. while (len > 0) {
  127. if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
  128. ret = AUX_I2C_NACK;
  129. break;
  130. }
  131. len--;
  132. }
  133. i2c_end_transfer(i2c_bus);
  134. break;
  135. /*
  136. * I2C MOT transactions.
  137. *
  138. * Here we send a start when:
  139. * - We didn't start transaction yet.
  140. * - We had a READ and we do a WRITE.
  141. * - We changed the address.
  142. */
  143. case WRITE_I2C_MOT:
  144. case READ_I2C_MOT:
  145. is_write = cmd == READ_I2C_MOT ? false : true;
  146. ret = AUX_I2C_NACK;
  147. if (!i2c_bus_busy(i2c_bus)) {
  148. /*
  149. * No transactions started..
  150. */
  151. if (i2c_start_transfer(i2c_bus, address, is_write)) {
  152. break;
  153. }
  154. } else if ((address != bus->last_i2c_address) ||
  155. (bus->last_transaction != cmd)) {
  156. /*
  157. * Transaction started but we need to restart..
  158. */
  159. i2c_end_transfer(i2c_bus);
  160. if (i2c_start_transfer(i2c_bus, address, is_write)) {
  161. break;
  162. }
  163. }
  164. bus->last_transaction = cmd;
  165. bus->last_i2c_address = address;
  166. while (len > 0) {
  167. if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
  168. i2c_end_transfer(i2c_bus);
  169. break;
  170. }
  171. len--;
  172. }
  173. if (len == 0) {
  174. ret = AUX_I2C_ACK;
  175. }
  176. break;
  177. default:
  178. DPRINTF("Not implemented!\n");
  179. return AUX_NACK;
  180. }
  181. DPRINTF("reply: %u\n", ret);
  182. return ret;
  183. }
  184. static const TypeInfo aux_bus_info = {
  185. .name = TYPE_AUX_BUS,
  186. .parent = TYPE_BUS,
  187. .instance_size = sizeof(AUXBus),
  188. .class_init = aux_bus_class_init
  189. };
  190. /* aux-i2c implementation (internal not public) */
  191. struct AUXTOI2CState {
  192. /*< private >*/
  193. DeviceState parent_obj;
  194. /*< public >*/
  195. I2CBus *i2c_bus;
  196. };
  197. static void aux_bridge_class_init(ObjectClass *oc, void *data)
  198. {
  199. DeviceClass *dc = DEVICE_CLASS(oc);
  200. /* This device is private and is created only once for each
  201. * aux-bus in aux_init_bus(..). So don't allow the user to add one.
  202. */
  203. dc->user_creatable = false;
  204. }
  205. static void aux_bridge_init(Object *obj)
  206. {
  207. AUXTOI2CState *s = AUXTOI2C(obj);
  208. s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
  209. }
  210. static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge)
  211. {
  212. return bridge->i2c_bus;
  213. }
  214. static const TypeInfo aux_to_i2c_type_info = {
  215. .name = TYPE_AUXTOI2C,
  216. .parent = TYPE_DEVICE,
  217. .class_init = aux_bridge_class_init,
  218. .instance_size = sizeof(AUXTOI2CState),
  219. .instance_init = aux_bridge_init
  220. };
  221. /* aux-slave implementation */
  222. static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
  223. {
  224. AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
  225. AUXSlave *s;
  226. /* Don't print anything if the device is I2C "bridge". */
  227. if (aux_bus_is_bridge(bus, dev)) {
  228. return;
  229. }
  230. s = AUX_SLAVE(dev);
  231. monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
  232. indent, "",
  233. object_property_get_uint(OBJECT(s->mmio), "addr", NULL),
  234. memory_region_size(s->mmio));
  235. }
  236. DeviceState *aux_create_slave(AUXBus *bus, const char *type)
  237. {
  238. DeviceState *dev;
  239. dev = DEVICE(object_new(type));
  240. assert(dev);
  241. qdev_set_parent_bus(dev, &bus->qbus);
  242. return dev;
  243. }
  244. void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
  245. {
  246. assert(!aux_slave->mmio);
  247. aux_slave->mmio = mmio;
  248. }
  249. static void aux_slave_class_init(ObjectClass *klass, void *data)
  250. {
  251. DeviceClass *k = DEVICE_CLASS(klass);
  252. set_bit(DEVICE_CATEGORY_MISC, k->categories);
  253. k->bus_type = TYPE_AUX_BUS;
  254. }
  255. static const TypeInfo aux_slave_type_info = {
  256. .name = TYPE_AUX_SLAVE,
  257. .parent = TYPE_DEVICE,
  258. .instance_size = sizeof(AUXSlave),
  259. .abstract = true,
  260. .class_init = aux_slave_class_init,
  261. };
  262. static void aux_register_types(void)
  263. {
  264. type_register_static(&aux_bus_info);
  265. type_register_static(&aux_slave_type_info);
  266. type_register_static(&aux_to_i2c_type_info);
  267. }
  268. type_init(aux_register_types)