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mips_int.c 2.6 KB

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  1. /*
  2. * QEMU MIPS interrupt support
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a copy
  5. * of this software and associated documentation files (the "Software"), to deal
  6. * in the Software without restriction, including without limitation the rights
  7. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  8. * copies of the Software, and to permit persons to whom the Software is
  9. * furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20. * THE SOFTWARE.
  21. */
  22. #include "qemu/osdep.h"
  23. #include "qemu/main-loop.h"
  24. #include "hw/irq.h"
  25. #include "hw/mips/cpudevs.h"
  26. #include "cpu.h"
  27. #include "sysemu/kvm.h"
  28. #include "kvm_mips.h"
  29. static void cpu_mips_irq_request(void *opaque, int irq, int level)
  30. {
  31. MIPSCPU *cpu = opaque;
  32. CPUMIPSState *env = &cpu->env;
  33. CPUState *cs = CPU(cpu);
  34. bool locked = false;
  35. if (irq < 0 || irq > 7) {
  36. return;
  37. }
  38. /* Make sure locking works even if BQL is already held by the caller */
  39. if (!qemu_mutex_iothread_locked()) {
  40. locked = true;
  41. qemu_mutex_lock_iothread();
  42. }
  43. if (level) {
  44. env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
  45. if (kvm_enabled() && irq == 2) {
  46. kvm_mips_set_interrupt(cpu, irq, level);
  47. }
  48. } else {
  49. env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
  50. if (kvm_enabled() && irq == 2) {
  51. kvm_mips_set_interrupt(cpu, irq, level);
  52. }
  53. }
  54. if (env->CP0_Cause & CP0Ca_IP_mask) {
  55. cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  56. } else {
  57. cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  58. }
  59. if (locked) {
  60. qemu_mutex_unlock_iothread();
  61. }
  62. }
  63. void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
  64. {
  65. CPUMIPSState *env = &cpu->env;
  66. qemu_irq *qi;
  67. int i;
  68. qi = qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8);
  69. for (i = 0; i < 8; i++) {
  70. env->irq[i] = qi[i];
  71. }
  72. g_free(qi);
  73. }
  74. void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
  75. {
  76. if (irq < 0 || irq > 2) {
  77. return;
  78. }
  79. qemu_set_irq(env->irq[irq], level);
  80. }