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q800.c 14 KB

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  1. /*
  2. * QEMU Motorla 680x0 Macintosh hardware System Emulator
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a copy
  5. * of this software and associated documentation files (the "Software"), to deal
  6. * in the Software without restriction, including without limitation the rights
  7. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  8. * copies of the Software, and to permit persons to whom the Software is
  9. * furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20. * THE SOFTWARE.
  21. */
  22. #include "qemu/osdep.h"
  23. #include "qemu/units.h"
  24. #include "qemu-common.h"
  25. #include "sysemu/sysemu.h"
  26. #include "cpu.h"
  27. #include "hw/hw.h"
  28. #include "hw/boards.h"
  29. #include "hw/irq.h"
  30. #include "elf.h"
  31. #include "hw/loader.h"
  32. #include "ui/console.h"
  33. #include "exec/address-spaces.h"
  34. #include "hw/char/escc.h"
  35. #include "hw/sysbus.h"
  36. #include "hw/scsi/esp.h"
  37. #include "bootinfo.h"
  38. #include "hw/misc/mac_via.h"
  39. #include "hw/input/adb.h"
  40. #include "hw/nubus/mac-nubus-bridge.h"
  41. #include "hw/display/macfb.h"
  42. #include "hw/block/swim.h"
  43. #include "net/net.h"
  44. #include "qapi/error.h"
  45. #include "sysemu/qtest.h"
  46. #include "sysemu/runstate.h"
  47. #include "sysemu/reset.h"
  48. #define MACROM_ADDR 0x40000000
  49. #define MACROM_SIZE 0x00100000
  50. #define MACROM_FILENAME "MacROM.bin"
  51. #define Q800_MACHINE_ID 35
  52. #define Q800_CPU_ID (1 << 2)
  53. #define Q800_FPU_ID (1 << 2)
  54. #define Q800_MMU_ID (1 << 2)
  55. #define MACH_MAC 3
  56. #define Q800_MAC_CPU_ID 2
  57. #define IO_BASE 0x50000000
  58. #define IO_SLICE 0x00040000
  59. #define IO_SIZE 0x04000000
  60. #define VIA_BASE (IO_BASE + 0x00000)
  61. #define SONIC_PROM_BASE (IO_BASE + 0x08000)
  62. #define SONIC_BASE (IO_BASE + 0x0a000)
  63. #define SCC_BASE (IO_BASE + 0x0c020)
  64. #define ESP_BASE (IO_BASE + 0x10000)
  65. #define ESP_PDMA (IO_BASE + 0x10100)
  66. #define ASC_BASE (IO_BASE + 0x14000)
  67. #define SWIM_BASE (IO_BASE + 0x1E000)
  68. #define NUBUS_SUPER_SLOT_BASE 0x60000000
  69. #define NUBUS_SLOT_BASE 0xf0000000
  70. /*
  71. * the video base, whereas it a Nubus address,
  72. * is needed by the kernel to have early display and
  73. * thus provided by the bootloader
  74. */
  75. #define VIDEO_BASE 0xf9001000
  76. #define MAC_CLOCK 3686418
  77. /*
  78. * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
  79. * that performs a variety of functions (RAM management, clock generation, ...).
  80. * The GLUE chip receives interrupt requests from various devices,
  81. * assign priority to each, and asserts one or more interrupt line to the
  82. * CPU.
  83. */
  84. typedef struct {
  85. M68kCPU *cpu;
  86. uint8_t ipr;
  87. } GLUEState;
  88. static void GLUE_set_irq(void *opaque, int irq, int level)
  89. {
  90. GLUEState *s = opaque;
  91. int i;
  92. if (level) {
  93. s->ipr |= 1 << irq;
  94. } else {
  95. s->ipr &= ~(1 << irq);
  96. }
  97. for (i = 7; i >= 0; i--) {
  98. if ((s->ipr >> i) & 1) {
  99. m68k_set_irq_level(s->cpu, i + 1, i + 25);
  100. return;
  101. }
  102. }
  103. m68k_set_irq_level(s->cpu, 0, 0);
  104. }
  105. static void main_cpu_reset(void *opaque)
  106. {
  107. M68kCPU *cpu = opaque;
  108. CPUState *cs = CPU(cpu);
  109. cpu_reset(cs);
  110. cpu->env.aregs[7] = ldl_phys(cs->as, 0);
  111. cpu->env.pc = ldl_phys(cs->as, 4);
  112. }
  113. static void q800_init(MachineState *machine)
  114. {
  115. M68kCPU *cpu = NULL;
  116. int linux_boot;
  117. int32_t kernel_size;
  118. uint64_t elf_entry;
  119. char *filename;
  120. int bios_size;
  121. ram_addr_t initrd_base;
  122. int32_t initrd_size;
  123. MemoryRegion *rom;
  124. MemoryRegion *ram;
  125. MemoryRegion *io;
  126. const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1;
  127. int i;
  128. ram_addr_t ram_size = machine->ram_size;
  129. const char *kernel_filename = machine->kernel_filename;
  130. const char *initrd_filename = machine->initrd_filename;
  131. const char *kernel_cmdline = machine->kernel_cmdline;
  132. hwaddr parameters_base;
  133. CPUState *cs;
  134. DeviceState *dev;
  135. DeviceState *via_dev;
  136. SysBusESPState *sysbus_esp;
  137. ESPState *esp;
  138. SysBusDevice *sysbus;
  139. BusState *adb_bus;
  140. NubusBus *nubus;
  141. GLUEState *irq;
  142. qemu_irq *pic;
  143. linux_boot = (kernel_filename != NULL);
  144. if (ram_size > 1 * GiB) {
  145. error_report("Too much memory for this machine: %" PRId64 " MiB, "
  146. "maximum 1024 MiB", ram_size / MiB);
  147. exit(1);
  148. }
  149. /* init CPUs */
  150. cpu = M68K_CPU(cpu_create(machine->cpu_type));
  151. qemu_register_reset(main_cpu_reset, cpu);
  152. /* RAM */
  153. ram = g_malloc(sizeof(*ram));
  154. memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abort);
  155. memory_region_add_subregion(get_system_memory(), 0, ram);
  156. /*
  157. * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
  158. * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
  159. */
  160. io = g_new(MemoryRegion, io_slice_nb);
  161. for (i = 0; i < io_slice_nb; i++) {
  162. char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1);
  163. memory_region_init_alias(&io[i], NULL, name, get_system_memory(),
  164. IO_BASE, IO_SLICE);
  165. memory_region_add_subregion(get_system_memory(),
  166. IO_BASE + (i + 1) * IO_SLICE, &io[i]);
  167. g_free(name);
  168. }
  169. /* IRQ Glue */
  170. irq = g_new0(GLUEState, 1);
  171. irq->cpu = cpu;
  172. pic = qemu_allocate_irqs(GLUE_set_irq, irq, 8);
  173. /* VIA */
  174. via_dev = qdev_create(NULL, TYPE_MAC_VIA);
  175. qdev_init_nofail(via_dev);
  176. sysbus = SYS_BUS_DEVICE(via_dev);
  177. sysbus_mmio_map(sysbus, 0, VIA_BASE);
  178. qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]);
  179. qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]);
  180. adb_bus = qdev_get_child_bus(via_dev, "adb.0");
  181. dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
  182. qdev_init_nofail(dev);
  183. dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
  184. qdev_init_nofail(dev);
  185. /* MACSONIC */
  186. if (nb_nics > 1) {
  187. error_report("q800 can only have one ethernet interface");
  188. exit(1);
  189. }
  190. qemu_check_nic_model(&nd_table[0], "dp83932");
  191. /*
  192. * MacSonic driver needs an Apple MAC address
  193. * Valid prefix are:
  194. * 00:05:02 Apple
  195. * 00:80:19 Dayna Communications, Inc.
  196. * 00:A0:40 Apple
  197. * 08:00:07 Apple
  198. * (Q800 use the last one)
  199. */
  200. nd_table[0].macaddr.a[0] = 0x08;
  201. nd_table[0].macaddr.a[1] = 0x00;
  202. nd_table[0].macaddr.a[2] = 0x07;
  203. dev = qdev_create(NULL, "dp8393x");
  204. qdev_set_nic_properties(dev, &nd_table[0]);
  205. qdev_prop_set_uint8(dev, "it_shift", 2);
  206. qdev_prop_set_bit(dev, "big_endian", true);
  207. qdev_prop_set_ptr(dev, "dma_mr", get_system_memory());
  208. qdev_init_nofail(dev);
  209. sysbus = SYS_BUS_DEVICE(dev);
  210. sysbus_mmio_map(sysbus, 0, SONIC_BASE);
  211. sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE);
  212. sysbus_connect_irq(sysbus, 0, pic[2]);
  213. /* SCC */
  214. dev = qdev_create(NULL, TYPE_ESCC);
  215. qdev_prop_set_uint32(dev, "disabled", 0);
  216. qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK);
  217. qdev_prop_set_uint32(dev, "it_shift", 1);
  218. qdev_prop_set_bit(dev, "bit_swap", true);
  219. qdev_prop_set_chr(dev, "chrA", serial_hd(0));
  220. qdev_prop_set_chr(dev, "chrB", serial_hd(1));
  221. qdev_prop_set_uint32(dev, "chnBtype", 0);
  222. qdev_prop_set_uint32(dev, "chnAtype", 0);
  223. qdev_init_nofail(dev);
  224. sysbus = SYS_BUS_DEVICE(dev);
  225. sysbus_connect_irq(sysbus, 0, pic[3]);
  226. sysbus_connect_irq(sysbus, 1, pic[3]);
  227. sysbus_mmio_map(sysbus, 0, SCC_BASE);
  228. /* SCSI */
  229. dev = qdev_create(NULL, TYPE_ESP);
  230. sysbus_esp = ESP_STATE(dev);
  231. esp = &sysbus_esp->esp;
  232. esp->dma_memory_read = NULL;
  233. esp->dma_memory_write = NULL;
  234. esp->dma_opaque = NULL;
  235. sysbus_esp->it_shift = 4;
  236. esp->dma_enabled = 1;
  237. qdev_init_nofail(dev);
  238. sysbus = SYS_BUS_DEVICE(dev);
  239. sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev,
  240. "via2-irq",
  241. VIA2_IRQ_SCSI_BIT));
  242. sysbus_connect_irq(sysbus, 1,
  243. qdev_get_gpio_in_named(via_dev, "via2-irq",
  244. VIA2_IRQ_SCSI_DATA_BIT));
  245. sysbus_mmio_map(sysbus, 0, ESP_BASE);
  246. sysbus_mmio_map(sysbus, 1, ESP_PDMA);
  247. scsi_bus_legacy_handle_cmdline(&esp->bus);
  248. /* SWIM floppy controller */
  249. dev = qdev_create(NULL, TYPE_SWIM);
  250. qdev_init_nofail(dev);
  251. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
  252. /* NuBus */
  253. dev = qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE);
  254. qdev_init_nofail(dev);
  255. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE);
  256. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE);
  257. nubus = MAC_NUBUS_BRIDGE(dev)->bus;
  258. /* framebuffer in nubus slot #9 */
  259. dev = qdev_create(BUS(nubus), TYPE_NUBUS_MACFB);
  260. qdev_prop_set_uint32(dev, "width", graphic_width);
  261. qdev_prop_set_uint32(dev, "height", graphic_height);
  262. qdev_prop_set_uint8(dev, "depth", graphic_depth);
  263. qdev_init_nofail(dev);
  264. cs = CPU(cpu);
  265. if (linux_boot) {
  266. uint64_t high;
  267. kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
  268. &elf_entry, NULL, &high, 1,
  269. EM_68K, 0, 0);
  270. if (kernel_size < 0) {
  271. error_report("could not load kernel '%s'", kernel_filename);
  272. exit(1);
  273. }
  274. stl_phys(cs->as, 4, elf_entry); /* reset initial PC */
  275. parameters_base = (high + 1) & ~1;
  276. BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC);
  277. BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID);
  278. BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID);
  279. BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID);
  280. BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID);
  281. BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID);
  282. BOOTINFO1(cs->as, parameters_base,
  283. BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */
  284. BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size);
  285. BOOTINFO1(cs->as, parameters_base, BI_MAC_VADDR, VIDEO_BASE);
  286. BOOTINFO1(cs->as, parameters_base, BI_MAC_VDEPTH, graphic_depth);
  287. BOOTINFO1(cs->as, parameters_base, BI_MAC_VDIM,
  288. (graphic_height << 16) | graphic_width);
  289. BOOTINFO1(cs->as, parameters_base, BI_MAC_VROW,
  290. (graphic_width * graphic_depth + 7) / 8);
  291. BOOTINFO1(cs->as, parameters_base, BI_MAC_SCCBASE, SCC_BASE);
  292. if (kernel_cmdline) {
  293. BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE,
  294. kernel_cmdline);
  295. }
  296. /* load initrd */
  297. if (initrd_filename) {
  298. initrd_size = get_image_size(initrd_filename);
  299. if (initrd_size < 0) {
  300. error_report("could not load initial ram disk '%s'",
  301. initrd_filename);
  302. exit(1);
  303. }
  304. initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK;
  305. load_image_targphys(initrd_filename, initrd_base,
  306. ram_size - initrd_base);
  307. BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base,
  308. initrd_size);
  309. } else {
  310. initrd_base = 0;
  311. initrd_size = 0;
  312. }
  313. BOOTINFO0(cs->as, parameters_base, BI_LAST);
  314. } else {
  315. uint8_t *ptr;
  316. /* allocate and load BIOS */
  317. rom = g_malloc(sizeof(*rom));
  318. memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
  319. &error_abort);
  320. if (bios_name == NULL) {
  321. bios_name = MACROM_FILENAME;
  322. }
  323. filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  324. memory_region_set_readonly(rom, true);
  325. memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
  326. /* Load MacROM binary */
  327. if (filename) {
  328. bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE);
  329. g_free(filename);
  330. } else {
  331. bios_size = -1;
  332. }
  333. /* Remove qtest_enabled() check once firmware files are in the tree */
  334. if (!qtest_enabled()) {
  335. if (bios_size < 0 || bios_size > MACROM_SIZE) {
  336. error_report("could not load MacROM '%s'", bios_name);
  337. exit(1);
  338. }
  339. ptr = rom_ptr(MACROM_ADDR, MACROM_SIZE);
  340. stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */
  341. stl_phys(cs->as, 4,
  342. MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */
  343. }
  344. }
  345. }
  346. static void q800_machine_class_init(ObjectClass *oc, void *data)
  347. {
  348. MachineClass *mc = MACHINE_CLASS(oc);
  349. mc->desc = "Macintosh Quadra 800";
  350. mc->init = q800_init;
  351. mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
  352. mc->max_cpus = 1;
  353. mc->is_default = 0;
  354. mc->block_default_type = IF_SCSI;
  355. }
  356. static const TypeInfo q800_machine_typeinfo = {
  357. .name = MACHINE_TYPE_NAME("q800"),
  358. .parent = TYPE_MACHINE,
  359. .class_init = q800_machine_class_init,
  360. };
  361. static void q800_machine_register_types(void)
  362. {
  363. type_register_static(&q800_machine_typeinfo);
  364. }
  365. type_init(q800_machine_register_types)