2
0

ssd0303.c 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335
  1. /*
  2. * SSD0303 OLED controller with OSRAM Pictiva 96x16 display.
  3. *
  4. * Copyright (c) 2006-2007 CodeSourcery.
  5. * Written by Paul Brook
  6. *
  7. * This code is licensed under the GPL.
  8. */
  9. /* The controller can support a variety of different displays, but we only
  10. implement one. Most of the commends relating to brightness and geometry
  11. setup are ignored. */
  12. #include "qemu/osdep.h"
  13. #include "hw/i2c/i2c.h"
  14. #include "migration/vmstate.h"
  15. #include "qemu/module.h"
  16. #include "ui/console.h"
  17. //#define DEBUG_SSD0303 1
  18. #ifdef DEBUG_SSD0303
  19. #define DPRINTF(fmt, ...) \
  20. do { printf("ssd0303: " fmt , ## __VA_ARGS__); } while (0)
  21. #define BADF(fmt, ...) \
  22. do { fprintf(stderr, "ssd0303: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  23. #else
  24. #define DPRINTF(fmt, ...) do {} while(0)
  25. #define BADF(fmt, ...) \
  26. do { fprintf(stderr, "ssd0303: error: " fmt , ## __VA_ARGS__);} while (0)
  27. #endif
  28. /* Scaling factor for pixels. */
  29. #define MAGNIFY 4
  30. enum ssd0303_mode
  31. {
  32. SSD0303_IDLE,
  33. SSD0303_DATA,
  34. SSD0303_CMD
  35. };
  36. enum ssd0303_cmd {
  37. SSD0303_CMD_NONE,
  38. SSD0303_CMD_SKIP1
  39. };
  40. #define TYPE_SSD0303 "ssd0303"
  41. #define SSD0303(obj) OBJECT_CHECK(ssd0303_state, (obj), TYPE_SSD0303)
  42. typedef struct {
  43. I2CSlave parent_obj;
  44. QemuConsole *con;
  45. int row;
  46. int col;
  47. int start_line;
  48. int mirror;
  49. int flash;
  50. int enabled;
  51. int inverse;
  52. int redraw;
  53. enum ssd0303_mode mode;
  54. enum ssd0303_cmd cmd_state;
  55. uint8_t framebuffer[132*8];
  56. } ssd0303_state;
  57. static uint8_t ssd0303_recv(I2CSlave *i2c)
  58. {
  59. BADF("Reads not implemented\n");
  60. return 0xff;
  61. }
  62. static int ssd0303_send(I2CSlave *i2c, uint8_t data)
  63. {
  64. ssd0303_state *s = SSD0303(i2c);
  65. enum ssd0303_cmd old_cmd_state;
  66. switch (s->mode) {
  67. case SSD0303_IDLE:
  68. DPRINTF("byte 0x%02x\n", data);
  69. if (data == 0x80)
  70. s->mode = SSD0303_CMD;
  71. else if (data == 0x40)
  72. s->mode = SSD0303_DATA;
  73. else
  74. BADF("Unexpected byte 0x%x\n", data);
  75. break;
  76. case SSD0303_DATA:
  77. DPRINTF("data 0x%02x\n", data);
  78. if (s->col < 132) {
  79. s->framebuffer[s->col + s->row * 132] = data;
  80. s->col++;
  81. s->redraw = 1;
  82. }
  83. break;
  84. case SSD0303_CMD:
  85. old_cmd_state = s->cmd_state;
  86. s->cmd_state = SSD0303_CMD_NONE;
  87. switch (old_cmd_state) {
  88. case SSD0303_CMD_NONE:
  89. DPRINTF("cmd 0x%02x\n", data);
  90. s->mode = SSD0303_IDLE;
  91. switch (data) {
  92. case 0x00 ... 0x0f: /* Set lower column address. */
  93. s->col = (s->col & 0xf0) | (data & 0xf);
  94. break;
  95. case 0x10 ... 0x20: /* Set higher column address. */
  96. s->col = (s->col & 0x0f) | ((data & 0xf) << 4);
  97. break;
  98. case 0x40 ... 0x7f: /* Set start line. */
  99. s->start_line = 0;
  100. break;
  101. case 0x81: /* Set contrast (Ignored). */
  102. s->cmd_state = SSD0303_CMD_SKIP1;
  103. break;
  104. case 0xa0: /* Mirror off. */
  105. s->mirror = 0;
  106. break;
  107. case 0xa1: /* Mirror off. */
  108. s->mirror = 1;
  109. break;
  110. case 0xa4: /* Entire display off. */
  111. s->flash = 0;
  112. break;
  113. case 0xa5: /* Entire display on. */
  114. s->flash = 1;
  115. break;
  116. case 0xa6: /* Inverse off. */
  117. s->inverse = 0;
  118. break;
  119. case 0xa7: /* Inverse on. */
  120. s->inverse = 1;
  121. break;
  122. case 0xa8: /* Set multiplied ratio (Ignored). */
  123. s->cmd_state = SSD0303_CMD_SKIP1;
  124. break;
  125. case 0xad: /* DC-DC power control. */
  126. s->cmd_state = SSD0303_CMD_SKIP1;
  127. break;
  128. case 0xae: /* Display off. */
  129. s->enabled = 0;
  130. break;
  131. case 0xaf: /* Display on. */
  132. s->enabled = 1;
  133. break;
  134. case 0xb0 ... 0xbf: /* Set Page address. */
  135. s->row = data & 7;
  136. break;
  137. case 0xc0 ... 0xc8: /* Set COM output direction (Ignored). */
  138. break;
  139. case 0xd3: /* Set display offset (Ignored). */
  140. s->cmd_state = SSD0303_CMD_SKIP1;
  141. break;
  142. case 0xd5: /* Set display clock (Ignored). */
  143. s->cmd_state = SSD0303_CMD_SKIP1;
  144. break;
  145. case 0xd8: /* Set color and power mode (Ignored). */
  146. s->cmd_state = SSD0303_CMD_SKIP1;
  147. break;
  148. case 0xd9: /* Set pre-charge period (Ignored). */
  149. s->cmd_state = SSD0303_CMD_SKIP1;
  150. break;
  151. case 0xda: /* Set COM pin configuration (Ignored). */
  152. s->cmd_state = SSD0303_CMD_SKIP1;
  153. break;
  154. case 0xdb: /* Set VCOM dselect level (Ignored). */
  155. s->cmd_state = SSD0303_CMD_SKIP1;
  156. break;
  157. case 0xe3: /* no-op. */
  158. break;
  159. default:
  160. BADF("Unknown command: 0x%x\n", data);
  161. }
  162. break;
  163. case SSD0303_CMD_SKIP1:
  164. DPRINTF("skip 0x%02x\n", data);
  165. break;
  166. }
  167. break;
  168. }
  169. return 0;
  170. }
  171. static int ssd0303_event(I2CSlave *i2c, enum i2c_event event)
  172. {
  173. ssd0303_state *s = SSD0303(i2c);
  174. switch (event) {
  175. case I2C_FINISH:
  176. s->mode = SSD0303_IDLE;
  177. break;
  178. case I2C_START_RECV:
  179. case I2C_START_SEND:
  180. case I2C_NACK:
  181. /* Nothing to do. */
  182. break;
  183. }
  184. return 0;
  185. }
  186. static void ssd0303_update_display(void *opaque)
  187. {
  188. ssd0303_state *s = (ssd0303_state *)opaque;
  189. DisplaySurface *surface = qemu_console_surface(s->con);
  190. uint8_t *dest;
  191. uint8_t *src;
  192. int x;
  193. int y;
  194. int line;
  195. char *colors[2];
  196. char colortab[MAGNIFY * 8];
  197. int dest_width;
  198. uint8_t mask;
  199. if (!s->redraw)
  200. return;
  201. switch (surface_bits_per_pixel(surface)) {
  202. case 0:
  203. return;
  204. case 15:
  205. dest_width = 2;
  206. break;
  207. case 16:
  208. dest_width = 2;
  209. break;
  210. case 24:
  211. dest_width = 3;
  212. break;
  213. case 32:
  214. dest_width = 4;
  215. break;
  216. default:
  217. BADF("Bad color depth\n");
  218. return;
  219. }
  220. dest_width *= MAGNIFY;
  221. memset(colortab, 0xff, dest_width);
  222. memset(colortab + dest_width, 0, dest_width);
  223. if (s->flash) {
  224. colors[0] = colortab;
  225. colors[1] = colortab;
  226. } else if (s->inverse) {
  227. colors[0] = colortab;
  228. colors[1] = colortab + dest_width;
  229. } else {
  230. colors[0] = colortab + dest_width;
  231. colors[1] = colortab;
  232. }
  233. dest = surface_data(surface);
  234. for (y = 0; y < 16; y++) {
  235. line = (y + s->start_line) & 63;
  236. src = s->framebuffer + 132 * (line >> 3) + 36;
  237. mask = 1 << (line & 7);
  238. for (x = 0; x < 96; x++) {
  239. memcpy(dest, colors[(*src & mask) != 0], dest_width);
  240. dest += dest_width;
  241. src++;
  242. }
  243. for (x = 1; x < MAGNIFY; x++) {
  244. memcpy(dest, dest - dest_width * 96, dest_width * 96);
  245. dest += dest_width * 96;
  246. }
  247. }
  248. s->redraw = 0;
  249. dpy_gfx_update(s->con, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY);
  250. }
  251. static void ssd0303_invalidate_display(void * opaque)
  252. {
  253. ssd0303_state *s = (ssd0303_state *)opaque;
  254. s->redraw = 1;
  255. }
  256. static const VMStateDescription vmstate_ssd0303 = {
  257. .name = "ssd0303_oled",
  258. .version_id = 1,
  259. .minimum_version_id = 1,
  260. .fields = (VMStateField[]) {
  261. VMSTATE_INT32(row, ssd0303_state),
  262. VMSTATE_INT32(col, ssd0303_state),
  263. VMSTATE_INT32(start_line, ssd0303_state),
  264. VMSTATE_INT32(mirror, ssd0303_state),
  265. VMSTATE_INT32(flash, ssd0303_state),
  266. VMSTATE_INT32(enabled, ssd0303_state),
  267. VMSTATE_INT32(inverse, ssd0303_state),
  268. VMSTATE_INT32(redraw, ssd0303_state),
  269. VMSTATE_UINT32(mode, ssd0303_state),
  270. VMSTATE_UINT32(cmd_state, ssd0303_state),
  271. VMSTATE_BUFFER(framebuffer, ssd0303_state),
  272. VMSTATE_I2C_SLAVE(parent_obj, ssd0303_state),
  273. VMSTATE_END_OF_LIST()
  274. }
  275. };
  276. static const GraphicHwOps ssd0303_ops = {
  277. .invalidate = ssd0303_invalidate_display,
  278. .gfx_update = ssd0303_update_display,
  279. };
  280. static void ssd0303_realize(DeviceState *dev, Error **errp)
  281. {
  282. ssd0303_state *s = SSD0303(dev);
  283. s->con = graphic_console_init(dev, 0, &ssd0303_ops, s);
  284. qemu_console_resize(s->con, 96 * MAGNIFY, 16 * MAGNIFY);
  285. }
  286. static void ssd0303_class_init(ObjectClass *klass, void *data)
  287. {
  288. DeviceClass *dc = DEVICE_CLASS(klass);
  289. I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
  290. dc->realize = ssd0303_realize;
  291. k->event = ssd0303_event;
  292. k->recv = ssd0303_recv;
  293. k->send = ssd0303_send;
  294. dc->vmsd = &vmstate_ssd0303;
  295. }
  296. static const TypeInfo ssd0303_info = {
  297. .name = TYPE_SSD0303,
  298. .parent = TYPE_I2C_SLAVE,
  299. .instance_size = sizeof(ssd0303_state),
  300. .class_init = ssd0303_class_init,
  301. };
  302. static void ssd0303_register_types(void)
  303. {
  304. type_register_static(&ssd0303_info);
  305. }
  306. type_init(ssd0303_register_types)