ati_dbg.c 7.9 KB

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  1. #include "qemu/osdep.h"
  2. #include "ati_int.h"
  3. #ifdef DEBUG_ATI
  4. struct ati_regdesc {
  5. const char *name;
  6. int num;
  7. };
  8. static struct ati_regdesc ati_reg_names[] = {
  9. {"MM_INDEX", 0x0000},
  10. {"MM_DATA", 0x0004},
  11. {"CLOCK_CNTL_INDEX", 0x0008},
  12. {"CLOCK_CNTL_DATA", 0x000c},
  13. {"BIOS_0_SCRATCH", 0x0010},
  14. {"BUS_CNTL", 0x0030},
  15. {"BUS_CNTL1", 0x0034},
  16. {"GEN_INT_CNTL", 0x0040},
  17. {"GEN_INT_STATUS", 0x0044},
  18. {"CRTC_GEN_CNTL", 0x0050},
  19. {"CRTC_EXT_CNTL", 0x0054},
  20. {"DAC_CNTL", 0x0058},
  21. {"GPIO_VGA_DDC", 0x0060},
  22. {"GPIO_DVI_DDC", 0x0064},
  23. {"GPIO_MONID", 0x0068},
  24. {"I2C_CNTL_1", 0x0094},
  25. {"AMCGPIO_MASK_MIR", 0x009c},
  26. {"AMCGPIO_A_MIR", 0x00a0},
  27. {"AMCGPIO_Y_MIR", 0x00a4},
  28. {"AMCGPIO_EN_MIR", 0x00a8},
  29. {"PALETTE_INDEX", 0x00b0},
  30. {"PALETTE_DATA", 0x00b4},
  31. {"CNFG_CNTL", 0x00e0},
  32. {"GEN_RESET_CNTL", 0x00f0},
  33. {"CNFG_MEMSIZE", 0x00f8},
  34. {"CONFIG_APER_0_BASE", 0x0100},
  35. {"CONFIG_APER_1_BASE", 0x0104},
  36. {"CONFIG_APER_SIZE", 0x0108},
  37. {"CONFIG_REG_1_BASE", 0x010c},
  38. {"CONFIG_REG_APER_SIZE", 0x0110},
  39. {"MEM_CNTL", 0x0140},
  40. {"MC_FB_LOCATION", 0x0148},
  41. {"MC_AGP_LOCATION", 0x014C},
  42. {"MC_STATUS", 0x0150},
  43. {"MEM_POWER_MISC", 0x015c},
  44. {"AGP_BASE", 0x0170},
  45. {"AGP_CNTL", 0x0174},
  46. {"AGP_APER_OFFSET", 0x0178},
  47. {"PCI_GART_PAGE", 0x017c},
  48. {"PC_NGUI_MODE", 0x0180},
  49. {"PC_NGUI_CTLSTAT", 0x0184},
  50. {"MPP_TB_CONFIG", 0x01C0},
  51. {"MPP_GP_CONFIG", 0x01C8},
  52. {"VIPH_CONTROL", 0x01D0},
  53. {"CRTC_H_TOTAL_DISP", 0x0200},
  54. {"CRTC_H_SYNC_STRT_WID", 0x0204},
  55. {"CRTC_V_TOTAL_DISP", 0x0208},
  56. {"CRTC_V_SYNC_STRT_WID", 0x020c},
  57. {"CRTC_VLINE_CRNT_VLINE", 0x0210},
  58. {"CRTC_CRNT_FRAME", 0x0214},
  59. {"CRTC_GUI_TRIG_VLINE", 0x0218},
  60. {"CRTC_OFFSET", 0x0224},
  61. {"CRTC_OFFSET_CNTL", 0x0228},
  62. {"CRTC_PITCH", 0x022c},
  63. {"OVR_CLR", 0x0230},
  64. {"OVR_WID_LEFT_RIGHT", 0x0234},
  65. {"OVR_WID_TOP_BOTTOM", 0x0238},
  66. {"CUR_OFFSET", 0x0260},
  67. {"CUR_HORZ_VERT_POSN", 0x0264},
  68. {"CUR_HORZ_VERT_OFF", 0x0268},
  69. {"CUR_CLR0", 0x026c},
  70. {"CUR_CLR1", 0x0270},
  71. {"LVDS_GEN_CNTL", 0x02d0},
  72. {"DDA_CONFIG", 0x02e0},
  73. {"DDA_ON_OFF", 0x02e4},
  74. {"VGA_DDA_CONFIG", 0x02e8},
  75. {"VGA_DDA_ON_OFF", 0x02ec},
  76. {"CRTC2_H_TOTAL_DISP", 0x0300},
  77. {"CRTC2_H_SYNC_STRT_WID", 0x0304},
  78. {"CRTC2_V_TOTAL_DISP", 0x0308},
  79. {"CRTC2_V_SYNC_STRT_WID", 0x030c},
  80. {"CRTC2_VLINE_CRNT_VLINE", 0x0310},
  81. {"CRTC2_CRNT_FRAME", 0x0314},
  82. {"CRTC2_GUI_TRIG_VLINE", 0x0318},
  83. {"CRTC2_OFFSET", 0x0324},
  84. {"CRTC2_OFFSET_CNTL", 0x0328},
  85. {"CRTC2_PITCH", 0x032c},
  86. {"DDA2_CONFIG", 0x03e0},
  87. {"DDA2_ON_OFF", 0x03e4},
  88. {"CRTC2_GEN_CNTL", 0x03f8},
  89. {"CRTC2_STATUS", 0x03fc},
  90. {"OV0_SCALE_CNTL", 0x0420},
  91. {"SUBPIC_CNTL", 0x0540},
  92. {"PM4_BUFFER_OFFSET", 0x0700},
  93. {"PM4_BUFFER_CNTL", 0x0704},
  94. {"PM4_BUFFER_WM_CNTL", 0x0708},
  95. {"PM4_BUFFER_DL_RPTR_ADDR", 0x070c},
  96. {"PM4_BUFFER_DL_RPTR", 0x0710},
  97. {"PM4_BUFFER_DL_WPTR", 0x0714},
  98. {"PM4_VC_FPU_SETUP", 0x071c},
  99. {"PM4_FPU_CNTL", 0x0720},
  100. {"PM4_VC_FORMAT", 0x0724},
  101. {"PM4_VC_CNTL", 0x0728},
  102. {"PM4_VC_I01", 0x072c},
  103. {"PM4_VC_VLOFF", 0x0730},
  104. {"PM4_VC_VLSIZE", 0x0734},
  105. {"PM4_IW_INDOFF", 0x0738},
  106. {"PM4_IW_INDSIZE", 0x073c},
  107. {"PM4_FPU_FPX0", 0x0740},
  108. {"PM4_FPU_FPY0", 0x0744},
  109. {"PM4_FPU_FPX1", 0x0748},
  110. {"PM4_FPU_FPY1", 0x074c},
  111. {"PM4_FPU_FPX2", 0x0750},
  112. {"PM4_FPU_FPY2", 0x0754},
  113. {"PM4_FPU_FPY3", 0x0758},
  114. {"PM4_FPU_FPY4", 0x075c},
  115. {"PM4_FPU_FPY5", 0x0760},
  116. {"PM4_FPU_FPY6", 0x0764},
  117. {"PM4_FPU_FPR", 0x0768},
  118. {"PM4_FPU_FPG", 0x076c},
  119. {"PM4_FPU_FPB", 0x0770},
  120. {"PM4_FPU_FPA", 0x0774},
  121. {"PM4_FPU_INTXY0", 0x0780},
  122. {"PM4_FPU_INTXY1", 0x0784},
  123. {"PM4_FPU_INTXY2", 0x0788},
  124. {"PM4_FPU_INTARGB", 0x078c},
  125. {"PM4_FPU_FPTWICEAREA", 0x0790},
  126. {"PM4_FPU_DMAJOR01", 0x0794},
  127. {"PM4_FPU_DMAJOR12", 0x0798},
  128. {"PM4_FPU_DMAJOR02", 0x079c},
  129. {"PM4_FPU_STAT", 0x07a0},
  130. {"PM4_STAT", 0x07b8},
  131. {"PM4_TEST_CNTL", 0x07d0},
  132. {"PM4_MICROCODE_ADDR", 0x07d4},
  133. {"PM4_MICROCODE_RADDR", 0x07d8},
  134. {"PM4_MICROCODE_DATAH", 0x07dc},
  135. {"PM4_MICROCODE_DATAL", 0x07e0},
  136. {"PM4_CMDFIFO_ADDR", 0x07e4},
  137. {"PM4_CMDFIFO_DATAH", 0x07e8},
  138. {"PM4_CMDFIFO_DATAL", 0x07ec},
  139. {"PM4_BUFFER_ADDR", 0x07f0},
  140. {"PM4_BUFFER_DATAH", 0x07f4},
  141. {"PM4_BUFFER_DATAL", 0x07f8},
  142. {"PM4_MICRO_CNTL", 0x07fc},
  143. {"CAP0_TRIG_CNTL", 0x0950},
  144. {"CAP1_TRIG_CNTL", 0x09c0},
  145. {"RBBM_STATUS", 0x0e40},
  146. {"PM4_FIFO_DATA_EVEN", 0x1000},
  147. {"PM4_FIFO_DATA_ODD", 0x1004},
  148. {"DST_OFFSET", 0x1404},
  149. {"DST_PITCH", 0x1408},
  150. {"DST_WIDTH", 0x140c},
  151. {"DST_HEIGHT", 0x1410},
  152. {"SRC_X", 0x1414},
  153. {"SRC_Y", 0x1418},
  154. {"DST_X", 0x141c},
  155. {"DST_Y", 0x1420},
  156. {"SRC_PITCH_OFFSET", 0x1428},
  157. {"DST_PITCH_OFFSET", 0x142c},
  158. {"SRC_Y_X", 0x1434},
  159. {"DST_Y_X", 0x1438},
  160. {"DST_HEIGHT_WIDTH", 0x143c},
  161. {"DP_GUI_MASTER_CNTL", 0x146c},
  162. {"BRUSH_SCALE", 0x1470},
  163. {"BRUSH_Y_X", 0x1474},
  164. {"DP_BRUSH_BKGD_CLR", 0x1478},
  165. {"DP_BRUSH_FRGD_CLR", 0x147c},
  166. {"DST_WIDTH_X", 0x1588},
  167. {"DST_HEIGHT_WIDTH_8", 0x158c},
  168. {"SRC_X_Y", 0x1590},
  169. {"DST_X_Y", 0x1594},
  170. {"DST_WIDTH_HEIGHT", 0x1598},
  171. {"DST_WIDTH_X_INCY", 0x159c},
  172. {"DST_HEIGHT_Y", 0x15a0},
  173. {"DST_X_SUB", 0x15a4},
  174. {"DST_Y_SUB", 0x15a8},
  175. {"SRC_OFFSET", 0x15ac},
  176. {"SRC_PITCH", 0x15b0},
  177. {"DST_HEIGHT_WIDTH_BW", 0x15b4},
  178. {"CLR_CMP_CNTL", 0x15c0},
  179. {"CLR_CMP_CLR_SRC", 0x15c4},
  180. {"CLR_CMP_CLR_DST", 0x15c8},
  181. {"CLR_CMP_MASK", 0x15cc},
  182. {"DP_SRC_FRGD_CLR", 0x15d8},
  183. {"DP_SRC_BKGD_CLR", 0x15dc},
  184. {"DST_BRES_ERR", 0x1628},
  185. {"DST_BRES_INC", 0x162c},
  186. {"DST_BRES_DEC", 0x1630},
  187. {"DST_BRES_LNTH", 0x1634},
  188. {"DST_BRES_LNTH_SUB", 0x1638},
  189. {"SC_LEFT", 0x1640},
  190. {"SC_RIGHT", 0x1644},
  191. {"SC_TOP", 0x1648},
  192. {"SC_BOTTOM", 0x164c},
  193. {"SRC_SC_RIGHT", 0x1654},
  194. {"SRC_SC_BOTTOM", 0x165c},
  195. {"GUI_DEBUG0", 0x16a0},
  196. {"GUI_DEBUG1", 0x16a4},
  197. {"GUI_TIMEOUT", 0x16b0},
  198. {"GUI_TIMEOUT0", 0x16b4},
  199. {"GUI_TIMEOUT1", 0x16b8},
  200. {"GUI_PROBE", 0x16bc},
  201. {"DP_CNTL", 0x16c0},
  202. {"DP_DATATYPE", 0x16c4},
  203. {"DP_MIX", 0x16c8},
  204. {"DP_WRITE_MASK", 0x16cc},
  205. {"DP_CNTL_XDIR_YDIR_YMAJOR", 0x16d0},
  206. {"DEFAULT_OFFSET", 0x16e0},
  207. {"DEFAULT_PITCH", 0x16e4},
  208. {"DEFAULT_SC_BOTTOM_RIGHT", 0x16e8},
  209. {"SC_TOP_LEFT", 0x16ec},
  210. {"SC_BOTTOM_RIGHT", 0x16f0},
  211. {"SRC_SC_BOTTOM_RIGHT", 0x16f4},
  212. {"DST_TILE", 0x1700},
  213. {"WAIT_UNTIL", 0x1720},
  214. {"CACHE_CNTL", 0x1724},
  215. {"GUI_STAT", 0x1740},
  216. {"PC_GUI_MODE", 0x1744},
  217. {"PC_GUI_CTLSTAT", 0x1748},
  218. {"PC_DEBUG_MODE", 0x1760},
  219. {"BRES_DST_ERR_DEC", 0x1780},
  220. {"TRAIL_BRES_T12_ERR_DEC", 0x1784},
  221. {"TRAIL_BRES_T12_INC", 0x1788},
  222. {"DP_T12_CNTL", 0x178c},
  223. {"DST_BRES_T1_LNTH", 0x1790},
  224. {"DST_BRES_T2_LNTH", 0x1794},
  225. {"SCALE_SRC_HEIGHT_WIDTH", 0x1994},
  226. {"SCALE_OFFSET_0", 0x1998},
  227. {"SCALE_PITCH", 0x199c},
  228. {"SCALE_X_INC", 0x19a0},
  229. {"SCALE_Y_INC", 0x19a4},
  230. {"SCALE_HACC", 0x19a8},
  231. {"SCALE_VACC", 0x19ac},
  232. {"SCALE_DST_X_Y", 0x19b0},
  233. {"SCALE_DST_HEIGHT_WIDTH", 0x19b4},
  234. {"SCALE_3D_CNTL", 0x1a00},
  235. {"SCALE_3D_DATATYPE", 0x1a20},
  236. {"SETUP_CNTL", 0x1bc4},
  237. {"SOLID_COLOR", 0x1bc8},
  238. {"WINDOW_XY_OFFSET", 0x1bcc},
  239. {"DRAW_LINE_POINT", 0x1bd0},
  240. {"SETUP_CNTL_PM4", 0x1bd4},
  241. {"DST_PITCH_OFFSET_C", 0x1c80},
  242. {"DP_GUI_MASTER_CNTL_C", 0x1c84},
  243. {"SC_TOP_LEFT_C", 0x1c88},
  244. {"SC_BOTTOM_RIGHT_C", 0x1c8c},
  245. {"CLR_CMP_MASK_3D", 0x1A28},
  246. {"MISC_3D_STATE_CNTL_REG", 0x1CA0},
  247. {"MC_SRC1_CNTL", 0x19D8},
  248. {"TEX_CNTL", 0x1800},
  249. {"RAGE128_MPP_TB_CONFIG", 0x01c0},
  250. {NULL, -1}
  251. };
  252. const char *ati_reg_name(int num)
  253. {
  254. int i;
  255. num &= ~3;
  256. for (i = 0; ati_reg_names[i].name; i++) {
  257. if (ati_reg_names[i].num == num) {
  258. return ati_reg_names[i].name;
  259. }
  260. }
  261. return "unknown";
  262. }
  263. #else
  264. const char *ati_reg_name(int num)
  265. {
  266. return "";
  267. }
  268. #endif