serial-pci-multi.c 7.0 KB

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  1. /*
  2. * QEMU 16550A multi UART emulation
  3. *
  4. * SPDX-License-Identifier: MIT
  5. *
  6. * Copyright (c) 2003-2004 Fabrice Bellard
  7. * Copyright (c) 2008 Citrix Systems, Inc.
  8. *
  9. * Permission is hereby granted, free of charge, to any person obtaining a copy
  10. * of this software and associated documentation files (the "Software"), to deal
  11. * in the Software without restriction, including without limitation the rights
  12. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13. * copies of the Software, and to permit persons to whom the Software is
  14. * furnished to do so, subject to the following conditions:
  15. *
  16. * The above copyright notice and this permission notice shall be included in
  17. * all copies or substantial portions of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25. * THE SOFTWARE.
  26. */
  27. /* see docs/specs/pci-serial.txt */
  28. #include "qemu/osdep.h"
  29. #include "qapi/error.h"
  30. #include "hw/char/serial.h"
  31. #include "hw/irq.h"
  32. #include "hw/pci/pci.h"
  33. #include "hw/qdev-properties.h"
  34. #include "migration/vmstate.h"
  35. #define PCI_SERIAL_MAX_PORTS 4
  36. typedef struct PCIMultiSerialState {
  37. PCIDevice dev;
  38. MemoryRegion iobar;
  39. uint32_t ports;
  40. char *name[PCI_SERIAL_MAX_PORTS];
  41. SerialState state[PCI_SERIAL_MAX_PORTS];
  42. uint32_t level[PCI_SERIAL_MAX_PORTS];
  43. qemu_irq *irqs;
  44. uint8_t prog_if;
  45. } PCIMultiSerialState;
  46. static void multi_serial_pci_exit(PCIDevice *dev)
  47. {
  48. PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
  49. SerialState *s;
  50. int i;
  51. for (i = 0; i < pci->ports; i++) {
  52. s = pci->state + i;
  53. serial_exit_core(s);
  54. memory_region_del_subregion(&pci->iobar, &s->io);
  55. g_free(pci->name[i]);
  56. }
  57. qemu_free_irqs(pci->irqs, pci->ports);
  58. }
  59. static void multi_serial_irq_mux(void *opaque, int n, int level)
  60. {
  61. PCIMultiSerialState *pci = opaque;
  62. int i, pending = 0;
  63. pci->level[n] = level;
  64. for (i = 0; i < pci->ports; i++) {
  65. if (pci->level[i]) {
  66. pending = 1;
  67. }
  68. }
  69. pci_set_irq(&pci->dev, pending);
  70. }
  71. static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
  72. {
  73. PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
  74. PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
  75. SerialState *s;
  76. Error *err = NULL;
  77. int i, nr_ports = 0;
  78. switch (pc->device_id) {
  79. case 0x0003:
  80. nr_ports = 2;
  81. break;
  82. case 0x0004:
  83. nr_ports = 4;
  84. break;
  85. }
  86. assert(nr_ports > 0);
  87. assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
  88. pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
  89. pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
  90. memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
  91. pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
  92. pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
  93. nr_ports);
  94. for (i = 0; i < nr_ports; i++) {
  95. s = pci->state + i;
  96. s->baudbase = 115200;
  97. serial_realize_core(s, &err);
  98. if (err != NULL) {
  99. error_propagate(errp, err);
  100. multi_serial_pci_exit(dev);
  101. return;
  102. }
  103. s->irq = pci->irqs[i];
  104. pci->name[i] = g_strdup_printf("uart #%d", i + 1);
  105. memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
  106. pci->name[i], 8);
  107. memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
  108. pci->ports++;
  109. }
  110. }
  111. static const VMStateDescription vmstate_pci_multi_serial = {
  112. .name = "pci-serial-multi",
  113. .version_id = 1,
  114. .minimum_version_id = 1,
  115. .fields = (VMStateField[]) {
  116. VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
  117. VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
  118. 0, vmstate_serial, SerialState),
  119. VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
  120. VMSTATE_END_OF_LIST()
  121. }
  122. };
  123. static Property multi_2x_serial_pci_properties[] = {
  124. DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
  125. DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
  126. DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
  127. DEFINE_PROP_END_OF_LIST(),
  128. };
  129. static Property multi_4x_serial_pci_properties[] = {
  130. DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
  131. DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
  132. DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
  133. DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
  134. DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
  135. DEFINE_PROP_END_OF_LIST(),
  136. };
  137. static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
  138. {
  139. DeviceClass *dc = DEVICE_CLASS(klass);
  140. PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
  141. pc->realize = multi_serial_pci_realize;
  142. pc->exit = multi_serial_pci_exit;
  143. pc->vendor_id = PCI_VENDOR_ID_REDHAT;
  144. pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
  145. pc->revision = 1;
  146. pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
  147. dc->vmsd = &vmstate_pci_multi_serial;
  148. dc->props = multi_2x_serial_pci_properties;
  149. set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
  150. }
  151. static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
  152. {
  153. DeviceClass *dc = DEVICE_CLASS(klass);
  154. PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
  155. pc->realize = multi_serial_pci_realize;
  156. pc->exit = multi_serial_pci_exit;
  157. pc->vendor_id = PCI_VENDOR_ID_REDHAT;
  158. pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
  159. pc->revision = 1;
  160. pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
  161. dc->vmsd = &vmstate_pci_multi_serial;
  162. dc->props = multi_4x_serial_pci_properties;
  163. set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
  164. }
  165. static const TypeInfo multi_2x_serial_pci_info = {
  166. .name = "pci-serial-2x",
  167. .parent = TYPE_PCI_DEVICE,
  168. .instance_size = sizeof(PCIMultiSerialState),
  169. .class_init = multi_2x_serial_pci_class_initfn,
  170. .interfaces = (InterfaceInfo[]) {
  171. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  172. { },
  173. },
  174. };
  175. static const TypeInfo multi_4x_serial_pci_info = {
  176. .name = "pci-serial-4x",
  177. .parent = TYPE_PCI_DEVICE,
  178. .instance_size = sizeof(PCIMultiSerialState),
  179. .class_init = multi_4x_serial_pci_class_initfn,
  180. .interfaces = (InterfaceInfo[]) {
  181. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  182. { },
  183. },
  184. };
  185. static void multi_serial_pci_register_types(void)
  186. {
  187. type_register_static(&multi_2x_serial_pci_info);
  188. type_register_static(&multi_4x_serial_pci_info);
  189. }
  190. type_init(multi_serial_pci_register_types)