ac97.c 39 KB

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  1. /*
  2. * Copyright (C) 2006 InnoTek Systemberatung GmbH
  3. *
  4. * This file is part of VirtualBox Open Source Edition (OSE), as
  5. * available from http://www.virtualbox.org. This file is free software;
  6. * you can redistribute it and/or modify it under the terms of the GNU
  7. * General Public License as published by the Free Software Foundation,
  8. * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
  9. * distribution. VirtualBox OSE is distributed in the hope that it will
  10. * be useful, but WITHOUT ANY WARRANTY of any kind.
  11. *
  12. * If you received this file as part of a commercial VirtualBox
  13. * distribution, then only the terms of your commercial VirtualBox
  14. * license agreement apply instead of the previous paragraph.
  15. *
  16. * Contributions after 2012-01-13 are licensed under the terms of the
  17. * GNU GPL, version 2 or (at your option) any later version.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "hw/audio/soundhw.h"
  21. #include "audio/audio.h"
  22. #include "hw/pci/pci.h"
  23. #include "hw/qdev-properties.h"
  24. #include "migration/vmstate.h"
  25. #include "qemu/module.h"
  26. #include "sysemu/dma.h"
  27. enum {
  28. AC97_Reset = 0x00,
  29. AC97_Master_Volume_Mute = 0x02,
  30. AC97_Headphone_Volume_Mute = 0x04,
  31. AC97_Master_Volume_Mono_Mute = 0x06,
  32. AC97_Master_Tone_RL = 0x08,
  33. AC97_PC_BEEP_Volume_Mute = 0x0A,
  34. AC97_Phone_Volume_Mute = 0x0C,
  35. AC97_Mic_Volume_Mute = 0x0E,
  36. AC97_Line_In_Volume_Mute = 0x10,
  37. AC97_CD_Volume_Mute = 0x12,
  38. AC97_Video_Volume_Mute = 0x14,
  39. AC97_Aux_Volume_Mute = 0x16,
  40. AC97_PCM_Out_Volume_Mute = 0x18,
  41. AC97_Record_Select = 0x1A,
  42. AC97_Record_Gain_Mute = 0x1C,
  43. AC97_Record_Gain_Mic_Mute = 0x1E,
  44. AC97_General_Purpose = 0x20,
  45. AC97_3D_Control = 0x22,
  46. AC97_AC_97_RESERVED = 0x24,
  47. AC97_Powerdown_Ctrl_Stat = 0x26,
  48. AC97_Extended_Audio_ID = 0x28,
  49. AC97_Extended_Audio_Ctrl_Stat = 0x2A,
  50. AC97_PCM_Front_DAC_Rate = 0x2C,
  51. AC97_PCM_Surround_DAC_Rate = 0x2E,
  52. AC97_PCM_LFE_DAC_Rate = 0x30,
  53. AC97_PCM_LR_ADC_Rate = 0x32,
  54. AC97_MIC_ADC_Rate = 0x34,
  55. AC97_6Ch_Vol_C_LFE_Mute = 0x36,
  56. AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
  57. AC97_Vendor_Reserved = 0x58,
  58. AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
  59. AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
  60. AC97_Vendor_ID1 = 0x7c,
  61. AC97_Vendor_ID2 = 0x7e
  62. };
  63. #define SOFT_VOLUME
  64. #define SR_FIFOE 16 /* rwc */
  65. #define SR_BCIS 8 /* rwc */
  66. #define SR_LVBCI 4 /* rwc */
  67. #define SR_CELV 2 /* ro */
  68. #define SR_DCH 1 /* ro */
  69. #define SR_VALID_MASK ((1 << 5) - 1)
  70. #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
  71. #define SR_RO_MASK (SR_DCH | SR_CELV)
  72. #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
  73. #define CR_IOCE 16 /* rw */
  74. #define CR_FEIE 8 /* rw */
  75. #define CR_LVBIE 4 /* rw */
  76. #define CR_RR 2 /* rw */
  77. #define CR_RPBM 1 /* rw */
  78. #define CR_VALID_MASK ((1 << 5) - 1)
  79. #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
  80. #define GC_WR 4 /* rw */
  81. #define GC_CR 2 /* rw */
  82. #define GC_VALID_MASK ((1 << 6) - 1)
  83. #define GS_MD3 (1<<17) /* rw */
  84. #define GS_AD3 (1<<16) /* rw */
  85. #define GS_RCS (1<<15) /* rwc */
  86. #define GS_B3S12 (1<<14) /* ro */
  87. #define GS_B2S12 (1<<13) /* ro */
  88. #define GS_B1S12 (1<<12) /* ro */
  89. #define GS_S1R1 (1<<11) /* rwc */
  90. #define GS_S0R1 (1<<10) /* rwc */
  91. #define GS_S1CR (1<<9) /* ro */
  92. #define GS_S0CR (1<<8) /* ro */
  93. #define GS_MINT (1<<7) /* ro */
  94. #define GS_POINT (1<<6) /* ro */
  95. #define GS_PIINT (1<<5) /* ro */
  96. #define GS_RSRVD ((1<<4)|(1<<3))
  97. #define GS_MOINT (1<<2) /* ro */
  98. #define GS_MIINT (1<<1) /* ro */
  99. #define GS_GSCI 1 /* rwc */
  100. #define GS_RO_MASK (GS_B3S12| \
  101. GS_B2S12| \
  102. GS_B1S12| \
  103. GS_S1CR| \
  104. GS_S0CR| \
  105. GS_MINT| \
  106. GS_POINT| \
  107. GS_PIINT| \
  108. GS_RSRVD| \
  109. GS_MOINT| \
  110. GS_MIINT)
  111. #define GS_VALID_MASK ((1 << 18) - 1)
  112. #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
  113. #define BD_IOC (1<<31)
  114. #define BD_BUP (1<<30)
  115. #define EACS_VRA 1
  116. #define EACS_VRM 8
  117. #define MUTE_SHIFT 15
  118. #define TYPE_AC97 "AC97"
  119. #define AC97(obj) \
  120. OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97)
  121. #define REC_MASK 7
  122. enum {
  123. REC_MIC = 0,
  124. REC_CD,
  125. REC_VIDEO,
  126. REC_AUX,
  127. REC_LINE_IN,
  128. REC_STEREO_MIX,
  129. REC_MONO_MIX,
  130. REC_PHONE
  131. };
  132. typedef struct BD {
  133. uint32_t addr;
  134. uint32_t ctl_len;
  135. } BD;
  136. typedef struct AC97BusMasterRegs {
  137. uint32_t bdbar; /* rw 0 */
  138. uint8_t civ; /* ro 0 */
  139. uint8_t lvi; /* rw 0 */
  140. uint16_t sr; /* rw 1 */
  141. uint16_t picb; /* ro 0 */
  142. uint8_t piv; /* ro 0 */
  143. uint8_t cr; /* rw 0 */
  144. unsigned int bd_valid;
  145. BD bd;
  146. } AC97BusMasterRegs;
  147. typedef struct AC97LinkState {
  148. PCIDevice dev;
  149. QEMUSoundCard card;
  150. uint32_t use_broken_id;
  151. uint32_t glob_cnt;
  152. uint32_t glob_sta;
  153. uint32_t cas;
  154. uint32_t last_samp;
  155. AC97BusMasterRegs bm_regs[3];
  156. uint8_t mixer_data[256];
  157. SWVoiceIn *voice_pi;
  158. SWVoiceOut *voice_po;
  159. SWVoiceIn *voice_mc;
  160. int invalid_freq[3];
  161. uint8_t silence[128];
  162. int bup_flag;
  163. MemoryRegion io_nam;
  164. MemoryRegion io_nabm;
  165. } AC97LinkState;
  166. enum {
  167. BUP_SET = 1,
  168. BUP_LAST = 2
  169. };
  170. #ifdef DEBUG_AC97
  171. #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
  172. #else
  173. #define dolog(...)
  174. #endif
  175. #define MKREGS(prefix, start) \
  176. enum { \
  177. prefix ## _BDBAR = start, \
  178. prefix ## _CIV = start + 4, \
  179. prefix ## _LVI = start + 5, \
  180. prefix ## _SR = start + 6, \
  181. prefix ## _PICB = start + 8, \
  182. prefix ## _PIV = start + 10, \
  183. prefix ## _CR = start + 11 \
  184. }
  185. enum {
  186. PI_INDEX = 0,
  187. PO_INDEX,
  188. MC_INDEX,
  189. LAST_INDEX
  190. };
  191. MKREGS (PI, PI_INDEX * 16);
  192. MKREGS (PO, PO_INDEX * 16);
  193. MKREGS (MC, MC_INDEX * 16);
  194. enum {
  195. GLOB_CNT = 0x2c,
  196. GLOB_STA = 0x30,
  197. CAS = 0x34
  198. };
  199. #define GET_BM(index) (((index) >> 4) & 3)
  200. static void po_callback (void *opaque, int free);
  201. static void pi_callback (void *opaque, int avail);
  202. static void mc_callback (void *opaque, int avail);
  203. static void warm_reset (AC97LinkState *s)
  204. {
  205. (void) s;
  206. }
  207. static void cold_reset (AC97LinkState * s)
  208. {
  209. (void) s;
  210. }
  211. static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
  212. {
  213. uint8_t b[8];
  214. pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
  215. r->bd_valid = 1;
  216. r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
  217. r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
  218. r->picb = r->bd.ctl_len & 0xffff;
  219. dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
  220. r->civ, r->bd.addr, r->bd.ctl_len >> 16,
  221. r->bd.ctl_len & 0xffff,
  222. (r->bd.ctl_len & 0xffff) << 1);
  223. }
  224. static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
  225. {
  226. int event = 0;
  227. int level = 0;
  228. uint32_t new_mask = new_sr & SR_INT_MASK;
  229. uint32_t old_mask = r->sr & SR_INT_MASK;
  230. uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
  231. if (new_mask ^ old_mask) {
  232. /** @todo is IRQ deasserted when only one of status bits is cleared? */
  233. if (!new_mask) {
  234. event = 1;
  235. level = 0;
  236. }
  237. else {
  238. if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
  239. event = 1;
  240. level = 1;
  241. }
  242. if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
  243. event = 1;
  244. level = 1;
  245. }
  246. }
  247. }
  248. r->sr = new_sr;
  249. dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
  250. r->sr & SR_BCIS, r->sr & SR_LVBCI,
  251. r->sr,
  252. event, level);
  253. if (!event)
  254. return;
  255. if (level) {
  256. s->glob_sta |= masks[r - s->bm_regs];
  257. dolog ("set irq level=1\n");
  258. pci_irq_assert(&s->dev);
  259. }
  260. else {
  261. s->glob_sta &= ~masks[r - s->bm_regs];
  262. dolog ("set irq level=0\n");
  263. pci_irq_deassert(&s->dev);
  264. }
  265. }
  266. static void voice_set_active (AC97LinkState *s, int bm_index, int on)
  267. {
  268. switch (bm_index) {
  269. case PI_INDEX:
  270. AUD_set_active_in (s->voice_pi, on);
  271. break;
  272. case PO_INDEX:
  273. AUD_set_active_out (s->voice_po, on);
  274. break;
  275. case MC_INDEX:
  276. AUD_set_active_in (s->voice_mc, on);
  277. break;
  278. default:
  279. AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
  280. break;
  281. }
  282. }
  283. static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
  284. {
  285. dolog ("reset_bm_regs\n");
  286. r->bdbar = 0;
  287. r->civ = 0;
  288. r->lvi = 0;
  289. /** todo do we need to do that? */
  290. update_sr (s, r, SR_DCH);
  291. r->picb = 0;
  292. r->piv = 0;
  293. r->cr = r->cr & CR_DONT_CLEAR_MASK;
  294. r->bd_valid = 0;
  295. voice_set_active (s, r - s->bm_regs, 0);
  296. memset (s->silence, 0, sizeof (s->silence));
  297. }
  298. static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
  299. {
  300. if (i + 2 > sizeof (s->mixer_data)) {
  301. dolog ("mixer_store: index %d out of bounds %zd\n",
  302. i, sizeof (s->mixer_data));
  303. return;
  304. }
  305. s->mixer_data[i + 0] = v & 0xff;
  306. s->mixer_data[i + 1] = v >> 8;
  307. }
  308. static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
  309. {
  310. uint16_t val = 0xffff;
  311. if (i + 2 > sizeof (s->mixer_data)) {
  312. dolog ("mixer_load: index %d out of bounds %zd\n",
  313. i, sizeof (s->mixer_data));
  314. }
  315. else {
  316. val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
  317. }
  318. return val;
  319. }
  320. static void open_voice (AC97LinkState *s, int index, int freq)
  321. {
  322. struct audsettings as;
  323. as.freq = freq;
  324. as.nchannels = 2;
  325. as.fmt = AUDIO_FORMAT_S16;
  326. as.endianness = 0;
  327. if (freq > 0) {
  328. s->invalid_freq[index] = 0;
  329. switch (index) {
  330. case PI_INDEX:
  331. s->voice_pi = AUD_open_in (
  332. &s->card,
  333. s->voice_pi,
  334. "ac97.pi",
  335. s,
  336. pi_callback,
  337. &as
  338. );
  339. break;
  340. case PO_INDEX:
  341. s->voice_po = AUD_open_out (
  342. &s->card,
  343. s->voice_po,
  344. "ac97.po",
  345. s,
  346. po_callback,
  347. &as
  348. );
  349. break;
  350. case MC_INDEX:
  351. s->voice_mc = AUD_open_in (
  352. &s->card,
  353. s->voice_mc,
  354. "ac97.mc",
  355. s,
  356. mc_callback,
  357. &as
  358. );
  359. break;
  360. }
  361. }
  362. else {
  363. s->invalid_freq[index] = freq;
  364. switch (index) {
  365. case PI_INDEX:
  366. AUD_close_in (&s->card, s->voice_pi);
  367. s->voice_pi = NULL;
  368. break;
  369. case PO_INDEX:
  370. AUD_close_out (&s->card, s->voice_po);
  371. s->voice_po = NULL;
  372. break;
  373. case MC_INDEX:
  374. AUD_close_in (&s->card, s->voice_mc);
  375. s->voice_mc = NULL;
  376. break;
  377. }
  378. }
  379. }
  380. static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
  381. {
  382. uint16_t freq;
  383. freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
  384. open_voice (s, PI_INDEX, freq);
  385. AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
  386. freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
  387. open_voice (s, PO_INDEX, freq);
  388. AUD_set_active_out (s->voice_po, active[PO_INDEX]);
  389. freq = mixer_load (s, AC97_MIC_ADC_Rate);
  390. open_voice (s, MC_INDEX, freq);
  391. AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
  392. }
  393. static void get_volume (uint16_t vol, uint16_t mask, int inverse,
  394. int *mute, uint8_t *lvol, uint8_t *rvol)
  395. {
  396. *mute = (vol >> MUTE_SHIFT) & 1;
  397. *rvol = (255 * (vol & mask)) / mask;
  398. *lvol = (255 * ((vol >> 8) & mask)) / mask;
  399. if (inverse) {
  400. *rvol = 255 - *rvol;
  401. *lvol = 255 - *lvol;
  402. }
  403. }
  404. static void update_combined_volume_out (AC97LinkState *s)
  405. {
  406. uint8_t lvol, rvol, plvol, prvol;
  407. int mute, pmute;
  408. get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1,
  409. &mute, &lvol, &rvol);
  410. get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1,
  411. &pmute, &plvol, &prvol);
  412. mute = mute | pmute;
  413. lvol = (lvol * plvol) / 255;
  414. rvol = (rvol * prvol) / 255;
  415. AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
  416. }
  417. static void update_volume_in (AC97LinkState *s)
  418. {
  419. uint8_t lvol, rvol;
  420. int mute;
  421. get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0,
  422. &mute, &lvol, &rvol);
  423. AUD_set_volume_in (s->voice_pi, mute, lvol, rvol);
  424. }
  425. static void set_volume (AC97LinkState *s, int index, uint32_t val)
  426. {
  427. switch (index) {
  428. case AC97_Master_Volume_Mute:
  429. val &= 0xbf3f;
  430. mixer_store (s, index, val);
  431. update_combined_volume_out (s);
  432. break;
  433. case AC97_PCM_Out_Volume_Mute:
  434. val &= 0x9f1f;
  435. mixer_store (s, index, val);
  436. update_combined_volume_out (s);
  437. break;
  438. case AC97_Record_Gain_Mute:
  439. val &= 0x8f0f;
  440. mixer_store (s, index, val);
  441. update_volume_in (s);
  442. break;
  443. }
  444. }
  445. static void record_select (AC97LinkState *s, uint32_t val)
  446. {
  447. uint8_t rs = val & REC_MASK;
  448. uint8_t ls = (val >> 8) & REC_MASK;
  449. mixer_store (s, AC97_Record_Select, rs | (ls << 8));
  450. }
  451. static void mixer_reset (AC97LinkState *s)
  452. {
  453. uint8_t active[LAST_INDEX];
  454. dolog ("mixer_reset\n");
  455. memset (s->mixer_data, 0, sizeof (s->mixer_data));
  456. memset (active, 0, sizeof (active));
  457. mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
  458. mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000);
  459. mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000);
  460. mixer_store (s, AC97_Master_Tone_RL, 0x0000);
  461. mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
  462. mixer_store (s, AC97_Phone_Volume_Mute , 0x0000);
  463. mixer_store (s, AC97_Mic_Volume_Mute , 0x0000);
  464. mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000);
  465. mixer_store (s, AC97_CD_Volume_Mute , 0x0000);
  466. mixer_store (s, AC97_Video_Volume_Mute , 0x0000);
  467. mixer_store (s, AC97_Aux_Volume_Mute , 0x0000);
  468. mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000);
  469. mixer_store (s, AC97_General_Purpose , 0x0000);
  470. mixer_store (s, AC97_3D_Control , 0x0000);
  471. mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
  472. /*
  473. * Sigmatel 9700 (STAC9700)
  474. */
  475. mixer_store (s, AC97_Vendor_ID1 , 0x8384);
  476. mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
  477. mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
  478. mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
  479. mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
  480. mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
  481. mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
  482. mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
  483. mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
  484. record_select (s, 0);
  485. set_volume (s, AC97_Master_Volume_Mute, 0x8000);
  486. set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808);
  487. set_volume (s, AC97_Record_Gain_Mute, 0x8808);
  488. reset_voices (s, active);
  489. }
  490. /**
  491. * Native audio mixer
  492. * I/O Reads
  493. */
  494. static uint32_t nam_readb (void *opaque, uint32_t addr)
  495. {
  496. AC97LinkState *s = opaque;
  497. dolog ("U nam readb %#x\n", addr);
  498. s->cas = 0;
  499. return ~0U;
  500. }
  501. static uint32_t nam_readw (void *opaque, uint32_t addr)
  502. {
  503. AC97LinkState *s = opaque;
  504. uint32_t val = ~0U;
  505. uint32_t index = addr;
  506. s->cas = 0;
  507. val = mixer_load (s, index);
  508. return val;
  509. }
  510. static uint32_t nam_readl (void *opaque, uint32_t addr)
  511. {
  512. AC97LinkState *s = opaque;
  513. dolog ("U nam readl %#x\n", addr);
  514. s->cas = 0;
  515. return ~0U;
  516. }
  517. /**
  518. * Native audio mixer
  519. * I/O Writes
  520. */
  521. static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
  522. {
  523. AC97LinkState *s = opaque;
  524. dolog ("U nam writeb %#x <- %#x\n", addr, val);
  525. s->cas = 0;
  526. }
  527. static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
  528. {
  529. AC97LinkState *s = opaque;
  530. uint32_t index = addr;
  531. s->cas = 0;
  532. switch (index) {
  533. case AC97_Reset:
  534. mixer_reset (s);
  535. break;
  536. case AC97_Powerdown_Ctrl_Stat:
  537. val &= ~0x800f;
  538. val |= mixer_load (s, index) & 0xf;
  539. mixer_store (s, index, val);
  540. break;
  541. case AC97_PCM_Out_Volume_Mute:
  542. case AC97_Master_Volume_Mute:
  543. case AC97_Record_Gain_Mute:
  544. set_volume (s, index, val);
  545. break;
  546. case AC97_Record_Select:
  547. record_select (s, val);
  548. break;
  549. case AC97_Vendor_ID1:
  550. case AC97_Vendor_ID2:
  551. dolog ("Attempt to write vendor ID to %#x\n", val);
  552. break;
  553. case AC97_Extended_Audio_ID:
  554. dolog ("Attempt to write extended audio ID to %#x\n", val);
  555. break;
  556. case AC97_Extended_Audio_Ctrl_Stat:
  557. if (!(val & EACS_VRA)) {
  558. mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
  559. mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
  560. open_voice (s, PI_INDEX, 48000);
  561. open_voice (s, PO_INDEX, 48000);
  562. }
  563. if (!(val & EACS_VRM)) {
  564. mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
  565. open_voice (s, MC_INDEX, 48000);
  566. }
  567. dolog ("Setting extended audio control to %#x\n", val);
  568. mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
  569. break;
  570. case AC97_PCM_Front_DAC_Rate:
  571. if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
  572. mixer_store (s, index, val);
  573. dolog ("Set front DAC rate to %d\n", val);
  574. open_voice (s, PO_INDEX, val);
  575. }
  576. else {
  577. dolog ("Attempt to set front DAC rate to %d, "
  578. "but VRA is not set\n",
  579. val);
  580. }
  581. break;
  582. case AC97_MIC_ADC_Rate:
  583. if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
  584. mixer_store (s, index, val);
  585. dolog ("Set MIC ADC rate to %d\n", val);
  586. open_voice (s, MC_INDEX, val);
  587. }
  588. else {
  589. dolog ("Attempt to set MIC ADC rate to %d, "
  590. "but VRM is not set\n",
  591. val);
  592. }
  593. break;
  594. case AC97_PCM_LR_ADC_Rate:
  595. if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
  596. mixer_store (s, index, val);
  597. dolog ("Set front LR ADC rate to %d\n", val);
  598. open_voice (s, PI_INDEX, val);
  599. }
  600. else {
  601. dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
  602. val);
  603. }
  604. break;
  605. case AC97_Headphone_Volume_Mute:
  606. case AC97_Master_Volume_Mono_Mute:
  607. case AC97_Master_Tone_RL:
  608. case AC97_PC_BEEP_Volume_Mute:
  609. case AC97_Phone_Volume_Mute:
  610. case AC97_Mic_Volume_Mute:
  611. case AC97_Line_In_Volume_Mute:
  612. case AC97_CD_Volume_Mute:
  613. case AC97_Video_Volume_Mute:
  614. case AC97_Aux_Volume_Mute:
  615. case AC97_Record_Gain_Mic_Mute:
  616. case AC97_General_Purpose:
  617. case AC97_3D_Control:
  618. case AC97_Sigmatel_Analog:
  619. case AC97_Sigmatel_Dac2Invert:
  620. /* None of the features in these regs are emulated, so they are RO */
  621. break;
  622. default:
  623. dolog ("U nam writew %#x <- %#x\n", addr, val);
  624. mixer_store (s, index, val);
  625. break;
  626. }
  627. }
  628. static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
  629. {
  630. AC97LinkState *s = opaque;
  631. dolog ("U nam writel %#x <- %#x\n", addr, val);
  632. s->cas = 0;
  633. }
  634. /**
  635. * Native audio bus master
  636. * I/O Reads
  637. */
  638. static uint32_t nabm_readb (void *opaque, uint32_t addr)
  639. {
  640. AC97LinkState *s = opaque;
  641. AC97BusMasterRegs *r = NULL;
  642. uint32_t index = addr;
  643. uint32_t val = ~0U;
  644. switch (index) {
  645. case CAS:
  646. dolog ("CAS %d\n", s->cas);
  647. val = s->cas;
  648. s->cas = 1;
  649. break;
  650. case PI_CIV:
  651. case PO_CIV:
  652. case MC_CIV:
  653. r = &s->bm_regs[GET_BM (index)];
  654. val = r->civ;
  655. dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
  656. break;
  657. case PI_LVI:
  658. case PO_LVI:
  659. case MC_LVI:
  660. r = &s->bm_regs[GET_BM (index)];
  661. val = r->lvi;
  662. dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
  663. break;
  664. case PI_PIV:
  665. case PO_PIV:
  666. case MC_PIV:
  667. r = &s->bm_regs[GET_BM (index)];
  668. val = r->piv;
  669. dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
  670. break;
  671. case PI_CR:
  672. case PO_CR:
  673. case MC_CR:
  674. r = &s->bm_regs[GET_BM (index)];
  675. val = r->cr;
  676. dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
  677. break;
  678. case PI_SR:
  679. case PO_SR:
  680. case MC_SR:
  681. r = &s->bm_regs[GET_BM (index)];
  682. val = r->sr & 0xff;
  683. dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
  684. break;
  685. default:
  686. dolog ("U nabm readb %#x -> %#x\n", addr, val);
  687. break;
  688. }
  689. return val;
  690. }
  691. static uint32_t nabm_readw (void *opaque, uint32_t addr)
  692. {
  693. AC97LinkState *s = opaque;
  694. AC97BusMasterRegs *r = NULL;
  695. uint32_t index = addr;
  696. uint32_t val = ~0U;
  697. switch (index) {
  698. case PI_SR:
  699. case PO_SR:
  700. case MC_SR:
  701. r = &s->bm_regs[GET_BM (index)];
  702. val = r->sr;
  703. dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
  704. break;
  705. case PI_PICB:
  706. case PO_PICB:
  707. case MC_PICB:
  708. r = &s->bm_regs[GET_BM (index)];
  709. val = r->picb;
  710. dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
  711. break;
  712. default:
  713. dolog ("U nabm readw %#x -> %#x\n", addr, val);
  714. break;
  715. }
  716. return val;
  717. }
  718. static uint32_t nabm_readl (void *opaque, uint32_t addr)
  719. {
  720. AC97LinkState *s = opaque;
  721. AC97BusMasterRegs *r = NULL;
  722. uint32_t index = addr;
  723. uint32_t val = ~0U;
  724. switch (index) {
  725. case PI_BDBAR:
  726. case PO_BDBAR:
  727. case MC_BDBAR:
  728. r = &s->bm_regs[GET_BM (index)];
  729. val = r->bdbar;
  730. dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
  731. break;
  732. case PI_CIV:
  733. case PO_CIV:
  734. case MC_CIV:
  735. r = &s->bm_regs[GET_BM (index)];
  736. val = r->civ | (r->lvi << 8) | (r->sr << 16);
  737. dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
  738. r->civ, r->lvi, r->sr);
  739. break;
  740. case PI_PICB:
  741. case PO_PICB:
  742. case MC_PICB:
  743. r = &s->bm_regs[GET_BM (index)];
  744. val = r->picb | (r->piv << 16) | (r->cr << 24);
  745. dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
  746. val, r->picb, r->piv, r->cr);
  747. break;
  748. case GLOB_CNT:
  749. val = s->glob_cnt;
  750. dolog ("glob_cnt -> %#x\n", val);
  751. break;
  752. case GLOB_STA:
  753. val = s->glob_sta | GS_S0CR;
  754. dolog ("glob_sta -> %#x\n", val);
  755. break;
  756. default:
  757. dolog ("U nabm readl %#x -> %#x\n", addr, val);
  758. break;
  759. }
  760. return val;
  761. }
  762. /**
  763. * Native audio bus master
  764. * I/O Writes
  765. */
  766. static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
  767. {
  768. AC97LinkState *s = opaque;
  769. AC97BusMasterRegs *r = NULL;
  770. uint32_t index = addr;
  771. switch (index) {
  772. case PI_LVI:
  773. case PO_LVI:
  774. case MC_LVI:
  775. r = &s->bm_regs[GET_BM (index)];
  776. if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
  777. r->sr &= ~(SR_DCH | SR_CELV);
  778. r->civ = r->piv;
  779. r->piv = (r->piv + 1) % 32;
  780. fetch_bd (s, r);
  781. }
  782. r->lvi = val % 32;
  783. dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
  784. break;
  785. case PI_CR:
  786. case PO_CR:
  787. case MC_CR:
  788. r = &s->bm_regs[GET_BM (index)];
  789. if (val & CR_RR) {
  790. reset_bm_regs (s, r);
  791. }
  792. else {
  793. r->cr = val & CR_VALID_MASK;
  794. if (!(r->cr & CR_RPBM)) {
  795. voice_set_active (s, r - s->bm_regs, 0);
  796. r->sr |= SR_DCH;
  797. }
  798. else {
  799. r->civ = r->piv;
  800. r->piv = (r->piv + 1) % 32;
  801. fetch_bd (s, r);
  802. r->sr &= ~SR_DCH;
  803. voice_set_active (s, r - s->bm_regs, 1);
  804. }
  805. }
  806. dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
  807. break;
  808. case PI_SR:
  809. case PO_SR:
  810. case MC_SR:
  811. r = &s->bm_regs[GET_BM (index)];
  812. r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
  813. update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
  814. dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
  815. break;
  816. default:
  817. dolog ("U nabm writeb %#x <- %#x\n", addr, val);
  818. break;
  819. }
  820. }
  821. static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
  822. {
  823. AC97LinkState *s = opaque;
  824. AC97BusMasterRegs *r = NULL;
  825. uint32_t index = addr;
  826. switch (index) {
  827. case PI_SR:
  828. case PO_SR:
  829. case MC_SR:
  830. r = &s->bm_regs[GET_BM (index)];
  831. r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
  832. update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
  833. dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
  834. break;
  835. default:
  836. dolog ("U nabm writew %#x <- %#x\n", addr, val);
  837. break;
  838. }
  839. }
  840. static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
  841. {
  842. AC97LinkState *s = opaque;
  843. AC97BusMasterRegs *r = NULL;
  844. uint32_t index = addr;
  845. switch (index) {
  846. case PI_BDBAR:
  847. case PO_BDBAR:
  848. case MC_BDBAR:
  849. r = &s->bm_regs[GET_BM (index)];
  850. r->bdbar = val & ~3;
  851. dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
  852. GET_BM (index), val, r->bdbar);
  853. break;
  854. case GLOB_CNT:
  855. if (val & GC_WR)
  856. warm_reset (s);
  857. if (val & GC_CR)
  858. cold_reset (s);
  859. if (!(val & (GC_WR | GC_CR)))
  860. s->glob_cnt = val & GC_VALID_MASK;
  861. dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
  862. break;
  863. case GLOB_STA:
  864. s->glob_sta &= ~(val & GS_WCLEAR_MASK);
  865. s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
  866. dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
  867. break;
  868. default:
  869. dolog ("U nabm writel %#x <- %#x\n", addr, val);
  870. break;
  871. }
  872. }
  873. static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
  874. int max, int *stop)
  875. {
  876. uint8_t tmpbuf[4096];
  877. uint32_t addr = r->bd.addr;
  878. uint32_t temp = r->picb << 1;
  879. uint32_t written = 0;
  880. int to_copy = 0;
  881. temp = MIN (temp, max);
  882. if (!temp) {
  883. *stop = 1;
  884. return 0;
  885. }
  886. while (temp) {
  887. int copied;
  888. to_copy = MIN (temp, sizeof (tmpbuf));
  889. pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
  890. copied = AUD_write (s->voice_po, tmpbuf, to_copy);
  891. dolog ("write_audio max=%x to_copy=%x copied=%x\n",
  892. max, to_copy, copied);
  893. if (!copied) {
  894. *stop = 1;
  895. break;
  896. }
  897. temp -= copied;
  898. addr += copied;
  899. written += copied;
  900. }
  901. if (!temp) {
  902. if (to_copy < 4) {
  903. dolog ("whoops\n");
  904. s->last_samp = 0;
  905. }
  906. else {
  907. s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
  908. }
  909. }
  910. r->bd.addr = addr;
  911. return written;
  912. }
  913. static void write_bup (AC97LinkState *s, int elapsed)
  914. {
  915. dolog ("write_bup\n");
  916. if (!(s->bup_flag & BUP_SET)) {
  917. if (s->bup_flag & BUP_LAST) {
  918. int i;
  919. uint8_t *p = s->silence;
  920. for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
  921. *(uint32_t *) p = s->last_samp;
  922. }
  923. }
  924. else {
  925. memset (s->silence, 0, sizeof (s->silence));
  926. }
  927. s->bup_flag |= BUP_SET;
  928. }
  929. while (elapsed) {
  930. int temp = MIN (elapsed, sizeof (s->silence));
  931. while (temp) {
  932. int copied = AUD_write (s->voice_po, s->silence, temp);
  933. if (!copied)
  934. return;
  935. temp -= copied;
  936. elapsed -= copied;
  937. }
  938. }
  939. }
  940. static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
  941. int max, int *stop)
  942. {
  943. uint8_t tmpbuf[4096];
  944. uint32_t addr = r->bd.addr;
  945. uint32_t temp = r->picb << 1;
  946. uint32_t nread = 0;
  947. int to_copy = 0;
  948. SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
  949. temp = MIN (temp, max);
  950. if (!temp) {
  951. *stop = 1;
  952. return 0;
  953. }
  954. while (temp) {
  955. int acquired;
  956. to_copy = MIN (temp, sizeof (tmpbuf));
  957. acquired = AUD_read (voice, tmpbuf, to_copy);
  958. if (!acquired) {
  959. *stop = 1;
  960. break;
  961. }
  962. pci_dma_write (&s->dev, addr, tmpbuf, acquired);
  963. temp -= acquired;
  964. addr += acquired;
  965. nread += acquired;
  966. }
  967. r->bd.addr = addr;
  968. return nread;
  969. }
  970. static void transfer_audio (AC97LinkState *s, int index, int elapsed)
  971. {
  972. AC97BusMasterRegs *r = &s->bm_regs[index];
  973. int stop = 0;
  974. if (s->invalid_freq[index]) {
  975. AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
  976. index, s->invalid_freq[index]);
  977. return;
  978. }
  979. if (r->sr & SR_DCH) {
  980. if (r->cr & CR_RPBM) {
  981. switch (index) {
  982. case PO_INDEX:
  983. write_bup (s, elapsed);
  984. break;
  985. }
  986. }
  987. return;
  988. }
  989. while ((elapsed >> 1) && !stop) {
  990. int temp;
  991. if (!r->bd_valid) {
  992. dolog ("invalid bd\n");
  993. fetch_bd (s, r);
  994. }
  995. if (!r->picb) {
  996. dolog ("fresh bd %d is empty %#x %#x\n",
  997. r->civ, r->bd.addr, r->bd.ctl_len);
  998. if (r->civ == r->lvi) {
  999. r->sr |= SR_DCH; /* CELV? */
  1000. s->bup_flag = 0;
  1001. break;
  1002. }
  1003. r->sr &= ~SR_CELV;
  1004. r->civ = r->piv;
  1005. r->piv = (r->piv + 1) % 32;
  1006. fetch_bd (s, r);
  1007. return;
  1008. }
  1009. switch (index) {
  1010. case PO_INDEX:
  1011. temp = write_audio (s, r, elapsed, &stop);
  1012. elapsed -= temp;
  1013. r->picb -= (temp >> 1);
  1014. break;
  1015. case PI_INDEX:
  1016. case MC_INDEX:
  1017. temp = read_audio (s, r, elapsed, &stop);
  1018. elapsed -= temp;
  1019. r->picb -= (temp >> 1);
  1020. break;
  1021. }
  1022. if (!r->picb) {
  1023. uint32_t new_sr = r->sr & ~SR_CELV;
  1024. if (r->bd.ctl_len & BD_IOC) {
  1025. new_sr |= SR_BCIS;
  1026. }
  1027. if (r->civ == r->lvi) {
  1028. dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
  1029. new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
  1030. stop = 1;
  1031. s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
  1032. }
  1033. else {
  1034. r->civ = r->piv;
  1035. r->piv = (r->piv + 1) % 32;
  1036. fetch_bd (s, r);
  1037. }
  1038. update_sr (s, r, new_sr);
  1039. }
  1040. }
  1041. }
  1042. static void pi_callback (void *opaque, int avail)
  1043. {
  1044. transfer_audio (opaque, PI_INDEX, avail);
  1045. }
  1046. static void mc_callback (void *opaque, int avail)
  1047. {
  1048. transfer_audio (opaque, MC_INDEX, avail);
  1049. }
  1050. static void po_callback (void *opaque, int free)
  1051. {
  1052. transfer_audio (opaque, PO_INDEX, free);
  1053. }
  1054. static const VMStateDescription vmstate_ac97_bm_regs = {
  1055. .name = "ac97_bm_regs",
  1056. .version_id = 1,
  1057. .minimum_version_id = 1,
  1058. .fields = (VMStateField[]) {
  1059. VMSTATE_UINT32 (bdbar, AC97BusMasterRegs),
  1060. VMSTATE_UINT8 (civ, AC97BusMasterRegs),
  1061. VMSTATE_UINT8 (lvi, AC97BusMasterRegs),
  1062. VMSTATE_UINT16 (sr, AC97BusMasterRegs),
  1063. VMSTATE_UINT16 (picb, AC97BusMasterRegs),
  1064. VMSTATE_UINT8 (piv, AC97BusMasterRegs),
  1065. VMSTATE_UINT8 (cr, AC97BusMasterRegs),
  1066. VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs),
  1067. VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs),
  1068. VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs),
  1069. VMSTATE_END_OF_LIST ()
  1070. }
  1071. };
  1072. static int ac97_post_load (void *opaque, int version_id)
  1073. {
  1074. uint8_t active[LAST_INDEX];
  1075. AC97LinkState *s = opaque;
  1076. record_select (s, mixer_load (s, AC97_Record_Select));
  1077. set_volume (s, AC97_Master_Volume_Mute,
  1078. mixer_load (s, AC97_Master_Volume_Mute));
  1079. set_volume (s, AC97_PCM_Out_Volume_Mute,
  1080. mixer_load (s, AC97_PCM_Out_Volume_Mute));
  1081. set_volume (s, AC97_Record_Gain_Mute,
  1082. mixer_load (s, AC97_Record_Gain_Mute));
  1083. active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
  1084. active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
  1085. active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
  1086. reset_voices (s, active);
  1087. s->bup_flag = 0;
  1088. s->last_samp = 0;
  1089. return 0;
  1090. }
  1091. static bool is_version_2 (void *opaque, int version_id)
  1092. {
  1093. return version_id == 2;
  1094. }
  1095. static const VMStateDescription vmstate_ac97 = {
  1096. .name = "ac97",
  1097. .version_id = 3,
  1098. .minimum_version_id = 2,
  1099. .post_load = ac97_post_load,
  1100. .fields = (VMStateField[]) {
  1101. VMSTATE_PCI_DEVICE (dev, AC97LinkState),
  1102. VMSTATE_UINT32 (glob_cnt, AC97LinkState),
  1103. VMSTATE_UINT32 (glob_sta, AC97LinkState),
  1104. VMSTATE_UINT32 (cas, AC97LinkState),
  1105. VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1,
  1106. vmstate_ac97_bm_regs, AC97BusMasterRegs),
  1107. VMSTATE_BUFFER (mixer_data, AC97LinkState),
  1108. VMSTATE_UNUSED_TEST (is_version_2, 3),
  1109. VMSTATE_END_OF_LIST ()
  1110. }
  1111. };
  1112. static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size)
  1113. {
  1114. if ((addr / size) > 256) {
  1115. return -1;
  1116. }
  1117. switch (size) {
  1118. case 1:
  1119. return nam_readb(opaque, addr);
  1120. case 2:
  1121. return nam_readw(opaque, addr);
  1122. case 4:
  1123. return nam_readl(opaque, addr);
  1124. default:
  1125. return -1;
  1126. }
  1127. }
  1128. static void nam_write(void *opaque, hwaddr addr, uint64_t val,
  1129. unsigned size)
  1130. {
  1131. if ((addr / size) > 256) {
  1132. return;
  1133. }
  1134. switch (size) {
  1135. case 1:
  1136. nam_writeb(opaque, addr, val);
  1137. break;
  1138. case 2:
  1139. nam_writew(opaque, addr, val);
  1140. break;
  1141. case 4:
  1142. nam_writel(opaque, addr, val);
  1143. break;
  1144. }
  1145. }
  1146. static const MemoryRegionOps ac97_io_nam_ops = {
  1147. .read = nam_read,
  1148. .write = nam_write,
  1149. .impl = {
  1150. .min_access_size = 1,
  1151. .max_access_size = 4,
  1152. },
  1153. .endianness = DEVICE_LITTLE_ENDIAN,
  1154. };
  1155. static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size)
  1156. {
  1157. if ((addr / size) > 64) {
  1158. return -1;
  1159. }
  1160. switch (size) {
  1161. case 1:
  1162. return nabm_readb(opaque, addr);
  1163. case 2:
  1164. return nabm_readw(opaque, addr);
  1165. case 4:
  1166. return nabm_readl(opaque, addr);
  1167. default:
  1168. return -1;
  1169. }
  1170. }
  1171. static void nabm_write(void *opaque, hwaddr addr, uint64_t val,
  1172. unsigned size)
  1173. {
  1174. if ((addr / size) > 64) {
  1175. return;
  1176. }
  1177. switch (size) {
  1178. case 1:
  1179. nabm_writeb(opaque, addr, val);
  1180. break;
  1181. case 2:
  1182. nabm_writew(opaque, addr, val);
  1183. break;
  1184. case 4:
  1185. nabm_writel(opaque, addr, val);
  1186. break;
  1187. }
  1188. }
  1189. static const MemoryRegionOps ac97_io_nabm_ops = {
  1190. .read = nabm_read,
  1191. .write = nabm_write,
  1192. .impl = {
  1193. .min_access_size = 1,
  1194. .max_access_size = 4,
  1195. },
  1196. .endianness = DEVICE_LITTLE_ENDIAN,
  1197. };
  1198. static void ac97_on_reset (DeviceState *dev)
  1199. {
  1200. AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
  1201. reset_bm_regs (s, &s->bm_regs[0]);
  1202. reset_bm_regs (s, &s->bm_regs[1]);
  1203. reset_bm_regs (s, &s->bm_regs[2]);
  1204. /*
  1205. * Reset the mixer too. The Windows XP driver seems to rely on
  1206. * this. At least it wants to read the vendor id before it resets
  1207. * the codec manually.
  1208. */
  1209. mixer_reset (s);
  1210. }
  1211. static void ac97_realize(PCIDevice *dev, Error **errp)
  1212. {
  1213. AC97LinkState *s = AC97(dev);
  1214. uint8_t *c = s->dev.config;
  1215. /* TODO: no need to override */
  1216. c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
  1217. c[PCI_COMMAND + 1] = 0x00;
  1218. /* TODO: */
  1219. c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
  1220. c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
  1221. c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
  1222. /* TODO set when bar is registered. no need to override. */
  1223. /* nabmar native audio mixer base address rw */
  1224. c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
  1225. c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
  1226. c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
  1227. c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
  1228. /* TODO set when bar is registered. no need to override. */
  1229. /* nabmbar native audio bus mastering base address rw */
  1230. c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
  1231. c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
  1232. c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
  1233. c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
  1234. if (s->use_broken_id) {
  1235. c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86;
  1236. c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
  1237. c[PCI_SUBSYSTEM_ID] = 0x00;
  1238. c[PCI_SUBSYSTEM_ID + 1] = 0x00;
  1239. }
  1240. c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
  1241. c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
  1242. memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s,
  1243. "ac97-nam", 1024);
  1244. memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s,
  1245. "ac97-nabm", 256);
  1246. pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
  1247. pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
  1248. AUD_register_card ("ac97", &s->card);
  1249. ac97_on_reset(DEVICE(s));
  1250. }
  1251. static void ac97_exit(PCIDevice *dev)
  1252. {
  1253. AC97LinkState *s = AC97(dev);
  1254. AUD_close_in(&s->card, s->voice_pi);
  1255. AUD_close_out(&s->card, s->voice_po);
  1256. AUD_close_in(&s->card, s->voice_mc);
  1257. AUD_remove_card(&s->card);
  1258. }
  1259. static int ac97_init (PCIBus *bus)
  1260. {
  1261. pci_create_simple(bus, -1, TYPE_AC97);
  1262. return 0;
  1263. }
  1264. static Property ac97_properties[] = {
  1265. DEFINE_AUDIO_PROPERTIES(AC97LinkState, card),
  1266. DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0),
  1267. DEFINE_PROP_END_OF_LIST (),
  1268. };
  1269. static void ac97_class_init (ObjectClass *klass, void *data)
  1270. {
  1271. DeviceClass *dc = DEVICE_CLASS (klass);
  1272. PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
  1273. k->realize = ac97_realize;
  1274. k->exit = ac97_exit;
  1275. k->vendor_id = PCI_VENDOR_ID_INTEL;
  1276. k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
  1277. k->revision = 0x01;
  1278. k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
  1279. set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
  1280. dc->desc = "Intel 82801AA AC97 Audio";
  1281. dc->vmsd = &vmstate_ac97;
  1282. dc->props = ac97_properties;
  1283. dc->reset = ac97_on_reset;
  1284. }
  1285. static const TypeInfo ac97_info = {
  1286. .name = TYPE_AC97,
  1287. .parent = TYPE_PCI_DEVICE,
  1288. .instance_size = sizeof (AC97LinkState),
  1289. .class_init = ac97_class_init,
  1290. .interfaces = (InterfaceInfo[]) {
  1291. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1292. { },
  1293. },
  1294. };
  1295. static void ac97_register_types (void)
  1296. {
  1297. type_register_static (&ac97_info);
  1298. pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init);
  1299. }
  1300. type_init (ac97_register_types)