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pxa2xx_pic.c 10 KB

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  1. /*
  2. * Intel XScale PXA Programmable Interrupt Controller.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Copyright (c) 2006 Thorsten Zitterell
  6. * Written by Andrzej Zaborowski <balrog@zabor.org>
  7. *
  8. * This code is licensed under the GPL.
  9. */
  10. #include "qemu/osdep.h"
  11. #include "qemu/module.h"
  12. #include "cpu.h"
  13. #include "hw/arm/pxa.h"
  14. #include "hw/sysbus.h"
  15. #include "migration/vmstate.h"
  16. #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
  17. #define ICMR 0x04 /* Interrupt Controller Mask register */
  18. #define ICLR 0x08 /* Interrupt Controller Level register */
  19. #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
  20. #define ICPR 0x10 /* Interrupt Controller Pending register */
  21. #define ICCR 0x14 /* Interrupt Controller Control register */
  22. #define ICHP 0x18 /* Interrupt Controller Highest Priority register */
  23. #define IPR0 0x1c /* Interrupt Controller Priority register 0 */
  24. #define IPR31 0x98 /* Interrupt Controller Priority register 31 */
  25. #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
  26. #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
  27. #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
  28. #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
  29. #define ICPR2 0xac /* Interrupt Controller Pending register 2 */
  30. #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
  31. #define IPR39 0xcc /* Interrupt Controller Priority register 39 */
  32. #define PXA2XX_PIC_SRCS 40
  33. #define TYPE_PXA2XX_PIC "pxa2xx_pic"
  34. #define PXA2XX_PIC(obj) \
  35. OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
  36. typedef struct {
  37. /*< private >*/
  38. SysBusDevice parent_obj;
  39. /*< public >*/
  40. MemoryRegion iomem;
  41. ARMCPU *cpu;
  42. uint32_t int_enabled[2];
  43. uint32_t int_pending[2];
  44. uint32_t is_fiq[2];
  45. uint32_t int_idle;
  46. uint32_t priority[PXA2XX_PIC_SRCS];
  47. } PXA2xxPICState;
  48. static void pxa2xx_pic_update(void *opaque)
  49. {
  50. uint32_t mask[2];
  51. PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  52. CPUState *cpu = CPU(s->cpu);
  53. if (cpu->halted) {
  54. mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
  55. mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
  56. if (mask[0] || mask[1]) {
  57. cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
  58. }
  59. }
  60. mask[0] = s->int_pending[0] & s->int_enabled[0];
  61. mask[1] = s->int_pending[1] & s->int_enabled[1];
  62. if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
  63. cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
  64. } else {
  65. cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
  66. }
  67. if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
  68. cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
  69. } else {
  70. cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
  71. }
  72. }
  73. /* Note: Here level means state of the signal on a pin, not
  74. * IRQ/FIQ distinction as in PXA Developer Manual. */
  75. static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
  76. {
  77. PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  78. int int_set = (irq >= 32);
  79. irq &= 31;
  80. if (level)
  81. s->int_pending[int_set] |= 1 << irq;
  82. else
  83. s->int_pending[int_set] &= ~(1 << irq);
  84. pxa2xx_pic_update(opaque);
  85. }
  86. static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
  87. int i, int_set, irq;
  88. uint32_t bit, mask[2];
  89. uint32_t ichp = 0x003f003f; /* Both IDs invalid */
  90. mask[0] = s->int_pending[0] & s->int_enabled[0];
  91. mask[1] = s->int_pending[1] & s->int_enabled[1];
  92. for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
  93. irq = s->priority[i] & 0x3f;
  94. if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
  95. /* Source peripheral ID is valid. */
  96. bit = 1 << (irq & 31);
  97. int_set = (irq >= 32);
  98. if (mask[int_set] & bit & s->is_fiq[int_set]) {
  99. /* FIQ asserted */
  100. ichp &= 0xffff0000;
  101. ichp |= (1 << 15) | irq;
  102. }
  103. if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
  104. /* IRQ asserted */
  105. ichp &= 0x0000ffff;
  106. ichp |= (1U << 31) | (irq << 16);
  107. }
  108. }
  109. }
  110. return ichp;
  111. }
  112. static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
  113. unsigned size)
  114. {
  115. PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  116. switch (offset) {
  117. case ICIP: /* IRQ Pending register */
  118. return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
  119. case ICIP2: /* IRQ Pending register 2 */
  120. return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
  121. case ICMR: /* Mask register */
  122. return s->int_enabled[0];
  123. case ICMR2: /* Mask register 2 */
  124. return s->int_enabled[1];
  125. case ICLR: /* Level register */
  126. return s->is_fiq[0];
  127. case ICLR2: /* Level register 2 */
  128. return s->is_fiq[1];
  129. case ICCR: /* Idle mask */
  130. return (s->int_idle == 0);
  131. case ICFP: /* FIQ Pending register */
  132. return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
  133. case ICFP2: /* FIQ Pending register 2 */
  134. return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
  135. case ICPR: /* Pending register */
  136. return s->int_pending[0];
  137. case ICPR2: /* Pending register 2 */
  138. return s->int_pending[1];
  139. case IPR0 ... IPR31:
  140. return s->priority[0 + ((offset - IPR0 ) >> 2)];
  141. case IPR32 ... IPR39:
  142. return s->priority[32 + ((offset - IPR32) >> 2)];
  143. case ICHP: /* Highest Priority register */
  144. return pxa2xx_pic_highest(s);
  145. default:
  146. printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
  147. return 0;
  148. }
  149. }
  150. static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
  151. uint64_t value, unsigned size)
  152. {
  153. PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  154. switch (offset) {
  155. case ICMR: /* Mask register */
  156. s->int_enabled[0] = value;
  157. break;
  158. case ICMR2: /* Mask register 2 */
  159. s->int_enabled[1] = value;
  160. break;
  161. case ICLR: /* Level register */
  162. s->is_fiq[0] = value;
  163. break;
  164. case ICLR2: /* Level register 2 */
  165. s->is_fiq[1] = value;
  166. break;
  167. case ICCR: /* Idle mask */
  168. s->int_idle = (value & 1) ? 0 : ~0;
  169. break;
  170. case IPR0 ... IPR31:
  171. s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
  172. break;
  173. case IPR32 ... IPR39:
  174. s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
  175. break;
  176. default:
  177. printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
  178. return;
  179. }
  180. pxa2xx_pic_update(opaque);
  181. }
  182. /* Interrupt Controller Coprocessor Space Register Mapping */
  183. static const int pxa2xx_cp_reg_map[0x10] = {
  184. [0x0 ... 0xf] = -1,
  185. [0x0] = ICIP,
  186. [0x1] = ICMR,
  187. [0x2] = ICLR,
  188. [0x3] = ICFP,
  189. [0x4] = ICPR,
  190. [0x5] = ICHP,
  191. [0x6] = ICIP2,
  192. [0x7] = ICMR2,
  193. [0x8] = ICLR2,
  194. [0x9] = ICFP2,
  195. [0xa] = ICPR2,
  196. };
  197. static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
  198. {
  199. int offset = pxa2xx_cp_reg_map[ri->crn];
  200. return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
  201. }
  202. static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
  203. uint64_t value)
  204. {
  205. int offset = pxa2xx_cp_reg_map[ri->crn];
  206. pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
  207. }
  208. #define REGINFO_FOR_PIC_CP(NAME, CRN) \
  209. { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
  210. .access = PL1_RW, .type = ARM_CP_IO, \
  211. .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
  212. static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
  213. REGINFO_FOR_PIC_CP("ICIP", 0),
  214. REGINFO_FOR_PIC_CP("ICMR", 1),
  215. REGINFO_FOR_PIC_CP("ICLR", 2),
  216. REGINFO_FOR_PIC_CP("ICFP", 3),
  217. REGINFO_FOR_PIC_CP("ICPR", 4),
  218. REGINFO_FOR_PIC_CP("ICHP", 5),
  219. REGINFO_FOR_PIC_CP("ICIP2", 6),
  220. REGINFO_FOR_PIC_CP("ICMR2", 7),
  221. REGINFO_FOR_PIC_CP("ICLR2", 8),
  222. REGINFO_FOR_PIC_CP("ICFP2", 9),
  223. REGINFO_FOR_PIC_CP("ICPR2", 0xa),
  224. REGINFO_SENTINEL
  225. };
  226. static const MemoryRegionOps pxa2xx_pic_ops = {
  227. .read = pxa2xx_pic_mem_read,
  228. .write = pxa2xx_pic_mem_write,
  229. .endianness = DEVICE_NATIVE_ENDIAN,
  230. };
  231. static int pxa2xx_pic_post_load(void *opaque, int version_id)
  232. {
  233. pxa2xx_pic_update(opaque);
  234. return 0;
  235. }
  236. DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
  237. {
  238. DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
  239. PXA2xxPICState *s = PXA2XX_PIC(dev);
  240. s->cpu = cpu;
  241. s->int_pending[0] = 0;
  242. s->int_pending[1] = 0;
  243. s->int_enabled[0] = 0;
  244. s->int_enabled[1] = 0;
  245. s->is_fiq[0] = 0;
  246. s->is_fiq[1] = 0;
  247. qdev_init_nofail(dev);
  248. qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
  249. /* Enable IC memory-mapped registers access. */
  250. memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
  251. "pxa2xx-pic", 0x00100000);
  252. sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
  253. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
  254. /* Enable IC coprocessor access. */
  255. define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
  256. return dev;
  257. }
  258. static VMStateDescription vmstate_pxa2xx_pic_regs = {
  259. .name = "pxa2xx_pic",
  260. .version_id = 0,
  261. .minimum_version_id = 0,
  262. .post_load = pxa2xx_pic_post_load,
  263. .fields = (VMStateField[]) {
  264. VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
  265. VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
  266. VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
  267. VMSTATE_UINT32(int_idle, PXA2xxPICState),
  268. VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
  269. VMSTATE_END_OF_LIST(),
  270. },
  271. };
  272. static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
  273. {
  274. DeviceClass *dc = DEVICE_CLASS(klass);
  275. dc->desc = "PXA2xx PIC";
  276. dc->vmsd = &vmstate_pxa2xx_pic_regs;
  277. }
  278. static const TypeInfo pxa2xx_pic_info = {
  279. .name = TYPE_PXA2XX_PIC,
  280. .parent = TYPE_SYS_BUS_DEVICE,
  281. .instance_size = sizeof(PXA2xxPICState),
  282. .class_init = pxa2xx_pic_class_init,
  283. };
  284. static void pxa2xx_pic_register_types(void)
  285. {
  286. type_register_static(&pxa2xx_pic_info);
  287. }
  288. type_init(pxa2xx_pic_register_types)